From: Magnus Damm
Neither the ARM page table code enabled by IOMMU_IO_PGTABLE_LPAE
nor the IPMMU_VMSA driver actually depends on ARM_LPAE, so get
rid of the dependency.
Tested with ipmmu-vmsa on r8a7794 ALT and a kernel config using:
# CONFIG_ARM_LPAE is not set
Signed-off-by: Magnus Damm
Ack
From: Magnus Damm
Introduce a bitmap for context handing and convert the
interrupt routine to go handle all registered contexts.
At this point the number of contexts are still limited.
Also remove the use of the ARM specific mapping variable
from ipmmu_irq() to allow compile on ARM64.
Signed-o
from initial series
- Updated bitmap code locking and also used lighter bitop functions
- Updated the Kconfig bits to apply on top of ARCH_RENESAS
Signed-off-by: Magnus Damm
---
Built on top of next-20160314
drivers/iommu/Kconfig |1
drivers/iommu/ipmmu-vmsa.c | 146
From: Magnus Damm
Make the driver compile on more than just 32-bit ARM
by breaking out and wrapping ARM specific functions
in #ifdefs. Not pretty, but needed to be able to use
the driver on other architectures like ARM64.
Signed-off-by: Magnus Damm
---
Changes since V1:
- Rebased to work wit
From: Magnus Damm
The IPMMU driver is using DT these days, and platform data is no longer
used by the driver. Remove unused code.
Signed-off-by: Magnus Damm
Reviewed-by: Laurent Pinchart
---
Changes since V1:
- Added Reviewed-by from Laurent
drivers/iommu/ipmmu-vmsa.c |5 -
1 file
Hi Laurent,
On Tue, Dec 29, 2015 at 9:14 AM, Laurent Pinchart
wrote:
> Hi Magnus,
>
> Thank you for the patch.
Thanks for your feedback!
> On Tuesday 15 December 2015 21:02:49 Magnus Damm wrote:
>> From: Magnus Damm
>>
>> Introduce a bitmap for context handing and convert the
>> interrupt rout
Hi Peter/Boris/Joerg,
On 3/14/16 23:39, Peter Zijlstra wrote:
On Mon, Mar 14, 2016 at 03:19:45PM +0100, Borislav Petkov wrote:
On Mon, Mar 14, 2016 at 08:37:02PM +0700, Suravee Suthikulpanit wrote:
Basically, we are trying to match the current Perf hierarchy for AMD IOMMU
(arch/x86/events/amd/
On Thu, 2016-02-25 at 08:38 -0600, Bjorn Helgaas wrote:
>
> > /*
> > - * Look for aliases to or from the given device for exisiting groups. The
> > - * dma_alias_devfn only supports aliases on the same bus, therefore the
> > search
> > + * Look for aliases to or from the given device for existi
On Mon, Mar 14, 2016 at 03:19:45PM +0100, Borislav Petkov wrote:
> On Mon, Mar 14, 2016 at 08:37:02PM +0700, Suravee Suthikulpanit wrote:
> > Basically, we are trying to match the current Perf hierarchy for AMD IOMMU
> > (arch/x86/events/amd/iommu.c). I can put it into
> > arch/x86/include/asm/perf
On Mon, Mar 14, 2016 at 08:37:02PM +0700, Suravee Suthikulpanit wrote:
> Basically, we are trying to match the current Perf hierarchy for AMD IOMMU
> (arch/x86/events/amd/iommu.c). I can put it into
> arch/x86/include/asm/perf_amd_iommu.h. What would you prefer?
Yeah, I was going to say the same t
Hi,
On 3/14/16 16:58, Peter Zijlstra wrote:
On Mon, Mar 14, 2016 at 12:26:00PM +0700, Suravee Suthikulpanit wrote:
Hi,
On 03/12/2016 08:22 PM, Peter Zijlstra wrote:
On Tue, Feb 23, 2016 at 08:12:36AM -0600, Suravee Suthikulpanit wrote:
From: Suravee Suthikulpanit
First, this patch move arc
On 13/03/16 22:01, Yong Wu wrote:
In MT8173, Normally the first 1GB PA is for the HW SRAM and Regs,
so the PA will be 33bits if the dram size is 4GB. We have a
"DRAM 4GB mode" toggle bit for this. If it's enabled, from CPU's
point of view, the dram PA will be from 0x1_~0x1_.
In s
On Mon, Mar 14, 2016 at 12:26:00PM +0700, Suravee Suthikulpanit wrote:
> Hi,
>
> On 03/12/2016 08:22 PM, Peter Zijlstra wrote:
> >On Tue, Feb 23, 2016 at 08:12:36AM -0600, Suravee Suthikulpanit wrote:
> >>From: Suravee Suthikulpanit
> >>
> >>First, this patch move arch/x86/events/amd/iommu.h to
>
> -Original Message-
> From: Arnd Bergmann [mailto:a...@arndb.de]
> Sent: Monday, March 14, 2016 6:26 AM
> To: linuxppc-...@lists.ozlabs.org
> Cc: Yangbo Lu; devicet...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; linux-ker...@vger.kernel.org; linux-
> c...@vger.kernel.org; lin
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