This patch-set add MTK 4GB mode support on the Short-Descriptor.
MTK extend the bit9 of the standard pgtable descriptor as the 4GB mode.
We add a special quirk for this.
This two patches are based on Robin's Short-decriptor v3[1], MTK
IOMMU v10[2] and Robin's "Rationalise quirk handling"[3].
[
This patch add 4GB mode support for m4u.
Signed-off-by: Yong Wu
---
In this patch I use the global "max_pfn" to check whether the current
dram size is over 4GB, I am not sure this is proper.
If there is any other suggestions, please let me know.
Thanks.
drivers/iommu/mtk_iommu.c | 14 +
Mediatek extend bit9 in the lvl1 and lvl2 pgtable descriptor of the
Short-descriptor as the 4GB mode in which the dram size will be
over 4GB.
We add a special quirk for this MTK-4GB mode, And in the standard
spec, Bit9 in the lvl1 is "IMPLEMENTATION DEFINED", while it's AP[2]
in the lvl2, therefor
On 02/23/2016 04:19 AM, Robin Murphy wrote:
On 18/02/16 18:29, tchalama...@caviumnetworks.com wrote:
From: Tirumalesh Chalamarla
Due to Errata#27704 CN88xx SMMUv2,supports only shared ASID and VMID
namespaces; specifically within a given node SMMU0 and SMMU1 share,
as does SMMU2 and SMMU3.
On 02/23/2016 04:26 AM, Mark Rutland wrote:
On Thu, Feb 18, 2016 at 10:29:18AM -0800, tchalama...@caviumnetworks.com wrote:
From: Tirumalesh Chalamarla
Due to Errata#27704 CN88xx SMMUv2,supports only shared ASID and VMID
namespaces; specifically within a given node SMMU0 and SMMU1 share,
as
in Summary,
if i change asid-base to cavium,asid-base and still use DT for supplying
base value, is this a solution that will be accepted, of course i will
do range check to see we are not supplying 16bit VMID for 8 bit systems
even though the property now indicates Cavium only.
Thanks,
Tiru
ARM-SMMUv2 supports upto 16 bit VMID. This patch enables
16 bit VMID when HW supports.
Changes from V2:
- Bug fix.
- Removed not needed prints and comments.
changes from V1:
- Remove DT Property and enable 16 bit VMID if ID says.
Signed-off-by: Tirumalesh Chalamarla
---
On 02/23/2016 03:22 AM, Will Deacon wrote:
Hi Tirumalesh,
I still have some questions and comments about this.
On Fri, Feb 19, 2016 at 10:33:33AM -0800, tchalama...@caviumnetworks.com wrote:
From: Tirumalesh Chalamarla
ARM-SMMUv2 supports upto 16 bit VMID. This patch enables
16 bit VMID wh
On Tue, Feb 23, 2016 at 09:26:18AM -0800, Laura Abbott wrote:
> It was an issue with build signing on the testers machine. Once that was
> fixed it was confirmed that the patches did fix the issue.
Btw, Joerg did come up with a minimal fix today:
https://lkml.kernel.org/r/20160223121215.ga31...@8
On 02/22/2016 05:36 PM, Laura Abbott wrote:
On 02/21/2016 05:52 PM, Wan Zongshun wrote:
Original Message
Hi,
Since about 4.4, we've been seeing reports of this warning on every boot
from some users:
WARNING: CPU: 2 PID: 1 at drivers/iommu/amd_iommu_init.c:2301
amd_iommu_pc
This patch adds multi-IOMMU support for perf by exposing
an AMD IOMMU PMU for each IOMMU found in the system via:
/sys/device/amd_iommu_x /* where x is the IOMMU index. */
This allows users to specify different events to be programed
onto performance counters of each IOMMU.
Cc: Peter Zijls
This patch shortens the struct name perf_amd_iommu to perf_iommu since
the old name is too long. The new name should be sufficient since
the structure is only used within this file. We also clean up variable
name for this structure in various functions.
Cc: Borislav Petkov
Signed-off-by: Suravee
This patch cleans up the coding style of this function.
This should not affect the logic and functionality.
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/arch/x86/e
This patch introduces amd_iommu_get_num_iommus(). This is intended for
Perf AMD IOMMU driver.
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/include/asm/perf/amd/iommu.h | 2 ++
drivers/iommu/amd_iommu_init.c| 7 ++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/ar
This is a two-part patch series:
Part1: 1-4 :
Introduce a workaround for the current AMD IOMMU perf initialization issue
in some existing KV and CZ platforms, where it fails to write to IOMMU
perf counter as reported by Andreas Hartmann here
(http://comments.gmane.org/gmane.linux.kernel.pci/49147)
The current amd_iommu_pc_set_reg_val() cann not support multi-IOMMU.
So, this patch rename and modifies them to allow callers to specify
IOMMU index.
The function amd_iommu_pc_get_set_reg_val() is too confusing,
and does not support multi-IOMMU. So, this patch breaks it down
to amd_iommu_pc_[get|s
This patch declare pr_fmt for perf/amd_iommu and remove unnecessary
pr_debug.
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/arch/x86/events/amd/iommu.c b/arch/x86/events/a
This patch contains the follow minor fixup:
* Fixed overflow handling since u64 delta would lose the MSB sign bit.
* Remove unnecessary local64_set().
* Coding style and make use of GENMASK_ULL macro.
Cc: Peter Zijlstra
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x8
This patch cleans up:
* Various bitwise operations in perf_iommu_enable_event
* Make use macros BIT(x)
This should not affect logic and functionality.
Cc: Borislav Petkov
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 12 ++--
1 file changed, 6 insertions(+)
From: Suravee Suthikulpanit
First, this patch move arch/x86/events/amd/iommu.h to
arch/x86/include/asm/perf/amd/iommu.h so that we easily include
it in both perf-amd-iommu and amd-iommu drivers.
Then, we consolidate declaration of AMD IOMMU performance counter
APIs into one file.
Reviewed-by: J
Currently, amd_iommu_pc_get_max_[banks|counters]() use end-point
device ID to locate an IOMMU and check the reported max banks/counters.
The logic assumes that the IOMMU_BASE_DEVID belongs to the first IOMMU,
and uses it to acquire a reference to the first IOMMU, which does not work
on certain syst
Hi Joerg,
Please pull the following arm-smmu updates for 4.6. This lays the
foundations for a functional IOMMU_DOMAIN_DMA for the two drivers,
although we haven't yet thrown the switch since we need to ensure
that the DMA ops all point in the right direction first. Hopefully we'll
get that going f
On Thu, Feb 18, 2016 at 10:29:18AM -0800, tchalama...@caviumnetworks.com wrote:
> From: Tirumalesh Chalamarla
>
> Due to Errata#27704 CN88xx SMMUv2,supports only shared ASID and VMID
> namespaces; specifically within a given node SMMU0 and SMMU1 share,
> as does SMMU2 and SMMU3.
>
> This patch
On 18/02/16 18:29, tchalama...@caviumnetworks.com wrote:
From: Tirumalesh Chalamarla
Due to Errata#27704 CN88xx SMMUv2,supports only shared ASID and VMID
namespaces; specifically within a given node SMMU0 and SMMU1 share,
as does SMMU2 and SMMU3.
This patch tries to address these issuee by su
On Tue, Feb 23, 2016 at 06:39:04PM +0700, Suravee Suthikulpanit wrote:
> Actually, my V5 is rebased from tips which has moved several files.
> I think we might need to create a separate patch series to fix this
> issue in older kernels. Which branch should I rebase my changes for
> the older kernel
On Thu, Feb 18, 2016 at 10:29:18AM -0800, tchalama...@caviumnetworks.com wrote:
> From: Tirumalesh Chalamarla
>
> Due to Errata#27704 CN88xx SMMUv2,supports only shared ASID and VMID
> namespaces; specifically within a given node SMMU0 and SMMU1 share,
> as does SMMU2 and SMMU3.
>
> This patch
On 02/23/2016 06:27 PM, Suravee Suthikulpanit wrote:
Hi,
On 02/23/2016 06:04 PM, Joerg Roedel wrote:
Hi Suravee,
On Thu, Feb 11, 2016 at 04:15:21PM +0700, Suthikulpanit, Suravee wrote:
From: Suravee Suthikulpanit
This patch series modifies the existing perf_event_amd_iommu driver
to suppo
Hi,
On 02/23/2016 06:04 PM, Joerg Roedel wrote:
Hi Suravee,
On Thu, Feb 11, 2016 at 04:15:21PM +0700, Suthikulpanit, Suravee wrote:
From: Suravee Suthikulpanit
This patch series modifies the existing perf_event_amd_iommu driver
to support systems with multiple IOMMUs. It introduces new AMD I
Hi Tirumalesh,
I still have some questions and comments about this.
On Fri, Feb 19, 2016 at 10:33:33AM -0800, tchalama...@caviumnetworks.com wrote:
> From: Tirumalesh Chalamarla
>
> ARM-SMMUv2 supports upto 16 bit VMID. This patch enables
> 16 bit VMID when HW supports.
>
> changes from V1:
>
Hi Suravee,
On Thu, Feb 11, 2016 at 04:15:21PM +0700, Suthikulpanit, Suravee wrote:
> From: Suravee Suthikulpanit
>
> This patch series modifies the existing perf_event_amd_iommu driver
> to support systems with multiple IOMMUs. It introduces new AMD IOMMU APIs,
> which are used by the AMD IOMMU
On 02/23/2016 12:24 PM, Alex Williamson wrote:
On Tue, 23 Feb 2016 12:12:42 +0700
Suravee Suthikulpanit wrote:
Hi
On 02/22/2016 09:07 PM, Peter Zijlstra wrote:
On Mon, Feb 22, 2016 at 03:00:31PM +0700, Suravee Suthikulpanit wrote:
So I really don't have time to review new muck while I'm h
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