[PATCH] intel-iommu: Fix off-by-one in pagetable freeing

2013-12-20 Thread Alex Williamson
dma_pte_free_level() has an off-by-one error when checking whether a pte is completely covered by a range. Take for example the case of attempting to free pfn 0x0 - 0x1ff, ie. 512 entries covering the first 2M superpage. The level_size() is 0x200 and we test: static void dma_pte_free_level(...

Re: [PATCHv7 06/12] ARM: tegra: create a DT header defining SWGROUP ID

2013-12-20 Thread Stephen Warren
On 12/20/2013 05:35 AM, Thierry Reding wrote: > On Wed, Dec 18, 2013 at 09:27:29AM -0700, Stephen Warren wrote: >> On 12/18/2013 01:02 AM, Mark Zhang wrote: >>> On 12/12/2013 03:57 PM, Hiroshi Doyu wrote: Create a header file to define the swgroup IDs used by the IOMMU(SMMU) binding. "swg

Re: [PATCHv7 06/12] ARM: tegra: create a DT header defining SWGROUP ID

2013-12-20 Thread Thierry Reding
On Wed, Dec 18, 2013 at 09:27:29AM -0700, Stephen Warren wrote: > On 12/18/2013 01:02 AM, Mark Zhang wrote: > > On 12/12/2013 03:57 PM, Hiroshi Doyu wrote: > >> Create a header file to define the swgroup IDs used by the IOMMU(SMMU) > >> binding. "swgroup" is a group of H/W clients which a Tegra SoC

[PATCH 1/1] x86/iommu: use bit structures for context_entry

2013-12-20 Thread Li, Zhen-Hua
There is a structure named context_entry used by intel iommu, and there are some bit operations on it. Use bit structure may make these operations easy. Also the function context_set_address_root may cause problem because it uses |= operation, not set the new value. And this patch can fix it. Sig