Re: [PATCH 2/3] AMD IOMMUv2 PC resource management hooks

2013-01-21 Thread Cyrill Gorcunov
On Mon, Jan 21, 2013 at 09:47:30PM +, Kinney, Steven wrote: > Hi Cyrill, > Agree, will clean this up. Yeah, but no rush. Lets wait for other opinions as well. ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/m

Re: [PATCH 2/3] AMD IOMMUv2 PC resource management hooks

2013-01-21 Thread Cyrill Gorcunov
On Mon, Jan 21, 2013 at 02:20:57PM -0600, Steven L. Kinney wrote: > +u8 amd_iommu_v2_get_max_pc_banks(u16 devid) > +{ > + struct amd_iommu *iommu; > + > + /* locate the iommu governing the devid */ > + iommu = amd_iommu_rlookup_table[devid]; > + > + if (iommu) > + return

[PATCH v6 3/4] ARM: mach-shmobile: sh73a0: Add IPMMU device

2013-01-21 Thread Hideki EIRAKU
This patch adds an IPMMU device and notifies the IPMMU driver which devices are connected via the IPMMU module. All devices connected to the main memory bus via the IPMMU module MUST be registered when SHMOBILE_IPMMU and SHMOBILE_IOMMU are enabled because physical address cannot be used while the

[PATCH v6 4/4] ARM: mach-shmobile: r8a7740: Add IPMMU device

2013-01-21 Thread Hideki EIRAKU
This patch adds an IPMMU device and notifies the IPMMU driver which devices are connected via the IPMMU module. All devices connected to the main memory bus via the IPMMU module MUST be registered when SHMOBILE_IPMMU and SHMOBILE_IOMMU are enabled because physical address cannot be used while the

[PATCH v6 1/4] iommu/shmobile: Add iommu driver for Renesas IPMMU modules

2013-01-21 Thread Hideki EIRAKU
This is the Renesas IPMMU driver and IOMMU API implementation. The IPMMU module supports the MMU function and the PMB function. The MMU function provides address translation by pagetable compatible with ARMv6. The PMB function provides address translation including tile-linear translation. This

[PATCH v6 2/4] ARM: mach-shmobile: sh7372: Add IPMMU device

2013-01-21 Thread Hideki EIRAKU
This patch adds an IPMMU device and notifies the IPMMU driver which devices are connected via the IPMMU module. All devices connected to the main memory bus via the IPMMU module MUST be registered when SHMOBILE_IPMMU and SHMOBILE_IOMMU are enabled because physical address cannot be used while the

[PATCH v6 0/4] Renesas IPMMU driver for sh7372, sh73a0 and r8a7740

2013-01-21 Thread Hideki EIRAKU
This is the Renesas IPMMU driver, IOMMU API implementation and IPMMU device support for sh7372 (AP4EVB and Mackerel), sh73a0 and r8a7740. The IPMMU module supports the MMU function and the PMB function. The MMU function provides address translation by pagetable compatible with ARMv6. The PMB fun

RE: [PATCH 2/3] AMD IOMMUv2 PC resource management hooks

2013-01-21 Thread Kinney, Steven
Hi Cyrill, Agree, will clean this up. Thanks -Original Message- From: Cyrill Gorcunov [mailto:gorcu...@gmail.com] On Behalf Of Cyrill Gorcunov Sent: Monday, January 21, 2013 3:32 PM To: Kinney, Steven Cc: Thomas Gleixner; Ingo Molnar; H. Peter Anvin; x...@kernel.org; Joe

[PATCH 3/3] AMD IOMMUv2 PC perf PMU implementation

2013-01-21 Thread Steven L. Kinney
From: "Steven L. Kinney" Implement a perf PMU to handle IOMMUv2 PC perf events. This PMU will handle static counter perf events relative to the AMD IOMMUv2 Performance Counters. To invoke the AMD IOMMUv2 PMU issue a perf tool command such as: ./perf stat -e iommuv2/config=,config1=/u For exa

[PATCH 1/3] AMD x86 quirks: Quirk for enabling IOMMUv2 PC feature

2013-01-21 Thread Steven L. Kinney
From: "Steven L. Kinney" Original code base by Andreas Herrmann at AMD with minor changes. Signed-off-by: Steven L. Kinney --- arch/x86/kernel/quirks.c | 17 + include/linux/pci_ids.h |2 ++ 2 files changed, 19 insertions(+) diff --git a/arch/x86/kernel/quirks.c b/arch/

[PATCH 2/3] AMD IOMMUv2 PC resource management hooks

2013-01-21 Thread Steven L. Kinney
From: "Steven L. Kinney" Add functionality to check the availability of the AMD IOMMUv2 Performance Counters and export this functionality to other core drivers, such as in this case, a perf IOMMUv2 PMU. This feature is not bound to any specific AMD family/model other than the presence of the IO

[PATCH 0/3] AMD IOMMUv2 Performance Counter patches

2013-01-21 Thread Steven L. Kinney
From: "Steven L. Kinney" These patches implement the AMD IOMMUv2.5 Performance Counter functionality via custom perf PMU and implement static counting for various IOMMU translations. The patches address three areas of functionality: 1) Add a PCI quirk for the enablement of IOMMUv2 EFR PC w

[PATCH 0/3] AMD IOMMUv2 Performance Counter patches

2013-01-21 Thread Steven L. Kinney
From: "Steven L. Kinney" These patches implement the AMD IOMMUv2.5 Performance Counter functionality via custom perf PMU and implement static counting for various IOMMU translations. The patches address three areas of functionality: 1) Add a PCI quirk for the enablement of IOMMUv2 EFR PC w

Re: [PATCH 4/6] iommu/tegra: smmu: Support variable MMIO range

2013-01-21 Thread Stephen Warren
On 01/21/2013 12:36 AM, Hiroshi Doyu wrote: > Stephen Warren wrote @ Fri, 18 Jan 2013 17:44:13 > +0100: > >>> Even the checks if "offs" is in some of register blocks could be >>> ifdef'ed out with DEBUG. "smmu->regbase" can be calculated in probe() >>> as below. I don't think that we don't need

[PATCH 13/33] iommu: Convert to devm_ioremap_resource()

2013-01-21 Thread Thierry Reding
Convert all uses of devm_request_and_ioremap() to the newly introduced devm_ioremap_resource() which provides more consistent error handling. devm_ioremap_resource() provides its own error messages so all explicit error messages can be removed from the failure code paths. Signed-off-by: Thierry R