Hi Joerg,
From: Joerg Roedel
Subject: Re: [PATCH 1/2] ARM: IOMMU: Tegra20: Add iommu_ops for GART driver
Date: Mon, 23 Jan 2012 16:00:48 +0100
Message-ID: <20120123150048.gb6...@8bytes.org>
> Hi,
>
> first, some questions about the GART on your platform.
>
> 1) How many GARTs are usually imple
From: "j...@8bytes.org"
Subject: Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver
Date: Tue, 24 Jan 2012 15:25:21 +0100
Message-ID: <20120124142521.ge6...@8bytes.org>
> On Tue, Jan 24, 2012 at 03:46:01PM +0200, Felipe Balbi wrote:
> > On Tue, Jan 24, 2012 at 02:41:21PM +0100, Hi
Hi,
On Mon, Jan 23, 2012 at 11:27 PM, Joerg Roedel wrote:
> Hi,
>
> please also get and inclue Acks from the Exynos maintainer for the next
> post.
> Since I have a compiling config for exynos now I will merge the patches
> when you have the Acks and addressed or explained the issues I pointed
> o
On Tue, Dec 20, 2011 at 09:30:37PM -0700, Alex Williamson wrote:
> On Wed, 2011-12-21 at 14:32 +1100, David Gibson wrote:
> > On Mon, Dec 19, 2011 at 04:41:56PM +0100, Joerg Roedel wrote:
> > > On Mon, Dec 19, 2011 at 11:11:25AM +1100, David Gibson wrote:
> > > > Well.. that's not where it is in Al
On 1/23/2012 6:03 AM, Joerg Roedel wrote:
Hi,
while reviewing another IOMMU driver again I came across a problem in
the IOMMU drivers for OMAP and MSM platforms. In both drivers the
'domain_destroy with devices attached' case isn't handled correctly.
OMAP driver seems not to track the devices a
Hi,
On Tue, Jan 24, 2012 at 02:41:21PM +0100, Hiroshi Doyu wrote:
> From: Joerg Roedel
> Subject: Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver
> Date: Mon, 23 Jan 2012 16:43:10 +0100
> Message-ID: <20120123154310.gc6...@8bytes.org>
>
> > > + }
> > > +
> > > + spin_unlock_ir
On Tue, Jan 24, 2012 at 03:46:01PM +0200, Felipe Balbi wrote:
> On Tue, Jan 24, 2012 at 02:41:21PM +0100, Hiroshi Doyu wrote:
> > Actually I really like the concept of this "domain" now, which hides
> > the H/W hierarchy from users.
> >
> > But in Tegra SMMU/GART case, there's a single one IOMMU d
From: Joerg Roedel
Subject: Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver
Date: Mon, 23 Jan 2012 16:43:10 +0100
Message-ID: <20120123154310.gc6...@8bytes.org>
> > + }
> > +
> > + spin_unlock_irqrestore(&as->lock, flags);
> > +
> > + domain->priv = NULL;
> > + dev_dbg(
From: "joerg.roe...@amd.com"
Subject: Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver
Date: Tue, 24 Jan 2012 12:57:23 +0100
Message-ID: <20120124115723.gc19...@amd.com>
> On Tue, Jan 24, 2012 at 12:36:14PM +0100, Hiroshi Doyu wrote:
> > > A domain is, as you said, a virtual add
On Tue, Jan 24, 2012 at 12:36:14PM +0100, Hiroshi Doyu wrote:
> > A domain is, as you said, a virtual address space for IO devices. But
> > the important point is, an arbitrary number of devices can be part of a
> > domain. This also means that the devices can be behind different
> > hardware SMMUs
From: Joerg Roedel
Subject: Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver
Date: Tue, 24 Jan 2012 12:04:44 +0100
Message-ID: <20120124110444.gb19...@amd.com>
> > > Hmm, this looks like there is a 1-1 mapping between hardware SMMU
> > > devices and domains. This is not consiste
On Tue, Jan 24, 2012 at 10:57:01AM +0100, Hiroshi Doyu wrote:
> > Why do you completly ignore the size parameter in this function (and
> > in the unmap part below)?
> > According to the page-sizes you export to the generic layer size can be
> > 4k or 4M. You need to take care of that in this functi
Hi Joerg,
From: Joerg Roedel
Subject: Re: [PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver
Date: Mon, 23 Jan 2012 16:43:10 +0100
Message-ID: <20120123154310.gc6...@8bytes.org>
> Hi,
>
> please see my comments inline. When you fix these issues I think the
> driver is ready for merg
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