configs may be tested in the coming days.
tested configs:
arc randconfig-001-20250227gcc-13.2.0
arc randconfig-002-20250227gcc-13.2.0
arm randconfig-001-20250227gcc-14.2.0
arm randconfig-002-20250227clang-17
arm
On Fri, Feb 21, 2025 at 04:49:17PM +0100, Piotr Kwapulinski wrote:
> The commit 23c0e5a16bcc ("ixgbe: Add link management support for E610
> device") introduced incorrect media type detection for E610 device. It
> reproduces when advertised speed is modified after driver reload. Clear
> the previou
On Mon, Feb 24, 2025 at 09:59:24PM +0100, Grzegorz Nitka wrote:
> Add E825C 10GbE SGMII device to the list of devices supporting 100Mbit
> link mode. Without that change, 100Mbit link mode is ignored in ethtool
> interface. This change was missed while adding the support for E825C
> devices family.
PTP capabilities are negotiated using virtchnl commands. There are two
available modes of the PTP support: direct and mailbox. When the direct
access to PTP resources is negotiated, virtchnl messages returns a set
of registers that allow read/write directly. When the mailbox access to
PTP resources
This patch series introduces support for Precision Time Protocol (PTP) to
Intel(R) Infrastructure Data Path Function (IDPF) driver. PTP feature is
supported when the PTP capability is negotiated with the Control
Plane (CP). IDPF creates a PTP clock and sets a set of supported
functions.
During the
Add functions to request Tx timestamp for the PTP packets, read the Tx
timestamp when the completion tag for that packet is being received,
extend the Tx timestamp value and set the supported timestamping modes.
Tx timestamp is requested for the PTP packets by setting a TSYN bit and
index value in
Tx timestamp capabilities are negotiated for the uplink Vport.
Driver receives information about the number of available Tx timestamp
latches, the size of Tx timestamp value and the set of indexes used
for Tx timestamping.
Add function to get the Tx timestamp capabilities and parse the uplink
vpor
PTP clock configuration operations - set time, adjust time and adjust
frequency are required to control the clock and maintain synchronization
process.
Extend get PTP capabilities function to request for the clock adjustments
and add functions to enable these actions using dedicated virtchnl
messa
PTP capabilities are negotiated using virtchnl command. Add get
capabilities function, direct access to read the PTP clock time and
direct access to read the cross timestamp - system time and PTP clock
time. Set initial PTP capabilities exposed to the stack.
Reviewed-by: Alexander Lobakin
Reviewe
PTP feature is supported if the VIRTCHNL2_CAP_PTP is negotiated during the
capabilities recognition. Initial PTP support includes PTP initialization
and registration of the clock.
Reviewed-by: Alexander Lobakin
Reviewed-by: Vadim Fedorenko
Reviewed-by: Willem de Bruijn
Signed-off-by: Milena Ole
When the access to read PTP clock is specified as mailbox, the driver
needs to send virtchnl message to perform PTP actions. Message is sent
using idpf_mbq_opc_send_msg_to_peer_drv mailbox opcode, with the parameters
received during PTP capabilities negotiation.
Add functions to recognize PTP mess
Move virtchnl structures to the header file to expose them for the PTP
virtchnl file.
Reviewed-by: Alexander Lobakin
Reviewed-by: Willem de Bruijn
Signed-off-by: Milena Olech
---
v1 -> v2: fix commit message title
.../net/ethernet/intel/idpf/idpf_virtchnl.c | 86 +--
.../net
Add Rx timestamp function when the Rx timestamp value is read directly
from the Rx descriptor. In order to extend the Rx timestamp value to 64
bit in hot path, the PHC time is cached in the receive groups.
Add supported Rx timestamp modes.
Signed-off-by: Milena Olech
---
v7 -> v8: add a function
Since workqueues are created per CPU, the works scheduled to this
workqueues are run on the CPU they were assigned. It may result in
overloaded CPU that is not able to handle virtchnl messages in
relatively short time. Allocating workqueue with WQ_UNBOUND and
WQ_HIGHPRI flags allows scheduler to qu
Assign the ptype extracted from qword to the ptype field of struct
libeth_rqe_info.
Remove the now excess ptype param of idpf_rx_singleq_extract_fields(),
idpf_rx_singleq_extract_base_fields() and
idpf_rx_singleq_extract_flex_fields().
Suggested-by: Alexander Lobakin
Reviewed-by: Przemek Kitszel
On Wed, 26 Feb 2025 19:03:35 +0800 Yunsheng Lin wrote:
> This patchset fix the dma API misuse problem as below:
> Networking driver with page_pool support may hand over page
> still with dma mapping to network stack and try to reuse that
> page after network stack is done with it and passes it back
have been built successfully.
More configs may be tested in the coming days.
tested configs:
alpha allyesconfiggcc-14.2.0
arc randconfig-001-20250227gcc-13.2.0
arc randconfig-002-20250227gcc-13.2.0
arm
On Tue, Feb 25, 2025 at 09:50:21AM +, Simon Horman wrote:
> On Fri, Feb 21, 2025 at 10:39:49AM +0100, Grzegorz Nitka wrote:
> > E82X adapters do not have sequential IDs, lane number is PF ID.
> >
> > Add check for ICE_MAC_GENERIC and skip checking port options.
>
> This I see.
Sorry, this wa
On Tue, Feb 25, 2025 at 02:40:10PM +0100, Martyna Szapar-Mudlaw wrote:
> Fix an issue when firmware logging stops after devlink reload action
> driver_reinit or driver reset. After the driver reinits and resumes
> operations, it must re-request event notifications from the firmware
> as a part of i
Hi Mateusz,
kernel test robot noticed the following build warnings:
[auto build test WARNING on tnguy-next-queue/dev-queue]
url:
https://github.com/intel-lab-lkp/linux/commits/Mateusz-Polchlopek/idpf-assign-extracted-ptype-to-struct-libeth_rqe_info-field/20250227-214755
base: https
E830 supports Earliest TxTime First (ETF) hardware offload, which is
configured via the ETF Qdisc (see tc-etf(8)). ETF introduces a new Tx flow
mechanism that utilizes a timestamp ring (tstamp_ring) alongside the
standard Tx ring. This timestamp ring is used to indicate when hardware
will transmit
Hi Andrew,
On Wed, Feb 26, 2025, at 5:52 PM, Andrew Lunn wrote:
> On Wed, Feb 26, 2025 at 02:44:12PM -0500, Mark Pearson wrote:
>> Issue is seen on some Lenovo desktop workstations where there
>> is a false IRP event which triggers a link flap.
>> Condition is rare and only seen on networks where
Packet buffers (RX + TX) total 64KB. Neither RX or TX buffers can be
larger than 34KB. So divide the buffer equally, 32KB for each.
Co-developed-by: Vinicius Costa Gomes
Signed-off-by: Vinicius Costa Gomes
Signed-off-by: Faizal Rahim
---
drivers/net/ethernet/intel/igc/igc_defines.h | 3 ++-
1
Introduces support for the FPE feature in the IGC driver.
The patches aligns with the upstream FPE API:
https://patchwork.kernel.org/project/netdevbpf/cover/20230220122343.1156614-1-vladimir.olt...@nxp.com/
https://patchwork.kernel.org/project/netdevbpf/cover/20230119122705.73054-1-vladimir.olt...
From: Vladimir Oltean
It appears that stmmac is not the only hardware which requires a
software-driven verification state machine for the MAC Merge layer.
While on the one hand it's good to encourage hardware implementations,
on the other hand it's quite difficult to tolerate multiple drivers
im
Add support to set tx-min-frag-size via set_mm callback in igc.
Increase the max limit of tx-ming-frag-size in ethtool from 252 to 256
since i225/6 value range is 64, 128, 192 and 256.
Co-developed-by: Vinicius Costa Gomes
Signed-off-by: Vinicius Costa Gomes
Signed-off-by: Faizal Rahim
---
dri
Implement "ethtool --show-mm" callback for IGC.
Tested with command:
$ ethtool --show-mm enp1s0.
MAC Merge layer state for enp1s0:
pMAC enabled: on
TX enabled: on
TX active: on
TX minimum fragment size: 64
RX minimum fragment size: 60
Verify enabled: on
Verify time: 128
Max verif
Renamed xdp_get_tx_ring() function to a more generic name for use in
upcoming frame preemption patches.
Signed-off-by: Faizal Rahim
---
drivers/net/ethernet/intel/igc/igc.h | 2 +-
drivers/net/ethernet/intel/igc/igc_main.c | 10 +-
2 files changed, 6 insertions(+), 6 deletions(-)
Since preemptible tc implementation is not ready yet, block it from being
set in taprio. The existing code already blocks it in mqprio.
Signed-off-by: Faizal Rahim
---
drivers/net/ethernet/intel/igc/igc_main.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/net/ethernet/intel/igc
Implemented "ethtool --include-statistics --show-mm" callback for IGC.
Tested preemption scenario to check preemption statistics:
1) Trigger verification handshake on both boards:
$ sudo ethtool --set-mm enp1s0 pmac-enabled on
$ sudo ethtool --set-mm enp1s0 tx-enabled on
$ sudo ethtool
In preparation for supporting frame preemption, when entering TSN mode
set the receive packet buffer to 16KB for the Express MAC, 16KB for
the Preemptible MAC and 2KB for the BMC, according to the datasheet
section 7.1.3.2.
Co-developed-by: Vinicius Costa Gomes
Signed-off-by: Vinicius Costa Gomes
This patch implements the "ethtool --set-mm" callback to trigger the
frame preemption verification handshake.
Uses the MAC Merge Software Verification (mmsv) mechanism in ethtool
to perform the verification handshake for igc.
The structure fpe.mmsv is set by mmsv in ethtool and should remain
read-
> The reason for the module option is I'm playing it safe, as Intel couldn't
> determine root cause.
> The aim of the patch is to keep the effect to a minimum whilst
> allowing users who are impacted to turn on the workaround, if they
> are encountering the issue.
And how do such users determine
> >> + e1e_rphy(hw, PHY_REG(772, 26), &phy_data);
> >
> > Please add some #define for these magic numbers, so we have some idea
> > what PHY register you are actually reading. That in itself might help
> > explain how the workaround actually works.
> >
>
> I don't know what this r
Hello,
syzbot found the following issue on:
HEAD commit:ac9c34d1e45a Merge tag 'for-linus' of git://git.kernel.org..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=10da9db058
kernel config: https://syzkaller.appspot.com/x/.config?x=b1635bf4c5557b92
das
successfully.
More configs may be tested in the coming days.
tested configs:
alpha allyesconfiggcc-14.2.0
arc randconfig-001-20250227gcc-13.2.0
arc randconfig-002-20250227gcc-13.2.0
arm randconfig-001-20250227
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