From: Vinoth Kumar Chandra Mohan
HMC resource initialization is updated to support V1 or V2 approach
based on the FW capability. In the V2 approach, driver receives the
assigned HMC resources count and verifies if it will fit in the given
local memory. If it doesn't fit, the driver load fails.
S
From: Shiraz Saleem
Extend the QP context structure with support for new fields
specific to GEN3 hardware capabilities.
Signed-off-by: Shiraz Saleem
Signed-off-by: Tatyana Nikolova
---
drivers/infiniband/hw/irdma/ctrl.c | 184 +++-
drivers/infiniband/hw/irdma/defs.h
From: Mustafa Ismail
Introduce support for the GEN3 auxiliary core driver, which is
responsible for initializing PCI-level RDMA resources.
Facilitate host-driver communication with the device's Control Plane (CP)
to discover capabilities and perform privileged operations through an
RDMA-specific
From: Shiraz Saleem
Add a new RDMA virtual channel op during QP1 creation that allow the
Control Plane (CP) to virtualize a regular QP as QP1 on non-default
RDMA capable vPorts. Additionally, the CP will return the Qsets to use
on the ib_device of the vPort.
Signed-off-by: Shiraz Saleem
Signed-
From: Joshua Hay
Add the initial idpf_idc.c file with the functions to kick off the IDC
initialization, create and initialize a core RDMA auxiliary device, and
destroy said device.
The RDMA core has a dependency on the vports being created by the
control plane before it can be initialized. There
From: Dave Ertman
To support RDMA for E2000 product, the idpf driver will use the IDC
interface with the irdma auxiliary driver, thus becoming a second
consumer of it. This requires the IDC be updated to support multiple
consumers. The use of exported symbols no longer makes sense because it
will
From: Christopher Bednarz
Discover the hardware register layout for GEN3 devices through an RDMA
virtual channel operation with the Control Plane (CP). Set up the
corresponding hardware attributes specific to GEN3 devices.
Signed-off-by: Christopher Bednarz
Signed-off-by: Tatyana Nikolova
---
From: Krzysztof Czurylo
Plug into the unified HW statistics framework by adding a hardware
statistics map array for GEN3, defining the HW-specific width and
location for each counter in the statistics buffer.
Signed-off-by: Krzysztof Czurylo
Signed-off-by: Tatyana Nikolova
---
drivers/infinib
This patch series is based on 6.14-rc1 and includes both netdev and RDMA
patches for ease of review. It can also be viewed here [1]. A shared pull
request will be sent for patches 1-7 following review.
The patch series introduces RDMA RoCEv2 support for the Intel Infrastructure
Processing Unit (IP
From: Joshua Hay
The only event an RDMA vport aux driver cares about right now is an MTU
change on its underlying vport. Implement and plumb the handler to
signal the pre MTU change event and post MTU change events to the RDMA
vport aux driver.
Signed-off-by: Joshua Hay
Signed-off-by: Tatyana N
From: Joshua Hay
Implement the idpf_idc_request_reset and idpf_idc_rdma_vc_send_sync
callbacks for the rdma core auxiliary driver to issue reset events to
the idpf and send (synchronous) virtchnl messages to the control plane
respectively.
Implement and plumb the reset handler for the opposite f
From: Joshua Hay
Implement the functions to create, initialize, and destroy an RDMA vport
auxiliary device. The vport aux dev creation is dependent on the
core aux device to call idpf_idc_vport_dev_ctrl to signal that it is
ready for vport aux devices. Implement that core callback to either
creat
From: Joshua Hay
Fetch the number of reserved RDMA vectors from the control plane.
Adjust the number of reserved LAN vectors if necessary. Adjust the
minimum number of vectors the OS should reserve to include RDMA; and
fail if the OS cannot reserve enough vectors for the minimum number of
LAN and
From: Shiraz Saleem
Update Kconfig to add dependency on idpf module. Additionally, add
IPU E2000 to list of devices supported.
Signed-off-by: Shiraz Saleem
Signed-off-by: Tatyana Nikolova
---
drivers/infiniband/hw/irdma/Kconfig | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
dif
From: Krzysztof Czurylo
GEN3 introduces asynchronous handling of Control QP (CQP) operations to
minimize head-of-line blocking. Create the CQP using the updated GEN3-
specific descriptor fields and implement the necessary support for this
deferred completion mechanism.
Signed-off-by: Krzysztof C
From: Shiraz Saleem
Extend support for GEN3 devices by programming the necessary hardware
IRQ registers and the updated descriptor fields for the Asynchronous
Event Queue (AEQ) and Completion Event Queue (CEQ). Introduce a RDMA
virtual channel operation with the Control Plane (CP) to associate
in
From: Mustafa Ismail
Refactor the irdma auxiliary driver and associated interfaces out of main.c
and into a standalone GEN2-specific source file and rename as gen_2 driver.
This is in preparation for adding GEN3 auxiliary drivers. Each HW
generation will have its own gen-specific interface file.
From: Shiraz Saleem
Introduce support for 64-byte CQEs in GEN3 devices. Additionally,
implement GEN3-specific CQE opcode decoding.
Signed-off-by: Shiraz Saleem
Signed-off-by: Tatyana Nikolova
---
v3:
* Fix detection of CQ empty when avoid_mem_cflct is on.
* In resize CQ, do not double the CQ
From: Shiraz Saleem
Enhance the CQE error and flush handling specific to GEN3 devices.
Unlike GEN1/2 devices, which depend on software to generate completions
in error, GEN3 devices leverage firmware to generate CQEs in error for
all WQEs posted after a QP moves to an error state.
Key changes in
From: Faisal Latif
Implement verb API and UAPI changes to support SRQ functionality in GEN3
devices.
Signed-off-by: Faisal Latif
Signed-off-by: Tatyana Nikolova
---
v3:
* Clean up SRQ unrelated changes.
* Do not use wqe_idx to get SRQ context in irdma_sc_get_next_aeqe()
because its lower 6 bi
From: Shiraz Saleem
With the deprecation of Memory Window and Timestamping support in GEN2,
move these features to be exclusive to GEN3. This iteration supports
only Type2 Memory Windows. Additionally, it includes the reporting of
the timestamp mask and Host Channel Adapter (HCA) core clock frequ
From: Faisal Latif
Extend irdma to support atomic operations, namely Compare and Swap and
Fetch and Add, for GEN3 devices.
Signed-off-by: Faisal Latif
Signed-off-by: Tatyana Nikolova
---
v3: Check IRDMA_ATOMICS_ALLOWED_BIT after the feature info has been
read from FW.
drivers/infiniband/hw/
From: Mustafa Ismail
In the IPU model, a function can host one or more logical network
endpoints called vPorts. Each vPort may be associated with either a
physical or an internal communication port, and can be RDMA capable. A
vPort features a netdev and, if RDMA capable, must have an associated
i
> -Original Message-
> From: Intel-wired-lan On Behalf Of
> Milena Olech
> Sent: Friday, January 17, 2025 4:41 AM
> To: intel-wired-...@lists.osuosl.org
> Cc: net...@vger.kernel.org; Nguyen, Anthony L
> ; Kitszel, Przemyslaw
> ; Olech, Milena
> Subject: [Intel-wired-lan] [PATCH v5 iwl-n
On Tue, 4 Feb 2025 15:06:17 -0700 Ahmed Zaki wrote:
> Drivers usually need to re-apply the user-set IRQ affinity to their IRQs
> after reset. However, since there can be only one IRQ affinity notifier
> for each IRQ, registering IRQ notifiers conflicts with the ARFS rmap
> management in the core (
From: Joshua Hay
The rdma driver needs to map its own mmio regions for the sake of
performance, meaning the idpf needs to avoid mapping portions of the bar
space. However, to be vendor agnostic, the idpf cannot assume where
these are and must avoid mapping hard coded regions. Instead, the idpf
w
From: Jay Bhat
Implement the necessary support for enabling push on GEN3 devices.
Key Changes:
- Introduce a RDMA virtual channel operation with the Control Plane (CP)
to manage the doorbell/push page which is a privileged operation.
- Implement the MMIO mapping of push pages which adheres to th
arc haps_hs_smp_defconfigclang-19
arc randconfig-001-20250207gcc-13.2.0
arc randconfig-001-20250208gcc-13.2.0
arc randconfig-002-20250207gcc-13.2.0
arc randconfig-002-20250208gcc-13.2.0
Previously control of the dpll SMA/U.FL pins was partially done through
ptp API, decouple pins control from both interfaces (dpll and ptp).
Allow the SMA/U.FL pins control over a dpll subsystem, and leave ptp
related SDP pins control over a ptp subsystem.
Arkadiusz Kubalewski (1):
ice: redesign
From: Karol Kolacinski
Add a description of PTP pins support by the adapters to ice driver
documentation.
Reviewed-by: Milena Olech
Signed-off-by: Karol Kolacinski
Signed-off-by: Arkadiusz Kubalewski
---
.../device_drivers/ethernet/intel/ice.rst | 13 +
1 file changed,
DPLL-enabled E810 NIC driver provides user with list of input and output
pins. Hardware internal design impacts user control over SMA and U.FL
pins. Currently end-user view on those dpll pins doesn't provide any layer
of abstraction. On the hardware level SMA and U.FL pins are tied together
due to
From: Karol Kolacinski
This change aligns E810 PTP pin control to all other products.
Currently, SMA/U.FL port expanders are controlled together with SDP pins
connected to 1588 clock. To align this, separate this control by
exposing only SDP20..23 pins in PTP API on adapters with DPLL.
Clear er
> -Original Message-
> From: Intel-wired-lan On Behalf Of
> Joshua Hay
> Sent: Tuesday, February 4, 2025 6:08 PM
> To: intel-wired-...@lists.osuosl.org
> Cc: Samudrala, Sridhar ; Hay, Joshua A
> ; Chittim, Madhu
> Subject: [Intel-wired-lan] [PATCH iwl-net v2] idpf: call set_real_num_qu
Hello Joe,
I noticed that XDP/ZC busy polling does not work anymore in combination
with igb driver. This seems to be related to commit 5ef44b3cb43b ("xsk:
Bring back busy polling support") which relies on
netif_queue_set_napi().
I see you implemented it for e1000, igc and so on. However, igb is
m
On Thu, Feb 06, 2025 at 04:19:20PM +0100, Piotr Kwapulinski wrote:
> The commit 23c0e5a16bcc ("ixgbe: Add link management support for E610
> device") introduced incorrect checking of media cage presence for E610
> device. Fix it.
>
> Fixes: 23c0e5a16bcc ("ixgbe: Add link management support for E61
On Thu, Feb 06, 2025 at 09:36:55AM +0100, Grzegorz Nitka wrote:
> From: Karol Kolacinski
>
> Minor PTP register refactor, including logical grouping E825C 1-step
> timestamping registers. Remove unused register definitions
> (PHY_REG_GPCS_BITSLIP, PHY_REG_REVISION).
> Also, apply preferred GENMAS
From: Don Skidmore
When an event is detected it is logged and, for the time being, the
queue is immediately re-enabled. This is due to the lack of an API
to the hypervisor so it could deal with it as it chooses.
Reviewed-by: Przemek Kitszel
Reviewed-by: Jedrzej Jagielski
Reviewed-by: Marcin S
From: Slawomir Mrozowicz
Add Tx Hang detection due to an unhandled MDD Event.
Previously, a malicious VF could disable the entire port causing
TX to hang on the E610 card.
Those events that caused PF to freeze were not detected
as an MDD event and usually required a Tx Hang watchdog timer
to cat
Hi,
This patchset is adding support for MDD (malicious driver detection) for
ixgbe driver. It can catch the error on VF side and reset malicious VF.
An MDD event can be triggered for example by sending from VF a TSO packet
with segment number set to 0.
Add checking for Tx hang in case of MDD is
From: Radoslaw Tyl
Modifying SRRCTL register can generate MDD event.
Turn MDD off during SRRCTL register write to prevent generating MDD.
Fix RCT in ixgbe_set_rx_drop_en().
Reviewed-by: Marcin Szycik
Reviewed-by: Przemek Kitszel
Signed-off-by: Radoslaw Tyl
Signed-off-by: Michal Swiatkowski
From: Paul Greenwalt
Add malicious driver detection. Support enabling MDD, disabling MDD,
handling a MDD event, and restoring a MDD VF.
Reviewed-by: Przemek Kitszel
Reviewed-by: Jedrzej Jagielski
Reviewed-by: Marcin Szycik
Signed-off-by: Paul Greenwalt
Signed-off-by: Michal Swiatkowski
---
On Mon, Feb 03, 2025 at 04:03:16PM +0100, Jedrzej Jagielski wrote:
> Add an initial support for devlink interface to ixgbe driver.
>
> Similarly to i40e driver the implementation doesn't enable
> devlink to manage device-wide configuration. Devlink instance
> is created for each physical function
On Thu, Feb 06, 2025 at 09:36:54AM +0100, Grzegorz Nitka wrote:
> From: Karol Kolacinski
>
> Simplify ice_phy_reg_info_eth56g struct definition to include base
> address for the very first quad. Use base address info and 'step'
> value to determine address for specific PHY quad.
>
> Reviewed-by:
On Thu, Feb 06, 2025 at 09:36:53AM +0100, Grzegorz Nitka wrote:
> From: Karol Kolacinski
>
> Implement setting GLTSYN_SYNC_DLAY for E825C products.
> This is the execution delay compensation of SYNC command between
> PHC and PHY.
> Also, refactor the code by changing ice_ptp_init_phc_eth56g funct
On Fri, Feb 07, 2025 at 10:03:45AM +, Simon Horman wrote:
> On Thu, Feb 06, 2025 at 09:36:54AM +0100, Grzegorz Nitka wrote:
> > From: Karol Kolacinski
> >
> > Simplify ice_phy_reg_info_eth56g struct definition to include base
> > address for the very first quad. Use base address info and 'ste
On Fri, Feb 07, 2025 at 09:38:41AM +0100, Kurt Kanzenbach wrote:
> Hello Joe,
>
> I noticed that XDP/ZC busy polling does not work anymore in combination
> with igb driver. This seems to be related to commit 5ef44b3cb43b ("xsk:
> Bring back busy polling support") which relies on
> netif_queue_set_
On Thu, Feb 06, 2025 at 11:30:23PM +0100, Przemek Kitszel wrote:
> GCC 7 is not as good as GCC 8+ in telling what is a compile-time
> const, and thus could be used for static storage.
> Fortunately keeping strings as const arrays is enough to make old
> gcc happy.
>
> Excerpt from the report:
> My
On Fri, Feb 07, 2025 at 11:43:42AM +0100, Michal Swiatkowski wrote:
> From: Slawomir Mrozowicz
>
> Add Tx Hang detection due to an unhandled MDD Event.
>
> Previously, a malicious VF could disable the entire port causing
> TX to hang on the E610 card.
> Those events that caused PF to freeze were
On Fri, Feb 07, 2025 at 11:43:40AM +0100, Michal Swiatkowski wrote:
> From: Paul Greenwalt
>
> Add malicious driver detection. Support enabling MDD, disabling MDD,
> handling a MDD event, and restoring a MDD VF.
>
> Reviewed-by: Przemek Kitszel
> Reviewed-by: Jedrzej Jagielski
> Reviewed-by: M
On Wed, Feb 05, 2025 at 08:45:46PM +, Simon Horman wrote:
> I ran into a similar problem not so long ago and I'm wondering if
> the following, based on a suggestion by Jiri Slaby, resolves your
> problem.
>
> diff --git a/drivers/net/ethernet/intel/ice/devlink/health.c
> b/drivers/net/etherne
Renamed xdp_get_tx_ring() function to a more generic name for use in
upcoming frame preemption patches.
Signed-off-by: Faizal Rahim
---
drivers/net/ethernet/intel/igc/igc.h | 2 +-
drivers/net/ethernet/intel/igc/igc_main.c | 10 +-
2 files changed, 6 insertions(+), 6 deletions(-)
From: Vladimir Oltean
It appears that stmmac is not the only hardware which requires a
software-driven verification state machine for the MAC Merge layer.
While on the one hand it's good to encourage hardware implementations,
on the other hand it's quite difficult to tolerate multiple drivers
im
This patch implements the "ethtool --set-mm" callback to trigger the
frame preemption verification handshake.
Uses the MAC Merge Software Verification (mmsv) mechanism in ethtool
to perform the verification handshake for igc.
The structure fpe.mmsv is set by mmsv in ethtool and should remain
read-
Packet buffers (RX + TX) total 64KB. Neither RX or TX buffers can be
larger than 34KB. So divide the buffer equally, 32KB for each.
Co-developed-by: Vinicius Costa Gomes
Signed-off-by: Vinicius Costa Gomes
Signed-off-by: Faizal Rahim
---
drivers/net/ethernet/intel/igc/igc_defines.h | 3 ++-
1
In preparation for supporting frame preemption, when entering TSN mode
set the receive packet buffer to 16KB for the Express MAC, 16KB for
the Preemptible MAC and 2KB for the BMC, according to the datasheet
section 7.1.3.2.
Co-developed-by: Vinicius Costa Gomes
Signed-off-by: Vinicius Costa Gomes
Introduces support for the FPE feature in the IGC driver.
The patches aligns with the upstream FPE API:
https://patchwork.kernel.org/project/netdevbpf/cover/20230220122343.1156614-1-vladimir.olt...@nxp.com/
https://patchwork.kernel.org/project/netdevbpf/cover/20230119122705.73054-1-vladimir.olt...
Set queue as preemptible or express via taprio.
This will eventually set queue-specific preemptible field in TXQCTL
register.
Implement configure_tx(), a callback triggered by mmsv, to set tx_enabled
and update preemptible queue settings. tx_enabled is a new field that
serves as a condition in igc
Add support to set tx-min-frag-size via set_mm callback in igc.
Increase the max limit of tx-ming-frag-size in ethtool from 252 to 256
since i225/6 value range is 64, 128, 192 and 256.
Co-developed-by: Vinicius Costa Gomes
Signed-off-by: Vinicius Costa Gomes
Signed-off-by: Faizal Rahim
---
dri
Implement "ethtool --show-mm" callback for IGC.
Tested with command:
$ ethtool --show-mm enp1s0.
MAC Merge layer state for enp1s0:
pMAC enabled: on
TX enabled: on
TX active: on
TX minimum fragment size: 64
RX minimum fragment size: 60
Verify enabled: on
Verify time: 128
Max verif
On 6/2/2025 11:04 pm, Vladimir Oltean wrote:
On Thu, Feb 06, 2025 at 10:40:11PM +0800, Abdul Rahim, Faizal wrote:
Hi Vladimir,
Thanks for the quick review, appreciate your help.
On 6/2/2025 1:12 am, Vladimir Oltean wrote:
On Wed, Feb 05, 2025 at 05:05:20AM -0500, Faizal Rahim wrote:
This
Implemented "ethtool --include-statistics --show-mm" callback for IGC.
Tested preemption scenario to check preemption statistics:
1) Trigger verification handshake on both boards:
$ sudo ethtool --set-mm enp1s0 pmac-enabled on
$ sudo ethtool --set-mm enp1s0 tx-enabled on
$ sudo ethtool
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