> Here the same thing. The 802.1ad bridge has the same PVID on all ports.
> Why does the FDB lookup have to be as complex as to take 2 VIDs into
> consideration, instead of just the inner one?
In all my examples I'm using the same PVID, because that's a required
condition for the issue to happen.
Song Yoong Siang writes:
> Improve XDP_SETUP_PROG process by avoiding unnecessary link down/up event
> and hardware device reset.
>
Some examples of problems that these hardware resets are causing would
be good.
> Signed-off-by: Song Yoong Siang
> ---
The duplication of code doesn't look that
On Thursday, December 5, 2024 8:38 AM, Gomes, Vinicius
wrote:
>Song Yoong Siang writes:
>
>> Improve XDP_SETUP_PROG process by avoiding unnecessary link down/up event
>> and hardware device reset.
>>
>
>Some examples of problems that these hardware resets are causing would
>be good.
>
Sure, may
> What stops you from changing the 802.1ad bridge port pvids to unique
> values, like 3, 4, 5... instead of 3, 3, 3, and making each other
> j != i bridge port be a non-pvid member of port i's pvid?
I'm not sure if I understand this suggestion.
I tried to draw out what you described here:
https:/
On Wed, Dec 04, 2024 at 12:37:24AM -0800, Andrew Strohman wrote:
> > What stops you from changing the 802.1ad bridge port pvids to unique
> > values, like 3, 4, 5... instead of 3, 3, 3, and making each other
> > j != i bridge port be a non-pvid member of port i's pvid?
>
> I'm not sure if I unders
On 11/5/24 06:47, Przemek Kitszel wrote:
On 10/31/24 22:14, Rosen Penev wrote:
The latter is the preferred way to copy ethtool strings.
Avoids manually incrementing the pointer. Cleans up the code quite well.
Signed-off-by: Rosen Penev
---
v3: change custom get_strings to u8** to make sure
HW can have different input/output delays for each of the pins.
Currently, only E82X adapters have delay compensation based on TSPLL
config and E810 adapters have constant 1 ms compensation, both cases
only for output delays and the same one for all pins.
E825 adapters have different delays for S
> I didn't say "tagged". I just said "not PVID". There are 2 independent
> bridge VLAN attributes: "pvid" and [egress-]"untagged". I am suggesting
> that packets in VID 3, 4, 5 all exit the 802.1ad bridge untagged, but
> every bridge port has a unique PVID from this range.
>
> bridge vlan add dev p
On 12/3/24 21:28, Gerhard Engleder wrote:
From: Gerhard Engleder
From: Gerhard Engleder
duplicated From: line
Link down and up triggers update of MTA table. This update executes many
PCIe writes and a final flush. Thus, PCIe will be blocked until all writes
are flushed. As a result, DMA t
On Wed, Dec 04, 2024 at 02:12:18AM -0800, Andrew Strohman wrote:
> > I didn't say "tagged". I just said "not PVID". There are 2 independent
> > bridge VLAN attributes: "pvid" and [egress-]"untagged". I am suggesting
> > that packets in VID 3, 4, 5 all exit the 802.1ad bridge untagged, but
> > every
This is the second attempt at fixing the behavior of igb_msix_other()
for PREEMPT_RT. The previous attempt [1] was reverted [2] following
concerns raised by Sebastian [3].
The initial approach proposed converting vfs_lock to a raw_spinlock,
a minor change intended to make it safe. However, it beca
>From the perspective of PREEMPT_RT, igb_msg_task() invokes functions
that are a mix of IRQ-safe and non-IRQ-safe operations.
To address this, we separate igb_msg_task() into distinct IRQ-safe and
preemptible-safe components. This is a preparatory step for upcoming
commits, where the igb_msix_othe
During testing of SR-IOV, Red Hat QE encountered an issue where the
ip link up command intermittently fails for the igbvf interfaces when
using the PREEMPT_RT variant. Investigation revealed that
e1000_write_posted_mbx returns an error due to the lack of an ACK
from e1000_poll_for_ack.
The underly
This change adds a raw_spinlock for the vfs_lock to the
igb_adapter structure, enabling its use in both interrupt and
preemptible contexts. This is essential for upcoming modifications
to split igb_msg_task() into interrupt-safe and preemptible-safe
parts.
The motivation for this change stems from
The adapter->vfs_lock currently protects critical sections shared between
igb_disable_sriov() and igb_msg_task(). Since igb_msg_task() — which is
invoked solely by the igb_msix_other() ISR—only proceeds when
adapter->vfs_allocated_count > 0, we can reduce the lock scope further.
By moving the assi
Improve XDP_SETUP_PROG process by avoiding unnecessary link down/up event
and hardware device reset.
Signed-off-by: Song Yoong Siang
---
drivers/net/ethernet/intel/igc/igc.h | 2 +
drivers/net/ethernet/intel/igc/igc_main.c | 138 ++
drivers/net/ethernet/intel/igc/igc_x
Firmware generates events for global events or port specific events.
Driver shall subscribe for health status events from firmware on supported
FW versions >= 1.7.6.
Driver shall expose those under specific health reporter, two new
reporters are introduced:
- FW health reporter shall represent glo
Dear Konrad,
Thank you for your patch. It’d be great if you made the commit message
summary/title a statement by adding a verb (in imperative mood). Maybe:
ice: Support for fw and port health status
Am 04.12.24 um 13:27 schrieb Konrad Knitter:
Firmware generates events for global events or
[Cc: -Brett, -Nicholas (550 #5.1.0 Address rejected.)]
Am 04.12.24 um 13:34 schrieb Paul Menzel:
Dear Konrad,
Thank you for your patch. It’d be great if you made the commit message
summary/title a statement by adding a verb (in imperative mood). Maybe:
ice: Support for fw and port health st
ptp4l application reports too high offset when ran on E823 device
with a 100GB/s link. Those values cannot go under 100ns, like in a
working case when using 100 GB/s cable.
This is due to incorrect frequency settings on the PHY clocks for
100 GB/s speed. Changes are introduced to align with the in
Add initial support for Intel(R) E610 Series of network devices. The E610
is based on X550 but adds firmware managed link, enhanced security
capabilities and support for updated server manageability.
This patch series adds low level support for the following features and
enables link management.
Add low level support for Admin Command Interface (ACI). ACI is the
Firmware interface used by a driver to communicate with E610 adapter. Add
the following ACI features:
- data structures, macros, register definitions
- commands handling
- events handling
Co-developed-by: Stefan Wegrzyn
Signed-of
Add low level support for E610 device capabilities detection. The
capabilities are discovered via the Admin Command Interface. Discover the
following capabilities:
- function caps: vmdq, dcb, rss, rx/tx qs, msix, nvm, orom, reset
- device caps: vsi, fdir, 1588
- phy caps
Co-developed-by: Stefan We
Add low level support for accessing NVM in E610 device. NVM operations are
handled via the Admin Command Interface. Add the following NVM specific
operations:
- acquire, release, read
- validate checksum
- read shadow ram
Co-developed-by: Stefan Wegrzyn
Signed-off-by: Stefan Wegrzyn
Co-developed
Add low level link management support for E610 device. Link management
operations are handled via the Admin Command Interface. Add the following
link management operations:
- get link capabilities
- set up link
- get media type
- get link status, link status events
- link power management
Co-devel
Add low level support for EEPROM dump for the specified network device.
Co-developed-by: Stefan Wegrzyn
Signed-off-by: Stefan Wegrzyn
Signed-off-by: Piotr Kwapulinski
---
drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c | 93 +++
drivers/net/ethernet/intel/ixgbe/ixgbe_e610.h | 5
Required to adopt x540 specific functions by E610 device.
Signed-off-by: Piotr Kwapulinski
Reviewed-by: Simon Horman
---
drivers/net/ethernet/intel/ixgbe/ixgbe_x540.h | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.h
b/drive
Required for enabling the link management in E610 device.
Reviewed-by: Simon Horman
Signed-off-by: Piotr Kwapulinski
---
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 17 +++--
drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c | 12 ++--
2 files changed, 17 insertions(+), 12 d
Add high level link management support for E610 device. Enable the
following features:
- driver load
- bring up network interface
- IP address assignment
- pass traffic
- show statistics (e.g. via ethtool)
- disable network interface
- driver unload
Co-developed-by: Carolyn Wyborny
Signed-off-by:
clang-20
arcrandconfig-001gcc-13.2.0
arc randconfig-001-20241204clang-14
arc randconfig-001-20241204gcc-13.2.0
arcrandconfig-002gcc-13.2.0
arc randconfig-002-20241204
randconfig-001clang-20
arc randconfig-001-20241204clang-14
arc randconfig-001-20241204gcc-13.2.0
arcrandconfig-002clang-20
arc randconfig-002-20241204clang-14
arc randconfig-002-20241204
-20241204clang-14
arcrandconfig-002clang-20
arc randconfig-002-20241204clang-14
arm allmodconfigclang-20
arm allnoconfiggcc-14.2.0
arm allyesconfig
-20241204clang-14
arcrandconfig-002clang-20
arc randconfig-002-20241204clang-14
arm allmodconfigclang-20
arm allnoconfiggcc-14.2.0
arm allyesconfig
static_assert() needs to be placed in the declaration section,
so move it there in ice_cfg_tx_topo() function.
Current code causes following warnings on some gcc versions:
error: ISO C90 forbids mixed declarations and code
[-Werror=declaration-after-statement]
Fixes: c188afdc3611 ("ice: fix memle
Dear Mateusz,
Thank you for the patch.
Am 04.12.24 um 16:02 schrieb Mateusz Polchlopek:
static_assert() needs to be placed in the declaration section,
so move it there in ice_cfg_tx_topo() function.
Current code causes following warnings on some gcc versions:
Please list the versions you kn
Programming the PHY registers in preparation for an increment value change
or a timer adjustment on E810 requires issuing Admin Queue commands for
each PHY register. It has been found that the firmware Admin Queue
processing occasionally has delays of tens or rarely up to hundreds of
milliseconds.
From: Jacob Keller
Newer firmware for the E810 devices support a 'low latency' interface to
interact with the PHY without using the Admin Queue. This is interacted
with via the REG_LL_PROXY_L and REG_LL_PROXY_H registers.
Currently, this interface is only used for Tx timestamps. There are two
di
From: Jacob Keller
Programming the PHY registers in preparation for an increment value change
or a timer adjustment on E810 requires issuing Admin Queue commands for
each PHY register. It has been found that the firmware Admin Queue
processing occasionally has delays of tens or rarely up to hundr
From: Jacob Keller
The TS_LL_READ macros are used as part of the low latency Tx timestamp
interface. A future firmware extension will add support for performing PHY
timer updates over this interface. Using TS_LL_READ as the prefix for these
macros will be confusing once the interface is used for
From: Jacob Keller
Newer versions of firmware support programming the PHY timer via the low
latency interface exposed over REG_LL_PROXY_L and REG_LL_PROXY_H. Add
support for checking the device capabilities for this feature.
Co-developed-by: Karol Kolacinski
Signed-off-by: Karol Kolacinski
Sig
From: Jacob Keller
The ice_read_phy_tstamp_ll_e810 function repeatedly reads the PF_SB_ATQBAL
register until the TS_LL_READ_TS bit is cleared. This is a perfect
candidate for using rd32_poll_timeout. However, the default implementation
uses a sleep-based wait.
Add a new rd32_poll_timeout_atomic
Hi Piotr,
kernel test robot noticed the following build warnings:
[auto build test WARNING on tnguy-next-queue/dev-queue]
url:
https://github.com/intel-lab-lkp/linux/commits/Piotr-Kwapulinski/ixgbe-Add-support-for-E610-FW-Admin-Command-Interface/20241204-223603
base: https
On 12/4/24 15:31, Piotr Kwapulinski wrote:
Add low level support for EEPROM dump for the specified network device.
Co-developed-by: Stefan Wegrzyn
Signed-off-by: Stefan Wegrzyn
Signed-off-by: Piotr Kwapulinski
---
drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c | 93 +++
driv
On 04.12.24 11:10, Przemek Kitszel wrote:
On 12/3/24 21:28, Gerhard Engleder wrote:
From: Gerhard Engleder
From: Gerhard Engleder
duplicated From: line
Nervous fingers, sorry, will be fixed.
Link down and up triggers update of MTA table. This update executes many
PCIe writes and a fina
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue.git main
branch HEAD: bb18265c3aba92b91a1355609769f3e967b65dee r8169: remove support
for chip version 11
elapsed time: 1619m
configs tested: 209
configs skipped: 8
The following configs have been built successfully.
45 matches
Mail list logo
