Fri, Apr 12, 2024 at 08:30:49AM CEST, michal.swiatkow...@linux.intel.com wrote:
>From: Piotr Raczynski
>
>Implement devlink port handlers responsible for ethernet type devlink
>subfunctions. Create subfunction devlink port and setup all resources
>needed for a subfunction netdev to operate. Config
Fri, Apr 12, 2024 at 08:30:51AM CEST, michal.swiatkow...@linux.intel.com wrote:
>From: Piotr Raczynski
>
>Implement subfunction driver. It is probe when subfunction port is
>activated.
>
>VSI is already created. During the probe VSI is being configured.
>MAC unicast and broadcast filter is added t
Fri, Apr 12, 2024 at 08:30:52AM CEST, michal.swiatkow...@linux.intel.com wrote:
>From: Piotr Raczynski
>
>Configure netdevice for subfunction usecase. Mostly it is reusing ops
>from the PF netdevice.
>
>SF netdev is linked to devlink port registered after SF activation.
>
>Signed-off-by: Piotr Rac
Fri, Apr 12, 2024 at 08:30:50AM CEST, michal.swiatkow...@linux.intel.com wrote:
>From: Piotr Raczynski
>
>Make devlink allocation function generic to use it for PF and for SF.
>
>Add function for SF devlink port creation. It will be used in next
>patch.
>
>Create header file for subfunction device
gcc
i386 allyesconfig gcc
i386 buildonly-randconfig-001-20240412 gcc
i386 buildonly-randconfig-002-20240412 clang
i386 buildonly-randconfig-003-20240412 gcc
i386 buildonly-randconfig-004-20240412 gcc
i386 buildonly-rand
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/tnguy/net-queue.git dev-queue
branch HEAD: f990a8a3833acaeb38f976ffa8fd90d136a9d810 ice: Fix checking for
unsupported keys on non-tunnel device
elapsed time: 998m
configs tested: 95
configs skipped: 3
The following configs have been
> -Original Message-
> From: Intel-wired-lan On Behalf Of
> Dariusz Aftanski
> Sent: Friday, March 8, 2024 4:29 PM
> To: intel-wired-...@lists.osuosl.org
> Cc: net...@vger.kernel.org; Dariusz Aftanski
> ; Michal Swiatkowski
>
> Subject: [Intel-wired-lan] [iwl-next v1] ice: Remove
> ndo_ge
allmodconfig gcc
arc allnoconfig gcc
arc allyesconfig gcc
arc defconfig gcc
arc randconfig-001-20240412 gcc
arc randconfig-002-20240412 gcc
On 4/12/24 08:30, Michal Swiatkowski wrote:
From: Piotr Raczynski
Implement subfunction driver. It is probe when subfunction port is
activated.
VSI is already created. During the probe VSI is being configured.
MAC unicast and broadcast filter is added to allow traffic to pass.
Signed-off-by:
gcc
arc allnoconfig gcc
arc allyesconfig gcc
arc defconfig gcc
arc randconfig-001-20240412 gcc
arc randconfig-002-20240412 gcc
arm
E825C products have a different PHY model than E822, E823 and E810 products.
This PHY is ETH56G and its support is necessary to have functional PTP stack
for E825C products.
Grzegorz Nitka (2):
ice: Add NAC Topology device capability parser
ice: Adjust PTP init for 2x50G E825C devices
Jacob K
Create new ice_ptp_hw struct and use it for all HW and PTP-related
fields from struct ice_hw.
Replace definitions with struct fields, which values are set accordingly
to a specific device.
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
V4 -> V
From: Jacob Keller
Multiple places in the driver code need to convert enum ice_ptp_tmr_cmd
values into register bits for both the main timer and the PHY port
timers. The main MAC register has one bit scheme for timer commands,
while the PHY commands use a different scheme.
The E810 and E830 devi
From: Jacob Keller
Add a new helper for getting base clock increment value for specific HW.
Signed-off-by: Jacob Keller
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
V4 -> V5: Removed unused UNKNOWN_INCVAL_E82X
drivers/net/ethernet/intel
From: Sergey Temerkhanov
Introduce functions enabling/disabling Tx TS interrupts
for the E822 and ETH56G PHYs
Signed-off-by: Sergey Temerkhanov
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
V5 -> V6: Adjusted return in ice_phy_cfg_intr_e82
From: Sergey Temerkhanov
Move CGU block to the beginning of ice_ptp_hw.c
Signed-off-by: Sergey Temerkhanov
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
V7 -> V8: brought back P_REG_40B_HIGH_S due to 32 bit compatibility issue
V6 -> V7: -
Add a possibility to mark all transmitted/received timestamps as invalid
by clearing PHY OFFSET_READY registers.
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
drivers/net/ethernet/intel/ice/ice_ptp.c| 11 ---
drivers/net/ethernet/int
From: Sergey Temerkhanov
E825C products feature a new PHY model - ETH56G.
Introduces all necessary PHY definitions, functions etc. for ETH56G PHY,
analogous to E82X and E810 ones with addition of a few HW-specific
functionalities for ETH56G like one-step timestamping.
It ensures correct PTP ini
Simplify the code by using anonymous struct in CGU registers instead of
naming each structure 'field'.
Suggested-by: Przemek Kitszel
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
drivers/net/ethernet/intel/ice/ice_cgu_regs.h | 12 ++---
dri
From: Michal Michalik
The CGU layout of E825-C is a little different than E822/E823. Add
support the new hardware adding relevant functions.
Signed-off-by: Michal Michalik
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
V4 -> V5: added UL to
From: Grzegorz Nitka
Add new device capability ICE_AQC_CAPS_NAC_TOPOLOGY which allows to
determine the mode of operation (1 or 2 NAC).
Define a new structure to store data from new capability and
corresponding parser code.
Co-developed-by: Prathisna Padmasanan
Signed-off-by: Prathisna Padmasana
There are E825C products featuring 2 NACs. Those have only one source
clock on the primary NAC.
For those devices, there
should be only one clock controller on the primary NAC. All PFs from
both NACs should connect as auxiliary devices to the auxiliary driver on
the primary NAC.
Reviewed-by: Igor
From: Grzegorz Nitka
>From FW/HW perspective, 2 port topology in E825C devices requires
merging of 2 port mapping internally and breakout mapping externally.
As a consequence, it requires different port numbering from PTP code
perspective.
For that topology, pf_id can not be used to index PTP por
On 09.04.2024 15:39, Andrew Lunn wrote:
>> This is something my current design supports I think. Using
>> ETHTOOL_A_MODULE_MAX_POWER_SET user can get what cage supports
>> and change it.
>
>> This could be done using ethtool_module_power_mode_policy I think.
>
> All these 'I think' don't give
> -Original Message-
> From: Intel-wired-lan On Behalf Of Ivan
> Vecera
> Sent: Wednesday, March 27, 2024 1:28 PM
> To: intel-wired-...@lists.osuosl.org
> Cc: net...@vger.kernel.org; linux-ker...@vger.kernel.org; Loktionov,
> Aleksandr ; eduma...@google.com; Nguyen,
> Anthony L ; k...@k
Fri, Mar 08, 2024 at 11:58:42AM CET, dariusz.aftan...@linux.intel.com wrote:
>ndo_get_phys_port_name is never actually used, as in switchdev
>devklink is always being created.
>
>Reviewed-by: Michal Swiatkowski
>Signed-off-by: Dariusz Aftanski
Reviewed-by: Jiri Pirko
gcc
arc allnoconfig gcc
arc allyesconfig gcc
arc defconfig gcc
arc randconfig-001-20240412 gcc
arc randconfig-002-20240412 gcc
On 3/27/2024 12:57 AM, Ivan Vecera wrote:
This series do following:
Patch 1 - Removes write-only flags field from i40e_veb structure and
from i40e_veb_setup() parameters
Patch 2 - Refactors parameter of i40e_notify_client_of_l2_param_changes()
and i40e_notify_client_of_ne
Implementation to dump PHY configuration and FEC statistics to
facilitate link level debugging of customer issues. Implementation has
two parts
a. Serdes equalization
# ethtool -d eth0
Output:
Offset Values
-- --
0x:
Current driver implementation for Sideband Queue supports
a fixed flag (ICE_AQ_FLAG_RD). To retrieve FEC statistics from firmware
Sideband Queue command is used with a different flag.
Extend API for Sideband Queue command to use 'flag' as input argument.
Reviewed-by: Jesse Brandeburg
Signed-off-
Some phy configurations such as serdes equalizer parameters, are applied
per serdes lane. Hence firmware requires serdes lane number to read
serdes equalizer values. Similarly firmware requires PCS quad number
and PCS port number to read FEC statistics. Current driver
implementation does not mainta
To debug link issues in the field, it is paramount to
dump fec corrected/uncorrected block counts from firmware.
Extend ethtool option '--show-fec' to support fec statistics.
The IEEE standard mandates two sets of counters:
- 30.5.1.1.17 aFECCorrectedBlocks
- 30.5.1.1.18 aFECUncorrectableBlocks
To debug link issues in the field, serdes Tx/Rx equalizer values
help to determine the health of serdes lane.
Extend 'ethtool -d' option to dump serdes Tx/Rx equalizer.
The following list of equalizer param is supported
a. rx_equalization_pre2
b. rx_equalization_pre1
c. rx_equalization_post1
d. rx
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