On Thu, Apr 04, 2024 at 06:03:02PM +0200, Alexander Lobakin wrote:
> Structures which are about to be copied to userspace shouldn't have
> uninitialized fields or paddings.
> memset() the whole &ip_tunnel_parm in ip_tunnel_parm_to_user() before
> filling it with the kernel data. The compilers will
> -Original Message-
> From: Intel-wired-lan On Behalf Of
> Lukasz Plachno
> Sent: Wednesday, April 3, 2024 3:54 PM
> To: intel-wired-...@lists.osuosl.org
> Cc: pmen...@molgen.mpg.de; brett.cree...@amd.com; net...@vger.kernel.org;
> Lobakin, Aleksander ; Plachno, Lukasz
> ; ho...@kernel
> -Original Message-
> From: Intel-wired-lan On Behalf Of
> Lukasz Plachno
> Sent: Wednesday, April 3, 2024 3:54 PM
> To: intel-wired-...@lists.osuosl.org
> Cc: pmen...@molgen.mpg.de; brett.cree...@amd.com; net...@vger.kernel.org;
> Buchocki, JakubX ; Lobakin, Aleksander
> ; Plachno, Lu
From: Przemek Kitszel
Date: Fri, 5 Apr 2024 12:32:55 +0200
> On 4/4/24 17:44, Alexander Lobakin wrote:
>> Add a couple intuitive helpers to hide Rx buffer implementation details
[...]
>> +struct libeth_fqe {
>> + struct page *page;
>> + u32 offset;
>> + u32
From: Jakub Kicinski
Date: Fri, 5 Apr 2024 21:25:13 -0700
> On Thu, 4 Apr 2024 17:44:00 +0200 Alexander Lobakin wrote:
>> +/**
>> + * struct libeth_fq - structure representing a buffer queue
>> + * @fp: hotpath part of the structure
>
> Second time this happens this week, so maybe some tooling
From: Alexander Lobakin
Date: Mon, 8 Apr 2024 11:11:12 +0200
> From: Jakub Kicinski
> Date: Fri, 5 Apr 2024 21:25:13 -0700
>
>> On Thu, 4 Apr 2024 17:44:00 +0200 Alexander Lobakin wrote:
>>> +/**
>>> + * struct libeth_fq - structure representing a buffer queue
>>> + * @fp: hotpath part of the
Hello:
This patch was applied to netdev/net-next.git (main)
by David S. Miller :
On Thu, 4 Apr 2024 18:03:02 +0200 you wrote:
> Structures which are about to be copied to userspace shouldn't have
> uninitialized fields or paddings.
> memset() the whole &ip_tunnel_parm in ip_tunnel_parm_to_user()
Hi,
This is second patchset split from subfunction patchset [1].
Important changes from previous version:
* remove unnecessary checks for devlink port type
* link correct devlink port to subfunction netdev
Follow up patchset with subfunction port representor will be the last
patchset for subfun
From: Piotr Raczynski
Add required plumbing for new VSI type dedicated to devlink subfunctions.
Make sure that the vsi is properly configured and destroyed. Also allow
loading XDP and AF_XDP sockets.
The first implementation of devlink subfunctions supports only one Tx/Rx
queue pair per given su
From: Piotr Raczynski
Make some of the netdevice_ops functions visible from outside for
another VSI type created netdev.
Reviewed-by: Przemek Kitszel
Reviewed-by: Wojciech Drewek
Signed-off-by: Piotr Raczynski
Signed-off-by: Michal Swiatkowski
---
drivers/net/ethernet/intel/ice/ice.h |
From: Piotr Raczynski
Implement devlink port handlers responsible for ethernet type devlink
subfunctions. Create subfunction devlink port and setup all resources
needed for a subfunction netdev to operate. Configure new VSI for each
new subfunction, initialize and configure interrupts and Tx/Rx r
From: Piotr Raczynski
Make devlink allocation function generic to use it for PF and for SF.
Add function for SF devlink port creation. It will be used in next
patch.
Signed-off-by: Piotr Raczynski
Signed-off-by: Michal Swiatkowski
---
.../net/ethernet/intel/ice/devlink/devlink.c | 39 ++
From: Piotr Raczynski
Implement subfunction driver. It is probe when subfunction port is
activated.
VSI is already created. During the probe VSI is being configured.
MAC unicast and broadcast filter is added to allow traffic to pass.
Signed-off-by: Piotr Raczynski
Signed-off-by: Michal Swiatko
From: Piotr Raczynski
Configure netdevice for subfunction usecase. Mostly it is reusing ops
from the PF netdevice.
SF netdev is linked to devlink port registered after SF activation.
Reviewed-by: Pawel Chmielewski
Signed-off-by: Piotr Raczynski
Signed-off-by: Michal Swiatkowski
---
drivers/
From: Piotr Raczynski
Use previously implemented SF aux driver. It is probe during SF
activation and remove after deactivation.
Reviewed-by: Pawel Chmielewski
Signed-off-by: Piotr Raczynski
Signed-off-by: Michal Swiatkowski
---
.../ethernet/intel/ice/devlink/devlink_port.c | 7 ++
.../ethe
Hello:
This patch was applied to netdev/net-next.git (main)
by David S. Miller :
On Fri, 5 Apr 2024 13:18:30 +0200 you wrote:
> Hi networking maintainers,
>
> This is a follow up in my ongoing effort of making inb()/outb() and
> similar I/O port accessors compile-time optional. Previously I sen
E825C products have a different PHY model than E822, E823 and E810 products.
This PHY is ETH56G and its support is necessary to have functional PTP stack
for E825C products.
Grzegorz Nitka (2):
ice: Add NAC Topology device capability parser
ice: Adjust PTP init for 2x50G E825C devices
Jacob K
Create new ice_ptp_hw struct and use it for all HW and PTP-related
fields from struct ice_hw.
Replace definitions with struct fields, which values are set accordingly
to a specific device.
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
V4 -> V
From: Jacob Keller
Multiple places in the driver code need to convert enum ice_ptp_tmr_cmd
values into register bits for both the main timer and the PHY port
timers. The main MAC register has one bit scheme for timer commands,
while the PHY commands use a different scheme.
The E810 and E830 devi
From: Sergey Temerkhanov
Introduce functions enabling/disabling Tx TS interrupts
for the E822 and ETH56G PHYs
Signed-off-by: Sergey Temerkhanov
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
V5 -> V6: Adjusted return in ice_phy_cfg_intr_e82
Add a possibility to mark all transmitted/received timestamps as invalid
by clearing PHY OFFSET_READY registers.
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
drivers/net/ethernet/intel/ice/ice_ptp.c| 11 ---
drivers/net/ethernet/int
From: Sergey Temerkhanov
Move CGU block to the beginning of ice_ptp_hw.c
Signed-off-by: Sergey Temerkhanov
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
V6 -> V7: - removed leftover code in ice_read_cgu_reg_e82x()
- changed .data
From: Jacob Keller
Add a new helper for getting base clock increment value for specific HW.
Signed-off-by: Jacob Keller
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
V4 -> V5: Removed unused UNKNOWN_INCVAL_E82X
drivers/net/ethernet/intel
Simplify the code by using anonymous struct in CGU registers instead of
naming each structure 'field'.
Suggested-by: Przemek Kitszel
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
drivers/net/ethernet/intel/ice/ice_cgu_regs.h | 12 ++---
dri
From: Sergey Temerkhanov
E825C products feature a new PHY model - ETH56G.
Introduces all necessary PHY definitions, functions etc. for ETH56G PHY,
analogous to E82X and E810 ones with addition of a few HW-specific
functionalities for ETH56G like one-step timestamping.
It ensures correct PTP ini
From: Michal Michalik
The CGU layout of E825-C is a little different than E822/E823. Add
support the new hardware adding relevant functions.
Signed-off-by: Michal Michalik
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
---
V4 -> V5: added UL to
From: Grzegorz Nitka
Add new device capability ICE_AQC_CAPS_NAC_TOPOLOGY which allows to
determine the mode of operation (1 or 2 NAC).
Define a new structure to store data from new capability and
corresponding parser code.
Co-developed-by: Prathisna Padmasanan
Signed-off-by: Prathisna Padmasana
There are E825C products featuring 2 NACs. Those have only one source
clock on the primary NAC.
For those devices, there
should be only one clock controller on the primary NAC. All PFs from
both NACs should connect as auxiliary devices to the auxiliary driver on
the primary NAC.
Reviewed-by: Igor
From: Grzegorz Nitka
>From FW/HW perspective, 2 port topology in E825C devices requires
merging of 2 port mapping internally and breakout mapping externally.
As a consequence, it requires different port numbering from PTP code
perspective.
For that topology, pf_id can not be used to index PTP por
On 3/25/2024 04:09, Song Yoong Siang wrote:
This patch adds support to per-packet Tx hardware timestamp request to
AF_XDP zero-copy packet via XDP Tx metadata framework. Please note that
user needs to enable Tx HW timestamp capability via igc_ioctl() with
SIOCSHWTSTAMP cmd before sending xsk Tx h
On 3/26/2024 00:29, Bjorn Helgaas wrote:
From: Bjorn Helgaas
8c5ad0dae93c ("igc: Add ethtool support") added ethtool_ops.begin() and
.complete(), which used pm_runtime_get_sync() to resume suspended devices
before any ethtool_ops callback and allow suspend after it completed.
Subsequently, f32
On Thu, Apr 04, 2024 at 01:29:17PM +0530, Karthik Sundaravel wrote:
> Changing the MAC address of the VFs is currently unsupported via devlink.
> Add the function handlers to set and get the HW address for the VFs.
>
> Signed-off-by: Karthik Sundaravel
Hi Karthik,
I think this series should be
On Thu, Apr 04, 2024 at 04:04:51PM +0200, Marcin Szycik wrote:
> In cases when VF sends malformed packets that are classified as malicious,
> it can cause Tx queue to freeze as a result of Malicious Driver Detection
> event. Such malformed packets can appear as a result of a faulty userspace
> app
9f74a3dfcf83 ("ice: Fix VF Reset paths when interface in a failed over
aggregate"), the ice driver has acquired the LAG mutex in ice_reset_vf().
The commit placed this lock acquisition just prior to the acquisition of
the VF configuration lock.
If ice_reset_vf() acquires the configuration lock via
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