On 2025/5/13 14:13, Jason Xing wrote:
> On Tue, May 13, 2025 at 12:08 PM Haifeng Xu wrote:
>>
>> Hi all,
>>
>> If the packets arrive at the rx and then raise soft irq to handle
>> it, but in i40e_clean_rx_irq, status_error_len is 0 and return.
>
Hi all,
If the packets arrive at the rx and then raise soft irq to handle it,
but in i40e_clean_rx_irq, status_error_len is 0 and return.
The data isn't fetchted from the rx buffer, so the how the packets
arrive at the rx will be processed?
FYI, the every rx/tx q
On 2025/1/9 05:06, Tony Nguyen wrote:
>
>
> On 1/7/2025 7:36 PM, Haifeng Xu wrote:
>>
>>
>> On 2025/1/8 01:16, Tony Nguyen wrote:
>
> ...
>
>>>
>>> What's your ntuple filter setting? If it's off, I suspect it may be the
>
On 2025/1/8 01:16, Tony Nguyen wrote:
>
>
> On 1/2/2025 7:05 PM, Haifeng Xu wrote:
>>
>>
>> On 2025/1/3 00:01, Edward Cree wrote:
>>> On 02/01/2025 11:23, Haifeng Xu wrote:
>>>> We want to make full use of cpu resources to receive packets. So
&g
On 2025/1/3 00:01, Edward Cree wrote:
> On 02/01/2025 11:23, Haifeng Xu wrote:
>> We want to make full use of cpu resources to receive packets. So
>> we enable 63 rx queues. But we found the rate of interrupt growth
>> on cpu 0~15 is faster than other cpus(almost twice).
&
On 2025/1/3 00:39, Jakub Kicinski wrote:
> On Thu, 2 Jan 2025 16:01:18 + Edward Cree wrote:
>> On 02/01/2025 11:23, Haifeng Xu wrote:
>>> We want to make full use of cpu resources to receive packets. So
>>> we enable 63 rx queues. But we found the rate of interrup
On 2025/1/2 19:46, Eric Dumazet wrote:
> On Thu, Jan 2, 2025 at 12:23 PM Haifeng Xu wrote:
>>
>>
>>
>> On 2025/1/2 18:34, Eric Dumazet wrote:
>>> On Thu, Jan 2, 2025 at 9:43 AM Haifeng Xu wrote:
>>>>
>>>>
>>>>
>>
On 2025/1/2 18:34, Eric Dumazet wrote:
> On Thu, Jan 2, 2025 at 9:43 AM Haifeng Xu wrote:
>>
>>
>>
>> On 2025/1/2 16:13, Eric Dumazet wrote:
>>> On Thu, Jan 2, 2025 at 4:53 AM Haifeng Xu wrote:
>>>>
>>>> Hi masters,
>>>>
On 2025/1/2 16:13, Eric Dumazet wrote:
> On Thu, Jan 2, 2025 at 4:53 AM Haifeng Xu wrote:
>>
>> Hi masters,
>>
>> We use the Intel Corporation 82599ES NIC in our production
>> environment. And it has 63 rx queues, every rx queue interrupt
Hi masters,
We use the Intel Corporation 82599ES NIC in our production environment.
And it has 63 rx queues, every rx queue interrupt is processed by a single cpu.
The RSS configuration can be seen as follow:
RX flow hash indirection table for eno5 with 63 RX ring(s):
Hi masters,
We use the Intel Corporation 82599ES NIC in our production environment.
And it has 63 rx
queues, every rx queue interrupt is processed by a single cpu.
The RSS configuration can be seen as follow:
RX flow hash indirection table for eno5 with 63 RX ring(s):
0: 0
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