From: Ville Syrjälä
Pull the common parts of intel_dp_compute_link_config_wide()
and intel_dp_compute_link_config_fast() into a shared helper
to avoid duplicated code.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c | 74 ++---
1 file changed, 43 in
From: Ville Syrjälä
Some new eDP panels don't like to operate at the max parameters, and
instead we need to go for an optimal confiugration. That unfortunately
doesn't work with older eDP panels which are generally only guaranteed
to work at the max parameters.
To solve these two conflicting req
From: Ville Syrjälä
MMIO async flips have been suported since g4x. We can easily enable
them for all ilk+ platforms. So let's do that.
g4x is more problematic since it doesn't have a flip done
interrupt (which the current solution depends on), and the flip
pending blit that it does have only wor
From: Ville Syrjälä
Drop the pointless extra parens.
Cc: Karthik B S
Cc: Vandita Kulkarni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
ind
From: Ville Syrjälä
Only assign the plane->async_flip() vfunc when the plane supports
async flips. For now we keep this artificially limited to the primary
plane since thats the only thing the legacy page flip uapi can target
and there is no async flip support in the atomic uapi yet.
Cc: Karthik
From: Ville Syrjälä
Set up the async flip PLANE_CTL bit directly in the
.async_flip() hook. Neither .update_plane() nor .disable_plane()
ever need to set this so having it done by skl_plane_ctl_crtc()
is rather pointless.
Cc: Karthik B S
Cc: Vandita Kulkarni
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
On some platforms we need to trigger an extra async flip with
the async flip bit disabled, and then wait for the next vblank
until the async flip bit off state will actually latch.
Currently the w/a is just open coded for skl+ universal planes.
Instead of doing that lets reus
From: Ville Syrjälä
Implement async flip support for BDW. The implementation is
similar to the skl+ code. And just like skl/bxt/glk bdw also
needs the disable w/a, thus we need to plumb the desired state
of the async flip all the way down to i9xx_plane_ctl_crtc().
According to the spec we do nee
From: Ville Syrjälä
Add support for async flips on ivb/hsw. Again no need for any
workarounds and just have to deal with the interrupt bits being
shuffled around a bit.
Cc: Karthik B S
Cc: Vandita Kulkarni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c| 24 +++
From: Ville Syrjälä
Add support for async flips on vlv/chv. Unlike all the other
platforms vlv/chv do not use the async flip bit in DSPCNTR and
instead we select between async vs. sync flips based on the
surface address register. The normal DSPSURF generates sync
flips DSPADDR_VLV generates async
From: Ville Syrjälä
Prepare for more platforms with async flip support by turning
the flip_done interrupt enable/disable into plane vfuncs.
Cc: Karthik B S
Cc: Vandita Kulkarni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 42 +--
.../drm/i9
From: Ville Syrjälä
Add support for async flips on ivb/hsw. Unlike bdw+ we don't need
any workarounds to disable async flips. Apart from that the only
real difference from the bdw implementation is the location of the
flip_done interrupt bits.
Cc: Karthik B S
Cc: Vandita Kulkarni
Signed-off-by
From: Ville Syrjälä
Second attempt at hooking up async flips for everyone,
this time taking care to keep the plane src coordinates
below the limits of the TILEOFF/OFFSET register.
Ville Syrjälä (11):
drm/i915: WARN if plane src coords are too big
drm/i915: Limit plane stride to below TILEOFF
From: Ville Syrjälä
Inform us if we're buggy and are about to exceed the size of the
bitfields in the plane TILEOFF/OFFSET registers.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c| 7 +++
drivers/gpu/drm/i915/display/intel_display.c | 4
2 files change
From: Ville Syrjälä
Limit pre-skl plane stride to below 4k or 8k pixels (depending on
the platform). We do this in order guarantee that TILEOFF/OFFSET.x
does not get too big.
Currently this is not a problem as we align SURF to 4k, and so
TILEOFF/OFFSET only have to deal with a single tile's wort
From: Ville Syrjälä
Drop the pointless extra parens.
Cc: Karthik B S
Cc: Vandita Kulkarni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
ind
From: Ville Syrjälä
Prepare for more platforms with async flip support by turning
the flip_done interrupt enable/disable into plane vfuncs.
Cc: Karthik B S
Cc: Vandita Kulkarni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 42 +--
.../drm/i9
From: Ville Syrjälä
Set up the async flip PLANE_CTL bit directly in the
.async_flip() hook. Neither .update_plane() nor .disable_plane()
ever need to set this so having it done by skl_plane_ctl_crtc()
is rather pointless.
Cc: Karthik B S
Cc: Vandita Kulkarni
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
On some platforms we need to trigger an extra async flip with
the async flip bit disabled, and then wait for the next vblank
until the async flip bit off state will actually latch.
Currently the w/a is just open coded for skl+ universal planes.
Instead of doing that lets reus
From: Ville Syrjälä
Only assign the plane->async_flip() vfunc when the plane supports
async flips. For now we keep this artificially limited to the primary
plane since thats the only thing the legacy page flip uapi can target
and there is no async flip support in the atomic uapi yet.
Cc: Karthik
From: Ville Syrjälä
Implement async flip support for BDW. The implementation is
similar to the skl+ code. And just like skl/bxt/glk bdw also
needs the disable w/a, thus we need to plumb the desired state
of the async flip all the way down to i9xx_plane_ctl_crtc().
According to the spec we do nee
From: Ville Syrjälä
Add support for async flips on ivb/hsw. Unlike bdw+ we don't need
any workarounds to disable async flips. Apart from that the only
real difference from the bdw implementation is the location of the
flip_done interrupt bits.
Cc: Karthik B S
Cc: Vandita Kulkarni
Signed-off-by
From: Ville Syrjälä
Add support for async flips on ivb/hsw. Again no need for any
workarounds and just have to deal with the interrupt bits being
shuffled around a bit.
Cc: Karthik B S
Cc: Vandita Kulkarni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c| 24 +++
From: Ville Syrjälä
Add support for async flips on vlv/chv. Unlike all the other
platforms vlv/chv do not use the async flip bit in DSPCNTR and
instead we select between async vs. sync flips based on the
surface address register. The normal DSPSURF generates sync
flips DSPADDR_VLV generates async
From: Ville Syrjälä
Let's not enable the 4:4:4->4:2:0 conversion bit in the DFP unless we're
actually outputting YCbCr 4:4:4. It would appear some protocol
converters blindy consult this bit even when the source is outputting
RGB, resulting in a visual mess.
Closes: https://gitlab.freedesktop.or
From: Ville Syrjälä
The DDI buf trans functions keep turning into bad
spaghetti every time a new platform gets added.
Split the platforms up properly and turn the whole
thing into a vfunc to make it easier to manage
multiple platforms.
v2: Rebase due to adl-p landing in the meantime
Ville Syrjä
From: Ville Syrjälä
Give the hsw/bdw/skl buf trans stuff a better namespace.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 39 +
drivers/gpu/drm/i915/display/intel_ddi.h | 4 +-
.../drm/i915/display/intel_ddi_buf_trans.
From: Ville Syrjälä
All the other platforms handle the output_type stuff in their
*_get_buf_trans() functions. Do the same for hsw/bdw/skl.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 27
.../drm/i915/display/intel_ddi
From: Ville Syrjälä
In order to abstact the buf trans stuff let's wrap the platform
specific structs into a union.
v2: Handle adl-p
Reviewed-by: Jani Nikula #v1
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 76 +-
.../drm/i915/display/intel_ddi_buf_trans.
From: Ville Syrjälä
Put a wrapper struct around the buf trans tables so that
we can declare the number of entries and default HDMI entry
alongside the table.
@wrap@
identifier old =~ "^.*translations.*";
fresh identifier new = "_" ## old;
type T;
@@
<...
static const T
- old
+ new
[] = {
From: Ville Syrjälä
Rename the dkl phy buf trans tables to follow the same
naming pattern used by everyone else.
v2: Handle adl-p
Reviewed-by: Jani Nikula #v1
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_ddi_buf_trans.c| 32 +--
1 file changed, 16 insertion
From: Ville Syrjälä
Add a small helper to get the buf trans entris+num_entries
from the struct. Should avoid copy-paste errors in the
platform specific get_buf_trans() functions.
@@
identifier T, N;
@@
- *N = T.num_entries;
- return T.entries;
+ return intel_get_buf_trans(&T, N);
@@
@@
is_hobl_
From: Ville Syrjälä
Raise the abstraction level of the get_buf_trans() functions
a bit more by returning the whole wrapper intel_ddi_buf_trans
struct.
v2: Handle adl-p
Reviewed-by: Jani Nikula #v1
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 76 +++
From: Ville Syrjälä
Store the default HDMI buf trans entry in struct intel_ddi_buf_trans
so that it's next to the actual table. This let's us start ridding
ourselves of some platofrm specifics in intel_ddi_hdmi_num_entries().
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
.../drm/i
From: Ville Syrjälä
Convert the get_buf_trans() functions into an encoder vfunc.
Allows us to get rid of bunch of platform if-ladders.
v2: Handle adl-p
Reviewed-by: Jani Nikula #v1
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_crt.c | 3 +
drivers/gpu/drm/i915/dis
From: Ville Syrjälä
Split the hsw/bdw/skl/kbl get_buf_trans() functions into
clean platform specific variants.
Reviewed-by: Jani Nikula
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_ddi_buf_trans.c| 308 +++---
1 file changed, 118 insertions(+), 190 deletions(-)
From: Ville Syrjälä
Give RKL its own get_buf_trans() func.
v2: Drop the FIXME since the spec was clarified to
indicate that TGL values are used for the HDMI/eDP cases.
Reviewed-by: Jani Nikula #v1
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_ddi_buf_trans.c| 62 +++
From: Ville Syrjälä
For some reason the dg1 buf trans tables have been stuffed into
icl_get_combo_buf_trans_edp() which doesn't even get called
on dg1. Split them out into a proper dg1 specific function,
and also make sure we use the proper buf trans tables for
DP as well as eDP.
v2: Add the hob
From: Ville Syrjälä
The icl combo phy DP HBR2 is identical to the eDP HBR3 table.
Get rid of one redundant copy.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_ddi_buf_trans.c| 39 +--
1 file changed, 10 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/
From: Ville Syrjälä
EHL is supposed to use special buf trans values for eDP HBR2+.
Add such a table.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_ddi_buf_trans.c| 28 +--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/disp
From: Ville Syrjälä
The jsl/ehl buf trans functions are needlessly conplicated.
Simplify them.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_ddi_buf_trans.c| 87 +--
1 file changed, 20 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i
From: Ville Syrjälä
All the foo_get_buf_trans_hdmi() functions just reuturn a single table.
Remove the pointless wrappers.
v2: Handle adl-p
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_ddi_buf_trans.c| 51 +++
1 file changed, 7 insertions(+), 44 deletions(-)
From: Ville Syrjälä
adls is supposed to use special buf trans tables. Add what's
missing.
v2: Drop the RBR/HBR table since it's the same as for tgl
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_ddi_buf_trans.c| 101 ++
1 file changed, 101 insertions(+)
diff
From: Ville Syrjälä
Sort out the mess with the local variables in
intel_get_load_detect_pipe(). Get rid of all aliasing pointers
and use standard naming/types.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 41 +---
1 file changed, 19 insertions
From: Ville Syrjälä
Use drm_crtc_mask() instead of hand rolling it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/displa
From: Ville Syrjälä
Sort out the mess with the local variables in
intel_find_initial_plane_obj(). Get rid of all aliasing pointers
and use standard naming/types.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 113 ++-
1 file changed, 62 insertio
From: Ville Syrjälä
Just pass the full atomic state+crtc to the pre-skl watermark
functions, and clean up the types/variable names around the area.
Note that having both .compute_pipe_wm() and .compute_intermediate_wm()
is entirely redundant now. We could unify them to a single vfunc.
But let's
From: Ville Syrjälä
Finish the s/intel_crtc/crtc/ conversion we started long ago,
and do a bit of other related house cleaning.
Ville Syrjälä (6):
drm/i915: Stop hand rolling drm_crtc_mask()
drm/i915: Clean up intel_get_load_detect_pipe() a bit
drm/i915: Clean up intel_find_initial_plane_o
From: Ville Syrjälä
Clear out the straggler 'intel_crtc' variables.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c| 4 +-
drivers/gpu/drm/i915/display/intel_crtc.c | 8 ++--
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +--
drivers/gpu/drm/i915/disp
From: Ville Syrjälä
Sort out the mess with the local variables in
intel_fbdev_init_bios(). Get rid of all aliasing pointers,
use standard naming/types, and introduc a few more locals
in the loops to avoid the hard to read long struct walks.
While at we also polish the debugs a bit to use the
can
From: Ville Syrjälä
I need to tweak the cfb stride/size handling a bit the current
cfb allocation code is too messy to make that easy. Start by
cleaning stuff up.
Ville Syrjälä (9):
drm/i915/fbc: s/threshold/limit/
drm/i915/fbc: Extract intel_fbc_program_cfb()
drm/i915/fbc: Embed the comp
From: Ville Syrjälä
Let's call the compression limit the limit.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 50
drivers/gpu/drm/i915/i915_drv.h | 3 +-
2 files changed, 27 insertions(+), 26 deletions(-)
diff --git a/drivers/gp
From: Ville Syrjälä
Extract the CFB (+LLB) programming into a separate function.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 46 ++--
1 file changed, 28 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/
From: Ville Syrjälä
Not much point in dynamically allocating the line length
buffer mm node that I can see. Just embed it directly like
we do the for the cfb node. One less failure point to worry
about.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 29
From: Ville Syrjälä
No point in passing the mm node explicitly to find_compression_limit()
since it's always the same node for the cfb.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/dr
From: Ville Syrjälä
The limit++ for the 16bpp case is nonsense since the
compression limit is always supposed to be power of two.
Replace it with <<=1.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --
From: Ville Syrjälä
Exctract the limit->register value conversion into a common
helper.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 58 ++--
1 file changed, 25 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb
From: Ville Syrjälä
Declutter find_compression_limit() a bit by extracting
intel_fbc_stolen_end().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/int
From: Ville Syrjälä
Write the cfb allocation loop as an actual loop instead of some
hard to read goto thing.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 51
1 file changed, 26 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/
From: Ville Syrjälä
Since the llb allocation has a fixed size, let's grab it before
the potentially variable sized cfb. That should avoid some allocation
failure cases once we allow different compression ratios for FBC1.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c
From: Ville Syrjälä
All the generic link training code should be in check now.
Let's move on to actually programming the each TX lane with
its own individual settings.
Ville Syrjälä (16):
drm/i915: Remove pointless extra namespace from dkl/snps buf trans
structs
drm/i915: Shrink {icl_mg,
From: Ville Syrjälä
The struct itself already has sufficient namespace. No need to
duplicate it in the members.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++---
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h | 12 ++--
drivers/gpu/drm
From: Ville Syrjälä
All the values we have in {icl_mg,tgl_dkl}_phy_ddi_buf_trans
fit into u8. Shrink the types accordingly.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drive
From: Ville Syrjälä
Use <4 instead of <=3 as the terminating condition for the
loops over the 4 lanes.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/d
From: Ville Syrjälä
DKL_TX_LOADGEN_SHARING_PMD_DISABLE doesn't even seem to exist,
also the spec says to skip all loadgen stuff.
The code was dead anyway since it wasn't actually writing the value
anywhere.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 8
From: Ville Syrjälä
Pull the convoluted loadgen calculation into a small helper.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 23 ++-
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/dr
From: Ville Syrjälä
Program each TX lane individually so that we can start to use per-lane
drive settings.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 28 ++--
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i9
From: Ville Syrjälä
Prepare for per-lane drive settings by querying the desired vswing
level per-lane.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b
From: Ville Syrjälä
Prepare for per-lane drive settings by querying the desired vswing
level per-lane.
Note that the code only does two loops, with each one writing the
levels for two TX lanes.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 13 -
1 fil
From: Ville Syrjälä
Prepare for per-lane drive settings by querying the desired vswing
level per-lane.
Note that the code only does two loops, with each one writing the
levels for two TX lanes. The register offsets also look a bit funny
because each time through the loop we write to the exact sa
From: Ville Syrjälä
Add the FOO_LN() register macros for all the icl combo phy registers.
Also get rid of the semi-pointless FOO_LN0() variants and just use
the parametrized version.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/icl_dsi.c | 14 +++---
drivers/gp
From: Ville Syrjälä
Prepare for per-lane drive settings by querying the desired vswing
level per-lane.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.
From: Ville Syrjälä
Now that the link buf_trans, link training, and the
combo/mg/dkl/snps phy programming are all fixed up we can
allow per-lane DP drive settings on icl+. Make it so.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 5 -
1 file chang
From: Ville Syrjälä
Streamline the code by using intel_de_rmw().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 36 +++-
1 file changed, 16 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/
From: Ville Syrjälä
Streamline the code by using intel_de_rmw().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 111 ---
1 file changed, 39 insertions(+), 72 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/
From: Ville Syrjälä
Streamline the code by using intel_de_rmw().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 44 ++--
1 file changed, 18 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/
From: Ville Syrjälä
Our lane power down defines already include the necessary shift,
don't shit them a second time.
Fortunately we masked off the correct bits, so we accidentally
left all lanes powered up all the time.
Bits 8-11 where we end up writing our misdirected lane mask are
documented a
From: Ville Syrjälä
I was just perusing skl_program_plane() when I stumbled on
this slightly iffy pxp stuff. Let's try to clean it up.
Cc: Anshuman Gupta
Cc: Daniele Ceraolo Spurio
Cc: Juston Li
Cc: Rodrigo Vivi
Cc: Uma Shankar
Ville Syrjälä (4):
drm/i915: Move the pxp plane state comput
From: Ville Syrjälä
No real reason to have this pxp state computation in
intel_atomic_check_planes(). Just stuff it into skl_plane_check().
There was also some funny state copying being done from the
old plane state to the new plane state when the plane is anyway
disabled.
The one thing we pres
From: Ville Syrjälä
There's lots of expensive stuff inserted between the PLANE_CTL
and PLANE_SURF writes even though the comment before the PLANE_CTL
write says not to put stuff there. Move it all to a more apporiate
place.
There's also a weird PLANE_COLOR_CTL RMW in there. I guess because
forc
From: Ville Syrjälä
We are inside the vblank evade critical section here, racing
against the raster beam. There is no time to print debug
messages.
Cc: Anshuman Gupta
Cc: Daniele Ceraolo Spurio
Cc: Juston Li
Cc: Rodrigo Vivi
Cc: Uma Shankar
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm
From: Ville Syrjälä
intel_load_plane_csc_black() is specific to glk+ so deserves
a name reflecting that fact. Also rename the variables to
standard form so I won't get confused reading the code.
Cc: Anshuman Gupta
Cc: Daniele Ceraolo Spurio
Cc: Juston Li
Cc: Rodrigo Vivi
Cc: Uma Shankar
Sig
From: Ville Syrjälä
Fix a pile of regression on older machines which just oops the driver
on load.
Cc: Dave Airlie
Cc: Jani Nikula
Cc: Maarten Lankhorst
Cc: Thomas Hellström
Cc: Chris Wilson
Cc: Mika Kuoppala
Ville Syrjälä (4):
drm/i915: Replace the unconditional clflush with
drm_cl
From: Ville Syrjälä
Not all machines have clflush, so don't go assuming they do.
Not really sure why the clflush is even here since hwsp
is supposed to get snooped I thought.
Although in my case we're talking about a i830 machine where
render/blitter snooping is definitely busted. But it might
w
From: Ville Syrjälä
This one is apparently a "clflush for good measure", so bit more
justification (if you can call it that) than some of the others.
Convert to drm_clflush_virt_range() again so that machines without
clflush will survive the ordeal.
Cc: sta...@vger.kernel.org
Cc: Maarten Lankhor
From: Ville Syrjälä
We don't have hpd support on i8xx/i915 which means hotplug_funcs==NULL.
Let's not oops when loading the driver on one those machines.
Cc: Dave Airlie
Cc: Jani Nikula
Fixes: cd030c7c11a4 ("drm/i915: constify hotplug function vtable.")
Signed-off-by: Ville Syrjälä
---
drive
From: Ville Syrjälä
Replace the unconditional clflush() with drm_clflush_virt_range()
which does the wbinvd() fallback when clflush is not available.
This time no justification is given for the clflush in the
offending commit.
Cc: sta...@vger.kernel.org
Cc: Maarten Lankhorst
Cc: Thomas Hellstr
From: Ville Syrjälä
Turns out the DSB has trouble correctly loading the gamma LUT.
>From a cursory look maybe like some entries do not load
properly, or they get loaded with some gibberish. Unfortunately
our current kms_color/etc. tests do not seem to catch this.
I had a brief look at the genera
From: Ville Syrjälä
All interpolated gamma modes including the icl+ multi segment
mode require non-decreasing entries for the interpolation to
work correctly. For some reason we're forgetting to declare
that for icl+. Let us do so.
References: https://gitlab.freedesktop.org/drm/intel/-/issues/39
From: Ville Syrjälä
Let's move the PCH modeset stuff into its own file and provide
a clean api for the higher level modeset code to use.
Not quite sure about the file name though. Ideas welcome.
Cc: Dave Airlie
Cc: Jani Nikula
Ville Syrjälä (9):
drm/i915: Move PCH refclok stuff into its ow
From: Ville Syrjälä
Move the PCH refclk stuff (including all the LPT/WPT
iCLKIP/CLKOUT_DP things) to its own file.
We also suck in the mPHY programming from intel_fdi.c
since we're the only caller.
Cc: Dave Airlie
Cc: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/Makefil
From: Ville Syrjälä
Start moving the code for PCH modeset sequence/etc. to
its own file.
Still not sure about the file name though...
Cc: Dave Airlie
Cc: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_cr
From: Ville Syrjälä
Use the clean "atomic_state+crtc" approach of passing
arguments to the top level PCH modeset code.
And while at it we can also just pass the whole crtc to
ilk_disable_pch_transcoder().
Cc: Dave Airlie
Cc: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/
From: Ville Syrjälä
Pull the ilk+ PCH state readout into its own function and relocate
to the appropriate file.
The clock readout parts are perhaps a bit iffy since we depend
on the gmch DPLL readout code. But we can think about the clock
readout big picture later.
Cc: Dave Airlie
Cc: Jani Nik
From: Ville Syrjälä
Nuke the hsw_get_ddi_port_state() eyesore by putting the
readout code into intel_pch_display.c, and calling it directly
from hsw_crt_get_config().
Cc: Dave Airlie
Cc: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_crt.c | 2 +
driver
From: Ville Syrjälä
Hoover the remaining open coded PCH modeset sequence bits
out from ilk_crtc_disable(). Somewhat annoyingly the
enable vs. disable is a bit asymmetric so we need two
functions for the disable case.
Cc: Dave Airlie
Cc: Jani Nikula
Signed-off-by: Ville Syrjälä
---
drivers/gp
From: Ville Syrjälä
Reanme intel_ddi_fdi_post_disable() to hsw_fdi_disable() and
relocate it next to all the other code dealing with FDI_RX.
intel_ddi.c has now been cleansed of FDI_RX.
In order to avoid exposing intel_disable_ddi_buf() outside
intel_ddi.c we can just open code the DDI_BUF_CTL w
From: Ville Syrjälä
Move the lpt_get_iclkip() call from hsw_crt_get_config()
since that's where we have the lpt_program_iclkip() call
as well.
Tehcnically this isn't perhaps quite right since iCLKIP
is providing the CRT dotclock. So one can argue all of
it should be directly in intel_crt.c. But
From: Ville Syrjälä
Let's add lpt_pch_disable() as the counterpart to
lpt_pch_enable().
Note that unlike the ilk+ code the fdi_link_train()
and fdi_disable() calls are still left directly in
intel_crt.c. If we wanted to move those we'd need to
add lpt_pch_pre_enable(). But the two fdi direct fdi
From: Ville Syrjälä
Currently we're failing to respect the sink's max TMDS clock
in the DP HDMI DFP code, and exceeding them means the sink
won't show a picture [1]. So let's improve the situation by
checking those limits, and generally fixing up a bunch things
in the deep color/4:2:0 related stu
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