port until we have the required
> infrastructure - but reserve the bit in flags for future use.
> v21: use_mm() is not required for get_user_pages(). It is only meant to
> be used to fix up the kernel thread's current->mm for use with
> copy_user().
>
> Signed-off-b
Hi Chris, just want to bring this one back to your attention while
I'm going through the rest of the series.
Thanks,
Brad
On Fri, Mar 28, 2014 at 03:58:25PM -0700, Volkin, Bradley D wrote:
> On Mon, Mar 17, 2014 at 05:21:55AM -0700, Chris Wilson wrote:
> > A common issue we have is
On Wed, Mar 19, 2014 at 04:13:06AM -0700, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> This adds a small benchmark for the new userptr functionality.
>
> Apart from basic surface creation and destruction, also tested is the
> impact of having userptr surfaces in the process address space. Re
On Wed, Mar 19, 2014 at 04:13:05AM -0700, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> No need for the old test case once the new one was added.
>
> Signed-off-by: Tvrtko Ursulin
Reviewed-by: Brad Volkin
> ---
> tests/.gitignore | 1 -
> tests/Makefile.sources | 1 -
> tests/g
On Wed, Mar 19, 2014 at 04:13:04AM -0700, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> A set of userptr test cases to support the new feature.
>
> For the eviction and swapping stress testing I have extracted
> some common behaviour from gem_evict_everything and made both
> test cases use it
On Wed, Apr 09, 2014 at 09:47:57AM -0700, Daniel Vetter wrote:
> On Wed, Apr 09, 2014 at 08:12:28AM -0700, Volkin, Bradley D wrote:
> > On Tue, Apr 08, 2014 at 11:20:30PM -0700, Chris Wilson wrote:
> > > On Tue, Apr 08, 2014 at 02:22:16PM -0700, bradley.d.vol...@inte
[snip]
On Wed, Apr 23, 2014 at 06:28:54AM -0700, Tvrtko Ursulin wrote:
> On 04/18/2014 12:18 AM, Volkin, Bradley D wrote:
> > On Wed, Mar 19, 2014 at 04:13:06AM -0700, Tvrtko Ursulin wrote:
> >> +static void **handle_ptr_map;
> >> +static unsigned int num_handle_ptr_m
On Wed, Apr 23, 2014 at 06:33:40AM -0700, Tvrtko Ursulin wrote:
>
> On 04/18/2014 06:10 PM, Volkin, Bradley D wrote:
> > On Wed, Mar 19, 2014 at 04:13:04AM -0700, Tvrtko Ursulin wrote:
> >> From: Tvrtko Ursulin
> >>
> >> A set of userptr test cases to sup
Reviewed-by: Brad Volkin
On Wed, Apr 23, 2014 at 08:07:55AM -0700, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Makes for a little bit less code duplication, especially since
> it will be used from more callers in the future.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> lib/drmtest.h
Reviewed-by: Brad Volkin
On Wed, Apr 23, 2014 at 09:03:23AM -0700, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> They build fine so give them some exposure.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> Android.mk | 2 +-
> benchmarks/Android.mk | 36 ++
Reviewed-by: Brad Volkin
On Wed, Apr 23, 2014 at 05:38:34PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> No need for the old test case once the new one was added.
>
> v2:
>* Just rebase for lib/ reorganization.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> tests/.gitignore
On Wed, Apr 23, 2014 at 05:38:35PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> This adds a small benchmark for the new userptr functionality.
>
> Apart from basic surface creation and destruction, also tested is the
> impact of having userptr surfaces in the process address space. Re
Reviewed-by: Brad Volkin
On Wed, Apr 23, 2014 at 05:38:33PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> A set of userptr test cases to support the new feature.
>
> For the eviction and swapping stress testing I have extracted
> some common behaviour from gem_evict_everything and ma
Reviewed-by: Brad Volkin
On Thu, Apr 24, 2014 at 10:07:32AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> This adds a small benchmark for the new userptr functionality.
>
> Apart from basic surface creation and destruction, also tested is the
> impact of having userptr surfaces in th
On Thu, Apr 24, 2014 at 02:22:39AM -0700, Chris Wilson wrote:
> On Fri, Mar 28, 2014 at 03:58:25PM -0700, Volkin, Bradley D wrote:
> > On Mon, Mar 17, 2014 at 05:21:55AM -0700, Chris Wilson wrote:
> > > @@ -1949,58 +1956,58 @@ static unsigned long
> > > __i915_gem_shr
On Mon, Apr 28, 2014 at 08:22:08AM -0700, Volkin, Bradley D wrote:
> From: Brad Volkin
>
> For clients that submit large batch buffers the command parser has
> a substantial impact on performance. On my HSW ULT system performance
> drops as much as ~20% on some tests. Most of th
On Mon, Apr 28, 2014 at 08:42:56AM -0700, Daniel Vetter wrote:
> On Mon, Apr 28, 2014 at 08:22:08AM -0700, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> >
> > For clients that submit large batch buffers the command parser has
> > a substantial impact on performance. On my HSW ULT syst
On Mon, Apr 28, 2014 at 08:53:30AM -0700, Daniel Vetter wrote:
> On Mon, Apr 28, 2014 at 08:22:08AM -0700, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> >
> > For clients that submit large batch buffers the command parser has
> > a substantial impact on performance. On my HSW ULT syst
On Fri, Apr 18, 2014 at 02:04:27PM -0700, Rodrigo Vivi wrote:
> From: Ben Widawsky
>
> I don't have any insight on what parts can do what. The docs do seem to
> suggest WT caching works in at least the same manner as it doesn't on
> Haswell.
As Ben previously mentioned, s/doesn't/does. Other tha
Reviewed-by: Brad Volkin
On Fri, Apr 18, 2014 at 02:04:28PM -0700, Rodrigo Vivi wrote:
> From: Ben Widawsky
>
> The same register exists for querying and programming eDRAM AKA eLLC. So
> we can simply use it. For now, use all the same defaults as we had
> for Haswell, since like Haswell, I have
Reviewed-by: Brad Volkin
On Fri, Apr 18, 2014 at 02:04:29PM -0700, Rodrigo Vivi wrote:
> From: Ben Widawsky
>
> It seems we need this at least for the current platforms we have, but
> probably not later. In any event, it should cause too much harm as we do
> the same thing on several other plat
Could someone help to review this patch please? It provides a nice
improvement to the command parser's performance, so I'd like to get
this one in.
Thanks,
Brad
On Mon, Apr 28, 2014 at 08:22:08AM -0700, Volkin, Bradley D wrote:
> From: Brad Volkin
>
> For clients that
On Mon, May 05, 2014 at 01:07:32AM -0700, Chris Wilson wrote:
> A few improvements to the fallback method for waiting upon ring space:
>
> 1. Fix the start/end wait tracepoints to always be paired.
> 2. Increase responsiveness of checking
> 3. Mark the process as waiting upon io
> 4. Check for sig
On Mon, May 05, 2014 at 01:07:33AM -0700, Chris Wilson wrote:
> During the review of
>
> commit 1f70999f9052f5a1b0ce1a55aff3808f2ec9fe42
> Author: Chris Wilson
> Date: Mon Jan 27 22:43:07 2014 +
>
> drm/i915: Prevent recursion by retiring requests when the ring is full
>
> Ville raise
On Thu, May 08, 2014 at 02:56:05AM -0700, Tvrtko Ursulin wrote:
>
> Hi Brad,
>
> On 04/28/2014 04:22 PM, bradley.d.vol...@intel.com wrote:
> [snip]
> > - BUG_ON(!validate_cmds_sorted(ring));
> > + BUG_ON(!validate_cmds_sorted(ring, cmd_tables, cmd_table_count));
> > BUG_ON(!validate_regs_
On Thu, May 08, 2014 at 06:42:16AM -0700, Tvrtko Ursulin wrote:
>
> On 04/28/2014 04:22 PM, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> >
> > For clients that submit large batch buffers the command parser has
> > a substantial impact on performance. On my HSW ULT system performance
On Thu, May 08, 2014 at 06:15:44AM -0700, Lespiau, Damien wrote:
> On Thu, May 08, 2014 at 02:05:07PM +0100, Damien Lespiau wrote:
> > On Mon, Apr 28, 2014 at 08:22:08AM -0700, bradley.d.vol...@intel.com wrote:
> > > From: Brad Volkin
> > > +/*
> > > + * Different command ranges have different num
On Thu, May 08, 2014 at 08:45:07AM -0700, Ville Syrjälä wrote:
> On Thu, May 08, 2014 at 08:27:16AM -0700, Volkin, Bradley D wrote:
> > On Thu, May 08, 2014 at 02:56:05AM -0700, Tvrtko Ursulin wrote:
> > >
> > > Hi Brad,
> > >
> > > On 04/28/20
On Thu, May 08, 2014 at 08:50:40AM -0700, Tvrtko Ursulin wrote:
>
> On 05/08/2014 04:27 PM, Volkin, Bradley D wrote:
> > On Thu, May 08, 2014 at 02:56:05AM -0700, Tvrtko Ursulin wrote:
> >>
> >> Hi Brad,
> >>
> >> On 04/28/2014 04:22
On Mon, Apr 28, 2014 at 08:01:29AM -0700, arun.siluv...@linux.intel.com wrote:
> From: "Siluvery, Arun"
>
> This patch adds support to have gem objects of variable size.
> The size of the gem object obj->size is always constant and this fact
> is tightly coupled in the driver; this implementation
On Sat, May 10, 2014 at 06:42:32AM -0700, Siluvery, Arun wrote:
> On 09/05/2014 22:18, Volkin, Bradley D wrote:
> > On Mon, Apr 28, 2014 at 08:01:29AM -0700, arun.siluv...@linux.intel.com
> > wrote:
> >> + if (ret)
> >> + return ret;
> >>
On Mon, May 12, 2014 at 09:24:06AM -0700, Daniel Vetter wrote:
> On Thu, May 08, 2014 at 09:02:18AM -0700, Volkin, Bradley D wrote:
> > On Thu, May 08, 2014 at 08:45:07AM -0700, Ville Syrjälä wrote:
> > > On Thu, May 08, 2014 at 08:27:16AM -0700, Volkin, Bradley D wrote:
>
_user().
> v22: Use sg_alloc_table_from_pages for that chunky feeling
> v23: Export a function for sanity checking dma-buf rather than encode
> userptr details elsewhere, and clean up comments based on
> suggestions by Bradley.
>
> Signed-off-by: Chris Wilson
> Cc: Tvrtk
On Fri, May 16, 2014 at 12:53:30PM -0700, Jesse Barnes wrote:
> On Fri, 16 May 2014 12:34:08 -0700
> Jesse Barnes wrote:
>
> > On Fri, 16 May 2014 20:20:50 +0100
> > Chris Wilson wrote:
> > > Yes, X only sets the secure bit when it pokes the display registers, and
> > > those registers should be
On Mon, May 19, 2014 at 09:12:26AM -0700, Mateo Lozano, Oscar wrote:
> BTW: do you want me to kill private_default_ctx as well? It doesn´t look very
> useful...
Isn't private_default_ctx the one that's actually used when userspace
specifies DEFAULT_CONTEXT_ID?
Brad
> ___
On Fri, May 09, 2014 at 05:08:32AM -0700, oscar.ma...@intel.com wrote:
> From: Ben Widawsky
>
> for_each_ring() iterates over all rings supported by the hardware, not
> just those which have been initialized as in for_each_active_ring()
I think we should give this a new name; something like for_
On Mon, May 19, 2014 at 09:33:37AM -0700, Mateo Lozano, Oscar wrote:
> > -Original Message-
> > From: Volkin, Bradley D
> > Sent: Monday, May 19, 2014 5:24 PM
> > To: Mateo Lozano, Oscar
> > Cc: Daniel Vetter; intel-gfx@lists.freedesktop.org
> > Subjec
On Mon, May 19, 2014 at 09:49:31AM -0700, Mateo Lozano, Oscar wrote:
> > -Original Message-
> > From: Volkin, Bradley D
> > Sent: Monday, May 19, 2014 5:41 PM
> > To: Mateo Lozano, Oscar
> > Cc: Daniel Vetter; intel-gfx@lists.freedesktop.org
> > Subjec
On Wed, May 21, 2014 at 07:02:56AM -0700, Mika Kuoppala wrote:
> + if (ring->id == RCS && !to->is_initialized && from == NULL) {
> + ret = i915_gem_render_state_init(ring);
> + if (ret)
> + DRM_ERROR("init render state: %d\n", ret);
> + }
Apologi
On Wed, May 28, 2014 at 02:29:34PM -0700, Daniel Vetter wrote:
> Jesse reportedly has a patch somewhere to (finally!) enable ppgtt on
> vlv. Would we still need any part of this with ppgtt support on vlv?
> -Daniel
Of course, as soon as I accept that it'll never happen... :)
Off the top of my hea
On Wed, May 28, 2014 at 03:02:24PM -0700, Jesse Barnes wrote:
> Need testing and possibly disabling on earlier steppings, but looks ok
> here on my B3.
>
> Signed-off-by: Jesse Barnes
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
On Tue, Jun 10, 2014 at 04:14:40AM -0700, Chris Wilson wrote:
> Inserting additional PTEs has no side-effect for us as the pfn are fixed
> for the entire time the object is resident in the global GTT. The
> downside is that we pay the entire cost of faulting the object upon the
> first hit, for whi
On Tue, Jun 10, 2014 at 04:14:41AM -0700, Chris Wilson wrote:
> On an Ivybridge i7-3720qm with 1600MHz DDR3, with 32 fences,
> Upload rate for 2 linear surfaces: 8134MiB/s -> 8154MiB/s
> Upload rate for 2 tiled surfaces: 8625MiB/s -> 8632MiB/s
> Upload rate for 4 linear surfaces: 8127MiB/s -> 8
On Thu, Jun 12, 2014 at 03:13:14PM +0100, Chris Wilson wrote:
> remap_pfn_range() has a nasty surprise if you try to handle two faults
> from the same vma concurrently: that is the second thread hits a BUG()
> to assert that the range is clear. As we hold our struct_mutex whilst
> manipulating the
On Fri, Feb 07, 2014 at 06:45:48AM -0800, Daniel Vetter wrote:
> On Fri, Feb 07, 2014 at 03:58:46PM +0200, Jani Nikula wrote:
> > On Wed, 29 Jan 2014, bradley.d.vol...@intel.com wrote:
> > > +static int valid_reg(const u32 *table, int count, u32 addr)
> > > +{
> > > + if (table && count != 0) {
> >
Daniel, Jani,
I think I managed to send this while you were both out and I'm sure it got
buried. Can you take a look? I think this rev addresses all of the current
comments.
Thanks,
Brad
On Tue, Feb 18, 2014 at 10:15:44AM -0800, Volkin, Bradley D wrote:
> From: Brad Volkin
>
>
On Wed, Mar 05, 2014 at 02:46:35AM -0800, Daniel Vetter wrote:
> On Tue, Feb 18, 2014 at 10:15:44AM -0800, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> > 3) Coherency. I've previously found a coherency issue on VLV when reading
> > the
> >batch buffer from the CPU during execbuff
On Wed, Mar 05, 2014 at 09:14:38AM -0800, Daniel Vetter wrote:
> On Wed, Mar 05, 2014 at 08:59:56AM -0800, Volkin, Bradley D wrote:
> > On Wed, Mar 05, 2014 at 02:46:35AM -0800, Daniel Vetter wrote:
> > > On Tue, Feb 18, 2014 at 10:15:44AM -0800, bradley.d.vol...@inte
On Thu, Mar 06, 2014 at 05:17:59AM -0800, Jani Nikula wrote:
> On Tue, 18 Feb 2014, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> >
> > Various commands that access memory have a bit to determine whether
> > the graphics address specified in the command should use the GGTT or
> > PPGTT
On Thu, Mar 06, 2014 at 01:58:09PM -0800, Daniel Vetter wrote:
> On Thu, Mar 06, 2014 at 01:32:48PM -0800, Volkin, Bradley D wrote:
> > On Thu, Mar 06, 2014 at 05:17:59AM -0800, Jani Nikula wrote:
> > > On Tue, 18 Feb 2014, bradley.d.vol...@intel.com wrote:
> &g
Reviewed-by: Brad Volkin
On Fri, Mar 07, 2014 at 12:30:36AM -0800, Chris Wilson wrote:
> We used to lock individual pages inside the buffer object and so needed
> to update the page flags every time. However, we now pin the pages into
> the object for the duration of the pwrite/pread (and hopeful
Reviewed-by: Brad Volkin
On Fri, Mar 07, 2014 at 12:30:37AM -0800, Chris Wilson wrote:
> We don't always want to write into main memory with pwrite. The shmem
> fast path in particular is used for memory that is cacheable - under
> such circumstances forcing the cache eviction is undesirable. As
On Tue, Mar 11, 2014 at 05:41:06AM -0700, Jani Nikula wrote:
>
> Hi Bradley -
>
> I've now rather meticulously reviewed what *is* in the command and
> register tables, and didn't spot any obvious errors.
Thanks Jani! I know it's a huge pain, so I appreciate you taking the
time for it.
>
> Ther
Thanks for fixing this Damien.
Reviewed-by: Brad Volkin
On Tue, Mar 18, 2014 at 05:43:08PM +, Damien Lespiau wrote:
> When compiling on 32bits, I have the following warning:
>
> drivers/gpu/drm/i915/i915_cmd_parser.c:405:4: warning: format ‘%ld’
> expects argument of type ‘long int’, but ar
On Tue, Mar 25, 2014 at 06:15:36AM -0700, Daniel Vetter wrote:
> On Thu, Mar 20, 2014 at 04:43:05PM +0200, Jani Nikula wrote:
> >
> > Hi Bradley -
> >
> > Apologies for my procrastination with the review; I don't easily recall
> > as tedious a review as the command and register tables. And I sure
On Tue, Mar 25, 2014 at 06:17:55AM -0700, Daniel Vetter wrote:
> On Thu, Jan 30, 2014 at 11:46:15AM +, Chris Wilson wrote:
> > On Wed, Jan 29, 2014 at 10:10:47PM +, Chris Wilson wrote:
> > > On Wed, Jan 29, 2014 at 01:58:29PM -0800, bradley.d.vol...@intel.com
> > > wrote:
> > > > From: Bra
On Tue, Mar 25, 2014 at 11:21:23PM -0700, Daniel Vetter wrote:
> On Tue, Mar 25, 2014 at 10:52:03PM -0700, Kenneth Graunke wrote:
> > Mesa needs to be able to write OACONTROL in order to expose the
> > Observability Architecture's performance counters via OpenGL.
> >
> > Signed-off-by: Kenneth Gra
On Wed, Mar 26, 2014 at 10:37:44AM -0700, Kenneth Graunke wrote:
> On 03/26/2014 09:38 AM, Daniel Vetter wrote:
> > On Wed, Mar 26, 2014 at 09:03:58AM -0700, Volkin, Bradley D wrote:
> >> On Tue, Mar 25, 2014 at 11:21:23PM -0700, Daniel Vetter wrote:
> >>> On Tue, Ma
[snip]
On Thu, Mar 27, 2014 at 12:57:21AM -0700, Daniel Vetter wrote:
> Another one that blows is igt/gen7_forcewake_mt. Not sure yet whether it's
> an issue with the test or the checker:
>
> https://bugs.freedesktop.org/show_bug.cgi?id=76670
For this one, the parser rejects an MI_STORE_REGISTER
On Thu, Mar 27, 2014 at 01:16:26PM -0700, Daniel Vetter wrote:
> On Thu, Mar 27, 2014 at 4:57 PM, Volkin, Bradley D
> wrote:
> > On Thu, Mar 27, 2014 at 12:57:21AM -0700, Daniel Vetter wrote:
> >> Another one that blows is igt/gen7_forcewake_mt. Not sure yet whether it
On Thu, Mar 27, 2014 at 02:47:03PM -0700, Kenneth Graunke wrote:
> Does any code actually rely on the tables being sorted?
Not today. The idea was to make it easier to move to an algorithm that does
in the future. For example, I thought binary search might be an easy win.
>
> I didn't see any ea
On Thu, Mar 27, 2014 at 02:58:01PM -0700, Kenneth Graunke wrote:
> On 03/27/2014 11:43 AM, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> >
> > There is some thought that the data from the performance counters enabled
> > via OACONTROL should only be available to the process that enabl
On Mon, Mar 17, 2014 at 05:21:55AM -0700, Chris Wilson wrote:
> A common issue we have is that retiring requests causes recursion
> through GTT manipulation or page table manipulation which we can only
> handle at very specific points. However, to maintain internal
> consistency (enforced through o
Hi Daniel, we've merged the kernel change for this but not the test. I'm
assuming we still want the test case.
Brad
On Thu, Mar 27, 2014 at 11:44:45AM -0700, Volkin, Bradley D wrote:
> From: Brad Volkin
>
> Signed-off-by: Brad Volkin
> ---
> te
On Tue, Apr 08, 2014 at 11:20:30PM -0700, Chris Wilson wrote:
> On Tue, Apr 08, 2014 at 02:22:16PM -0700, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> >
> > The command parser in newer kernels will reject it and setting this
> > bit is not required for the actual test case.
> >
> >
On Tue, Nov 26, 2013 at 09:29:32AM -0800, Chris Wilson wrote:
> On Tue, Nov 26, 2013 at 08:51:22AM -0800, bradley.d.vol...@intel.com wrote:
> > +static const struct drm_i915_cmd_descriptor*
> > +find_cmd_in_table(const struct drm_i915_cmd_table *table,
> > + u32 cmd_header)
> > +{
> > +
On Tue, Nov 26, 2013 at 09:56:09AM -0800, Chris Wilson wrote:
> On Tue, Nov 26, 2013 at 09:38:55AM -0800, Volkin, Bradley D wrote:
> > On Tue, Nov 26, 2013 at 09:29:32AM -0800, Chris Wilson wrote:
> > > On Tue, Nov 26, 2013 at 08:51:22AM -0800, bradley.d.vol...@inte
On Tue, Nov 26, 2013 at 10:08:48AM -0800, Chris Wilson wrote:
> On Tue, Nov 26, 2013 at 08:51:37AM -0800, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> >
> > The length mask is different for each ring and the size can vary,
> > so we should duplicate the definition with the correct en
On Tue, Nov 26, 2013 at 11:35:38AM -0800, Daniel Vetter wrote:
> Hi Brad,
>
> On Tue, Nov 26, 2013 at 08:51:17AM -0800, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> >
> > Certain OpenGL features (e.g. transform feedback, performance monitoring)
> > require userspace code to submit b
On Wed, Dec 04, 2013 at 12:13:39AM -0800, Daniel Vetter wrote:
> On Tue, Nov 26, 2013 at 9:24 PM, Volkin, Bradley D
> wrote:
>
> [snip]
>
> > Which "state setup stuff" are you referring to? Something specific in i-g-t
> > or something
> > more g
On Thu, Dec 05, 2013 at 01:38:00AM -0800, Kenneth Graunke wrote:
> On 11/27/2013 04:51 AM, Daniel Vetter wrote:
> > On Tue, Nov 26, 2013 at 08:51:23AM -0800, bradley.d.vol...@intel.com wrote:
> >> From: Brad Volkin
> >>
> >> So userspace can query the kernel for command parser support.
> >>
> >> O
On Tue, Nov 26, 2013 at 12:24:14PM -0800, Volkin, Bradley D wrote:
> On Tue, Nov 26, 2013 at 11:35:38AM -0800, Daniel Vetter wrote:
> > I think long-term we should even scan secure batches. We'd need to allow
> > some registers which only the drm master (i.e. owner of the disp
On Tue, Nov 26, 2013 at 09:56:09AM -0800, Chris Wilson wrote:
> On Tue, Nov 26, 2013 at 09:38:55AM -0800, Volkin, Bradley D wrote:
> > On Tue, Nov 26, 2013 at 09:29:32AM -0800, Chris Wilson wrote:
> > > On Tue, Nov 26, 2013 at 08:51:22AM -0800, bradley.d.vol...@inte
[snip]
On Tue, Nov 26, 2013 at 11:35:38AM -0800, Daniel Vetter wrote:
> > 2) Coherency. I've found two types of coherency issues when reading the
> > batch
> >buffer from the CPU during execbuffer2. Looking for help with both
> > issues.
> > i. First, the i-g-t test gem_cpu_reloc blits t
On Wed, Dec 11, 2013 at 01:54:40AM -0800, Daniel Vetter wrote:
> On Tue, Dec 10, 2013 at 04:58:18PM -0800, Volkin, Bradley D wrote:
> > So, I have a functioning kmap_atomic based parser using an sg_mapping_iter,
> > and in the
> > tests I'm running, it's worse
Hi Chris,
A few questions/comments throughout. I may be off the mark on some. Please
bear with me as I try to get more familiar with the gem code.
Thanks,
Brad
[ snip ]
On Fri, Jan 24, 2014 at 01:00:19AM -0800, Chris Wilson wrote:
> +static void
> +__i915_mmu_notifier_destroy_worker(struct work
On Wed, Jan 29, 2014 at 02:11:17PM -0800, Daniel Vetter wrote:
> On Wed, Jan 29, 2014 at 01:55:01PM -0800, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> > 3) Coherency. I've found a coherency issue on VLV when reading the batch
> > buffer
> >from the CPU during execbuffer2. Usersp
On Wed, Jan 29, 2014 at 02:13:21PM -0800, Chris Wilson wrote:
> On Wed, Jan 29, 2014 at 01:57:28PM -0800, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> >
> > Signed-off-by: Brad Volkin
> > ---
> > include/drm/i915_drm.h | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
On Wed, Jan 29, 2014 at 02:33:55PM -0800, Chris Wilson wrote:
> On Wed, Jan 29, 2014 at 01:55:11PM -0800, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> >
> > Various commands that access memory have a bit to determine whether
> > the graphics address specified in the command should us
On Wed, Jan 29, 2014 at 02:37:25PM -0800, Chris Wilson wrote:
> On Wed, Jan 29, 2014 at 01:55:08PM -0800, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> >
> > These are used to implement scanline waits in the X server.
> >
> > Signed-off-by: Brad Volkin
> > ---
> > drivers/gpu/drm/i
On Thu, Jan 30, 2014 at 01:19:15AM -0800, Daniel Vetter wrote:
> On Wed, Jan 29, 2014 at 01:55:13PM -0800, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> >
> > So userspace can query the kernel for command parser support.
> >
> > OTC-Tracker: AXIA-4631
> > Change-Id: I58af650db9f6753c
On Thu, Jan 30, 2014 at 01:20:57AM -0800, Daniel Vetter wrote:
> On Wed, Jan 29, 2014 at 02:26:12PM -0800, Volkin, Bradley D wrote:
> > On Wed, Jan 29, 2014 at 02:13:21PM -0800, Chris Wilson wrote:
> > > On Wed, Jan 29, 2014 at 01:57:28PM -0800, bradley.d.vol...@inte
On Thu, Jan 30, 2014 at 01:12:06AM -0800, Daniel Vetter wrote:
> On Thu, Jan 30, 2014 at 10:05:28AM +0100, Daniel Vetter wrote:
> > On Thu, Jan 30, 2014 at 09:53:28AM +0100, Daniel Vetter wrote:
> > > On Wed, Jan 29, 2014 at 10:28:36PM +, Chris Wilson wrote:
> > > > On Wed, Jan 29, 2014 at 01:5
On Thu, Jan 30, 2014 at 03:07:15AM -0800, Daniel Vetter wrote:
> On Thu, Jan 30, 2014 at 10:12:06AM +0100, Daniel Vetter wrote:
> > On Thu, Jan 30, 2014 at 10:05:28AM +0100, Daniel Vetter wrote:
> > > On Thu, Jan 30, 2014 at 09:53:28AM +0100, Daniel Vetter wrote:
> > > > On Wed, Jan 29, 2014 at 10:
Ping. Daniel or Chris, can one of you clarify this request? Thanks.
On Thu, Jan 30, 2014 at 10:05:27AM -0800, Volkin, Bradley D wrote:
> On Thu, Jan 30, 2014 at 03:07:15AM -0800, Daniel Vetter wrote:
> > On Thu, Jan 30, 2014 at 10:12:06AM +0100, Daniel Vetter wrote:
> > > On Th
On Tue, Feb 04, 2014 at 02:20:36AM -0800, Daniel Vetter wrote:
> On Mon, Feb 03, 2014 at 03:00:19PM -0800, Volkin, Bradley D wrote:
> > Ping. Daniel or Chris, can one of you clarify this request? Thanks.
>
> I've been enjoying fosdem ...
>
> > On Thu, Jan 30, 201
On Tue, Feb 04, 2014 at 11:33:31AM -0800, Daniel Vetter wrote:
> On Tue, Feb 04, 2014 at 10:45:45AM -0800, Volkin, Bradley D wrote:
> > The current table structure is that we have tables per-ring and per-gen
> > (plus the table
> > for common MI commands) and all tables are
On Wed, Feb 05, 2014 at 02:28:29AM -0800, Chris Wilson wrote:
> On Tue, Nov 26, 2013 at 08:51:17AM -0800, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> >
> > Certain OpenGL features (e.g. transform feedback, performance monitoring)
> > require userspace code to submit batches containi
On Wed, Feb 05, 2014 at 07:15:35AM -0800, Jani Nikula wrote:
> On Wed, 29 Jan 2014, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> >
> > The command parser scans batch buffers submitted via execbuffer ioctls
> > before
> > the driver submits them to hardware. At a high level, it looks
[snip]
On Wed, Feb 05, 2014 at 07:22:33AM -0800, Jani Nikula wrote:
> On Wed, 29 Jan 2014, bradley.d.vol...@intel.com wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 13ed6ed..2b7c26e 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b
On Wed, Feb 05, 2014 at 07:29:12AM -0800, Jani Nikula wrote:
> On Wed, 29 Jan 2014, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> >
> > These registers are currently used by mesa for blitting,
> > transform feedback extensions, and performance monitoring
> > extensions.
> >
> > Signed-
On Wed, Feb 05, 2014 at 07:33:28AM -0800, Jani Nikula wrote:
> On Wed, 29 Jan 2014, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> >
> > MI_STORE_REGISTER_MEM, MI_LOAD_REGISTER_MEM, and MI_LOAD_REGISTER_IMM
> > commands allow userspace access to registers. Only certain registers
> > sho
[snip]
On Wed, Feb 05, 2014 at 07:37:51AM -0800, Jani Nikula wrote:
> On Wed, 29 Jan 2014, bradley.d.vol...@intel.com wrote:
> > int i915_needs_cmd_parser(struct intel_ring_buffer *ring)
> > {
> > + drm_i915_private_t *dev_priv =
> > + (drm_i915_private_t *)ring->dev->dev_private;
>
On Wed, Feb 05, 2014 at 10:30:00AM -0800, Daniel Vetter wrote:
> On Wed, Feb 5, 2014 at 7:18 PM, Volkin, Bradley D
> wrote:
> > On Wed, Feb 05, 2014 at 02:28:29AM -0800, Chris Wilson wrote:
> >> On Tue, Nov 26, 2013 at 08:51:17AM -0800, bradley.d.vol...@intel.com wrote:
>
On Wed, Feb 05, 2014 at 11:17:25AM -0800, Daniel Vetter wrote:
> On Wed, Feb 5, 2014 at 8:00 PM, Volkin, Bradley D
> wrote:
> > To test/merge, we'd have to change the series to take out the part where
> > patch 02/13 sets I915_DISPATCH_SECURE to avoid a BUG_ON() when
>
On Thu, Oct 30, 2014 at 04:03:23PM -0700, armin.c.re...@intel.com wrote:
> From: Armin Reese
>
> The new 'i915_context_dump' file generates a hex dump of the
> entire logical context DRM object. It is useful for
> validating the contents of the default context set up by
> the golden state batch
On Mon, Nov 03, 2014 at 11:19:40AM -0800, Volkin, Bradley D wrote:
> From: Brad Volkin
>
> This is v3 of the series I sent here:
> http://lists.freedesktop.org/archives/intel-gfx/2014-July/048705.html
>
> Most of the previous commentary still applies. We've fixe
On Tue, Nov 04, 2014 at 02:17:59AM -0800, Daniel Vetter wrote:
> On Mon, Nov 03, 2014 at 11:19:42AM -0800, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> >
> > This patch sets up all of the tracking and copying necessary to
> > use batch pools with the command parser and dispatches the
On Tue, Nov 04, 2014 at 02:30:14AM -0800, Daniel Vetter wrote:
> On Mon, Nov 03, 2014 at 11:19:42AM -0800, bradley.d.vol...@intel.com wrote:
> > + flags |= I915_DISPATCH_SECURE;
>
> I've forgotten one: You must have a full ppgtt check here since the
> binding for aliasing ppgtt i
[snip]
On Wed, Nov 05, 2014 at 01:50:24AM -0800, Daniel Vetter wrote:
> On Tue, Nov 04, 2014 at 08:35:00AM -0800, Volkin, Bradley D wrote:
> > On Tue, Nov 04, 2014 at 02:17:59AM -0800, Daniel Vetter wrote:
> > > On Mon, Nov 03, 2014 at 11:19:42AM -0800, bradley.d.vol...@inte
1 - 100 of 138 matches
Mail list logo
