[Intel-gfx] [PATCH 00/14] Adding NV12 support

This patch series is adding NV12 support for Broxton display after rebasing on latest drm-tip. Initial series of the patches can be found here: https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html Previous revision history: The first version of patches were reviewed when floated b

[Intel-gfx] [PATCH 08/14] drm/i915/skl+: nv12 workaround disable WM level 1-7

From: Mahesh Kumar Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A) Hardware sometimes fails to wake memory from pkg C states fetching the last few lines of planar YUV 420 (NV12) planes. This causes intermittent underflow and corruption. WA: Disable package C states or do not enable late

[Intel-gfx] [PATCH 07/14] drm/i915/skl+: make sure higher latency level has higher wm value

From: Mahesh Kumar DDB allocation optimization algorithm require/assumes ddb allocation for any memory C-state level DDB value to be as high as level below. Render decompression require level WM to be as high as wm level-0. This patch fulfils both the requirements. Signed-off-by: Mahesh Kumar -

[Intel-gfx] [PATCH 10/14] drm/i915: Update format_is_yuv() to include NV12

y: Clinton Taylor Reviewed-by: Clinton Taylor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_sprite.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/d

[Intel-gfx] [PATCH 09/14] drm/i915: Set scaler mode for NV12

-by: Clinton Taylor Reviewed-by: Clinton Taylor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_atomic.c | 8 +++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH 11/14] drm/i915: Upscale scaler max scale for NV12

issue here. v7: Rebased (me) v8: Rebased (me) Tested-by: Clinton Taylor Reviewed-by: Clinton Taylor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_display.c | 33 +++-- drivers/gpu/drm

[Intel-gfx] [PATCH 12/14] drm/i915: Add NV12 as supported format for primary plane

NV12 support for both BXT and KBL. Tested-by: Clinton Taylor Reviewed-by: Clinton Taylor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_display.c | 26 -- 1 file changed, 24 insertions(+), 2

[Intel-gfx] [PATCH 14/14] drm/i915: Add NV12 support to intel_framebuffer_init

cting the NV12 changes to BXT and KBL for now. Tested-by: Clinton Taylor Reviewed-by: Clinton Taylor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_display.c | 8 1 file changed, 8 insertions(+) diff --

[Intel-gfx] [PATCH 13/14] drm/i915: Add NV12 as supported format for sprite plane

aylor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_sprite.c | 24 +--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/

[Intel-gfx] [PATCH 10/16] drm/i915: Set scaler mode for NV12

ode to be applicable to all Gen. Tested-by: Clinton Taylor Reviewed-by: Clinton Taylor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_atomic.c | 8 ++-- 2 files changed

[Intel-gfx] [PATCH 06/16] drm/i915/skl+: pass skl_wm_level struct to wm compute func

Sharma Signed-off-by: Mahesh Kumar Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_pm.c | 18 +++--- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2a0cc0b..f6ad1bf 100644 --- a

[Intel-gfx] [PATCH 09/16] drm/i915/skl: split skl_compute_ddb function

From: Mahesh Kumar This patch splits skl_compute_wm/ddb functions into two parts. One adds all affected pipes after the commit to atomic_state structure and second part does compute the DDB. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/intel_pm.c | 157 ++---

[Intel-gfx] [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12

From: Mahesh Kumar For YUV 420 Planar formats like NV12, buffer allocation is done for Y and UV surfaces separately. For NV12 plane formats, the UV buffer allocation must be programmed in the Plane Buffer Config register and the Y buffer allocation must be programmed in the Plane NV12 Buffer Conf

[Intel-gfx] [PATCH 07/16] drm/i915/skl+: make sure higher latency level has higher wm value

From: Mahesh Kumar DDB allocation optimization algorithm requires/assumes ddb allocation for any memory C-state level DDB value to be as high as level below the current level. Render decompression requires level WM to be as high as wm level-0. This patch fulfils both the requirements. Signed-off

[Intel-gfx] [PATCH 12/16] drm/i915: Upscale scaler max scale for NV12

lor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_display.c | 40 ++-- drivers/gpu/drm/i915/intel_drv.h | 3 ++- drivers/gpu/drm/i915/intel_sprite.c | 3 ++- 3 files changed,

[Intel-gfx] [PATCH 08/16] drm/i915/skl+: nv12 workaround disable WM level 1-7

able latency levels 1 through 7 (WM1 - WM7) on NV12 planes. v2: Addressed review comments by Maarten. Reviewed-by: Maarten Lankhorst Signed-off-by: Mahesh Kumar Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_pm.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/dri

[Intel-gfx] [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM

From: Mahesh Kumar NV12 requires WM calculation for UV plane as well. UV plane WM should also fulfill all the WM related restrictions. v2: Addressed review comments from Shashank Sharma. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_drv.h

[Intel-gfx] [PATCH 03/16] drm/i915/skl+: add NV12 in skl_format_to_fourcc

From: Mahesh Kumar Add support of recognizing DRM_FORMAT_NV12 from plane_format register value. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/intel_display.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.

[Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane

: Rebased (me) v10: Addressed review comments from Maarten. Adding NV12 inside skl_primary_formats itself. Tested-by: Clinton Taylor Reviewed-by: Clinton Taylor Reviewed-by: Shashank Sharma Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas

[Intel-gfx] [PATCH 11/16] drm/i915: Update format_is_yuv() to include NV12

mat_is_yuv function from static to non-static. We need to use it later from other files for check. Tested-by: Clinton Taylor Reviewed-by: Clinton Taylor Reviewed-by: Shashank Sharma Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i

[Intel-gfx] [PATCH 02/16] drm/i915/skl+: refactor WM calculation for NV12

ssed review comments by Maarten Reviewed-by: Maarten Lankhorst Signed-off-by: Mahesh Kumar Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_drv.h | 5 +- drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 121 --- 3 f

[Intel-gfx] [PATCH 01/16] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

From: Mahesh Kumar skl_wm_values struct contains values of pipe/plane DDB only. so rename it for better readability of code. Similarly skl_copy_wm_for_pipe copies DDB values. s/skl_wm_values/skl_ddb_values s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe Changes since V1: - also change name of skl

[Intel-gfx] [PATCH 14/16] drm/i915: Add NV12 as supported format for sprite plane

inton Taylor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_sprite.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 77a5433..

[Intel-gfx] [PATCH 15/16] drm/i915: Add NV12 support to intel_framebuffer_init

u Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_display.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 6f43d72..42ec089 100644 --- a/drivers

[Intel-gfx] [PATCH 00/16] Adding NV12 support

to wm compute func drm/i915/skl+: make sure higher latency level has higher wm value drm/i915/skl+: nv12 workaround disable WM level 1-7 drm/i915/skl: split skl_compute_ddb function Vidya Srinivas (1): drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg drivers/gpu/drm/i915/i915_drv.h

[Intel-gfx] [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

If the fb format is YUV, enable the plane CSC mode bits for the conversion. Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_reg.h | 6 ++ drivers/gpu/drm/i915/intel_display.c | 2 ++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers

[Intel-gfx] [PATCH 01/16] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

From: Mahesh Kumar skl_wm_values struct contains values of pipe/plane DDB only. so rename it for better readability of code. Similarly skl_copy_wm_for_pipe copies DDB values. s/skl_wm_values/skl_ddb_values s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe Changes since V1: - also change name of skl

[Intel-gfx] [PATCH 03/16] drm/i915/skl+: add NV12 in skl_format_to_fourcc

From: Mahesh Kumar Add support of recognizing DRM_FORMAT_NV12 from plane_format register value. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/intel_display.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.

[Intel-gfx] [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12

From: Mahesh Kumar For YUV 420 Planar formats like NV12, buffer allocation is done for Y and UV surfaces separately. For NV12 plane formats, the UV buffer allocation must be programmed in the Plane Buffer Config register and the Y buffer allocation must be programmed in the Plane NV12 Buffer Conf

[Intel-gfx] [PATCH 08/16] drm/i915/skl+: nv12 workaround disable WM level 1-7

able latency levels 1 through 7 (WM1 - WM7) on NV12 planes. v2: Addressed review comments by Maarten. v3: Adding reviewed by tag from Shashank Sharma Reviewed-by: Shashank Sharma Reviewed-by: Maarten Lankhorst Signed-off-by: Mahesh Kumar Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/

[Intel-gfx] [PATCH 14/16] drm/i915: Add NV12 as supported format for sprite plane

inton Taylor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_sprite.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 77a5433..

[Intel-gfx] [PATCH 11/16] drm/i915: Update format_is_yuv() to include NV12

mat_is_yuv function from static to non-static. We need to use it later from other files for check. Tested-by: Clinton Taylor Reviewed-by: Clinton Taylor Reviewed-by: Shashank Sharma Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i

[Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane

: Rebased (me) v10: Addressed review comments from Maarten. Adding NV12 inside skl_primary_formats itself. Tested-by: Clinton Taylor Reviewed-by: Clinton Taylor Reviewed-by: Shashank Sharma Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas

[Intel-gfx] [PATCH 06/16] drm/i915/skl+: pass skl_wm_level struct to wm compute func

Sharma Signed-off-by: Mahesh Kumar Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_pm.c | 18 +++--- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index bfe64a9..5154ce3 100644 --- a

[Intel-gfx] [PATCH 12/16] drm/i915: Upscale scaler max scale for NV12

lor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_display.c | 40 ++-- drivers/gpu/drm/i915/intel_drv.h | 3 ++- drivers/gpu/drm/i915/intel_sprite.c | 3 ++- 3 files changed,

[Intel-gfx] [PATCH 00/16] Adding NV12 support

related changes for WM drm/i915/skl+: pass skl_wm_level struct to wm compute func drm/i915/skl+: make sure higher latency level has higher wm value drm/i915/skl+: nv12 workaround disable WM level 1-7 drm/i915/skl: split skl_compute_ddb function Vidya Srinivas (1): drm/i915: Enable YUV to

[Intel-gfx] [PATCH 10/16] drm/i915: Set scaler mode for NV12

ode to be applicable to all Gen. Tested-by: Clinton Taylor Reviewed-by: Clinton Taylor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_atomic.c | 8 ++-- 2 files changed

[Intel-gfx] [PATCH 02/16] drm/i915/skl+: refactor WM calculation for NV12

ssed review comments by Maarten v4: Fixed a compilation issue of string replacement is_nv12 to is_planar Reviewed-by: Maarten Lankhorst Signed-off-by: Mahesh Kumar Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_drv.h | 5 +- drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu

[Intel-gfx] [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM

skl_compute_plane_wm_params and skl_compute_plane_wm. Adding reviewed by tag from Shashank Sharma Reviewed-by: Shashank Sharma Signed-off-by: Mahesh Kumar Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 50

[Intel-gfx] [PATCH 07/16] drm/i915/skl+: make sure higher latency level has higher wm value

: Changed plane_num to plane_id in skl_compute_wm_levels Signed-off-by: Mahesh Kumar Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_pm.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 5154ce3

[Intel-gfx] [PATCH 15/16] drm/i915: Add NV12 support to intel_framebuffer_init

u Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_display.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 6f43d72..42ec089 100644 --- a/drivers

[Intel-gfx] [PATCH 09/16] drm/i915/skl: split skl_compute_ddb function

From: Mahesh Kumar This patch splits skl_compute_wm/ddb functions into two parts. One adds all affected pipes after the commit to atomic_state structure and second part does compute the DDB. v2: Added reviewed by tag from Shashank Sharma Reviewed-by: Shashank Sharma Signed-off-by: Mahesh Kumar

[Intel-gfx] [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

If the fb format is YUV, enable the plane CSC mode bits for the conversion. Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_reg.h | 6 ++ drivers/gpu/drm/i915/intel_display.c | 2 ++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers

[Intel-gfx] [PATCH 00/16] Adding NV12 support

WM level 1-7 drm/i915/skl: split skl_compute_ddb function Vidya Srinivas (1): drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg drivers/gpu/drm/i915/i915_drv.h | 10 +- drivers/gpu/drm/i915/i915_reg.h | 8 + drivers/gpu/drm/i915/intel_atomic.c | 13 +- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 01/16] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

From: Mahesh Kumar skl_wm_values struct contains values of pipe/plane DDB only. so rename it for better readability of code. Similarly skl_copy_wm_for_pipe copies DDB values. s/skl_wm_values/skl_ddb_values s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe Changes since V1: - also change name of skl

[Intel-gfx] [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12

From: Mahesh Kumar For YUV 420 Planar formats like NV12, buffer allocation is done for Y and UV surfaces separately. For NV12 plane formats, the UV buffer allocation must be programmed in the Plane Buffer Config register and the Y buffer allocation must be programmed in the Plane NV12 Buffer Conf

[Intel-gfx] [PATCH 03/16] drm/i915/skl+: add NV12 in skl_format_to_fourcc

From: Mahesh Kumar Add support of recognizing DRM_FORMAT_NV12 from plane_format register value. v2: Added reviewed by tag from Mika Kahola Reviewed-by: Mika Kahola Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/intel_display.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drive

[Intel-gfx] [PATCH 07/16] drm/i915/skl+: make sure higher latency level has higher wm value

From: Mahesh Kumar DDB allocation optimization algorithm requires/assumes ddb allocation for any memory C-state level DDB value to be as high as level below the current level. Render decompression requires level WM to be as high as wm level-0. This patch fulfils both the requirements. v2: Change

[Intel-gfx] [PATCH 06/16] drm/i915/skl+: pass skl_wm_level struct to wm compute func

tag from Shashank Sharma Reviewed-by: Shashank Sharma Signed-off-by: Mahesh Kumar Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_pm.c | 18 +++--- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 02/16] drm/i915/skl+: refactor WM calculation for NV12

ssed review comments by Maarten v4: Fixed a compilation issue of string replacement is_nv12 to is_planar Reviewed-by: Maarten Lankhorst Signed-off-by: Mahesh Kumar Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_drv.h | 5 +- drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu

[Intel-gfx] [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM

skl_compute_plane_wm_params and skl_compute_plane_wm. Adding reviewed by tag from Shashank Sharma Reviewed-by: Shashank Sharma Signed-off-by: Mahesh Kumar Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 50

[Intel-gfx] [PATCH 15/16] drm/i915: Add NV12 support to intel_framebuffer_init

-by: Shashank Sharma Reviewed-by: Clinton Taylor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_display.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers

[Intel-gfx] [PATCH 14/16] drm/i915: Add NV12 as supported format for sprite plane

hank Sharma Made the condition in intel_sprite_plane_create simple and easy to read as suggested. Tested-by: Clinton Taylor Reviewed-by: Clinton Taylor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_sprite.c | 9

[Intel-gfx] [PATCH 11/16] drm/i915: Update format_is_yuv() to include NV12

mat_is_yuv function from static to non-static. We need to use it later from other files for check. Tested-by: Clinton Taylor Reviewed-by: Clinton Taylor Reviewed-by: Shashank Sharma Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i

[Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane

: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_display.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 142dfe0..1870366 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b

[Intel-gfx] [PATCH 08/16] drm/i915/skl+: nv12 workaround disable WM level 1-7

able latency levels 1 through 7 (WM1 - WM7) on NV12 planes. v2: Addressed review comments by Maarten. v3: Adding reviewed by tag from Shashank Sharma Reviewed-by: Shashank Sharma Reviewed-by: Maarten Lankhorst Signed-off-by: Mahesh Kumar Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/

[Intel-gfx] [PATCH 10/16] drm/i915: Set scaler mode for NV12

uru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_atomic.c | 13 +++-- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h in

[Intel-gfx] [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

If the fb format is YUV, enable the plane CSC mode bits for the conversion. v2: Addressed review comments from Shashank Sharma Alignment issue fixed in i915_reg.h v3: Adding Reviewed By from Shashank Sharma Reviewed-by: Shashank Sharma Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 12/16] drm/i915: Upscale scaler max scale for NV12

ned-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_display.c | 40 ++-- drivers/gpu/drm/i915/intel_drv.h | 3 ++- drivers/gpu/drm/i915/intel_sprite.c | 3 ++- 3 files changed, 33 insertions(+), 13 deletions(-) diff --gi

[Intel-gfx] [PATCH 09/16] drm/i915/skl: split skl_compute_ddb function

From: Mahesh Kumar This patch splits skl_compute_wm/ddb functions into two parts. One adds all affected pipes after the commit to atomic_state structure and second part does compute the DDB. v2: Added reviewed by tag from Shashank Sharma Reviewed-by: Shashank Sharma Signed-off-by: Mahesh Kumar

[Intel-gfx] [PATCH v13 02/17] drm/i915/skl+: refactor WM calculation for NV12

ssed review comments by Maarten v4: Fixed a compilation issue of string replacement is_nv12 to is_planar Reviewed-by: Maarten Lankhorst Signed-off-by: Mahesh Kumar Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_drv.h | 5 +- drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu

[Intel-gfx] [PATCH v13 09/17] drm/i915/skl: split skl_compute_ddb function

From: Mahesh Kumar This patch splits skl_compute_wm/ddb functions into two parts. One adds all affected pipes after the commit to atomic_state structure and second part does compute the DDB. v2: Added reviewed by tag from Shashank Sharma Reviewed-by: Shashank Sharma Signed-off-by: Mahesh Kumar

[Intel-gfx] [PATCH v13 03/17] drm/i915/skl+: add NV12 in skl_format_to_fourcc

From: Mahesh Kumar Add support of recognizing DRM_FORMAT_NV12 from plane_format register value. v2: Added reviewed by tag from Mika Kahola Reviewed-by: Mika Kahola Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/intel_display.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drive

[Intel-gfx] [PATCH v13 15/17] drm/i915: Add NV12 support to intel_framebuffer_init

om Juha-Pekka Heikkila "NV12 not to be supported by SKL" Tested-by: Clinton Taylor Reviewed-by: Shashank Sharma Reviewed-by: Clinton Taylor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_display.c | 8

[Intel-gfx] [PATCH v13 01/17] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

From: Mahesh Kumar skl_wm_values struct contains values of pipe/plane DDB only. so rename it for better readability of code. Similarly skl_copy_wm_for_pipe copies DDB values. s/skl_wm_values/skl_ddb_values s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe Changes since V1: - also change name of skl

[Intel-gfx] [PATCH v13 00/17] Add NV12 support

higher wm value drm/i915/skl+: nv12 workaround disable WM level 1-7 drm/i915/skl: split skl_compute_ddb function Vidya Srinivas (2): drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg drm/i915: Display WA 827 drivers/gpu/drm/i915/i915_drv.h | 10 +- drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH v13 14/17] drm/i915: Add NV12 as supported format for sprite plane

_formats to include NV12 and a check skl_plane_has_planar in sprite create Added NV12 format to skl_mod_supported Tested-by: Clinton Taylor Reviewed-by: Shashank Sharma Reviewed-by: Clinton Taylor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srini

[Intel-gfx] [PATCH v13 07/17] drm/i915/skl+: make sure higher latency level has higher wm value

From: Mahesh Kumar DDB allocation optimization algorithm requires/assumes ddb allocation for any memory C-state level DDB value to be as high as level below the current level. Render decompression requires level WM to be as high as wm level-0. This patch fulfils both the requirements. v2: Change

[Intel-gfx] [PATCH v13 04/17] drm/i915/skl+: support verification of DDB HW state for NV12

From: Mahesh Kumar For YUV 420 Planar formats like NV12, buffer allocation is done for Y and UV surfaces separately. For NV12 plane formats, the UV buffer allocation must be programmed in the Plane Buffer Config register and the Y buffer allocation must be programmed in the Plane NV12 Buffer Conf

[Intel-gfx] [PATCH v13 08/17] drm/i915/skl+: nv12 workaround disable WM level 1-7

able latency levels 1 through 7 (WM1 - WM7) on NV12 planes. v2: Addressed review comments by Maarten. v3: Adding reviewed by tag from Shashank Sharma Reviewed-by: Shashank Sharma Reviewed-by: Maarten Lankhorst Signed-off-by: Mahesh Kumar Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/

[Intel-gfx] [PATCH v13 12/17] drm/i915: Upscale scaler max scale for NV12

ton Taylor Reviewed-by: Clinton Taylor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Uma Shankar Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_display.c | 78 ++-- drivers/gpu/drm/i915/intel_drv.h | 4 +- driv

[Intel-gfx] [PATCH v13 11/17] drm/i915: Update format_is_yuv() to include NV12

static. So this patch after rebase just adds NV12 to intel_format_is_yuv function. Tested-by: Clinton Taylor Reviewed-by: Clinton Taylor Reviewed-by: Shashank Sharma Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_dr

[Intel-gfx] [PATCH v13 13/17] drm/i915: Add NV12 as supported format for primary plane

endu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_display.c | 50 ++-- drivers/gpu/drm/i915/intel_drv.h | 2 ++ 2 files changed, 50 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gp

[Intel-gfx] [PATCH v13 05/17] drm/i915/skl+: NV12 related changes for WM

skl_compute_plane_wm_params and skl_compute_plane_wm. Adding reviewed by tag from Shashank Sharma Reviewed-by: Shashank Sharma Signed-off-by: Mahesh Kumar Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 50

[Intel-gfx] [PATCH v13 06/17] drm/i915/skl+: pass skl_wm_level struct to wm compute func

tag from Shashank Sharma Reviewed-by: Shashank Sharma Signed-off-by: Mahesh Kumar Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_pm.c | 18 +++--- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH v13 10/17] drm/i915: Set scaler mode for NV12

d by SKL" Adding Reviewed by tag from Shashank Shamr Tested-by: Clinton Taylor Reviewed-by: Shashank Sharma Reviewed-by: Clinton Taylor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers

[Intel-gfx] [PATCH v13 17/17] drm/i915: Display WA 827

f-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_display.c | 31 +++ 2 files changed, 34 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu

[Intel-gfx] [PATCH v13 16/17] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

already merged. plane_state->base.color_encoding might not be set for NV12. For now, just using PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 in glk_plane_color_ctl if format is NV12. Reviewed-by: Shashank Sharma Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_display.c | 8 +++- 1 f

[Intel-gfx] [PATCH 6/6] drm/i915: Add NV12 support to intel_framebuffer_init

inton Taylor Reviewed-by: Clinton Taylor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_display.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm

[Intel-gfx] [PATCH 4/6] drm/i915: Add NV12 as supported format for primary plane

Reviewed-by: Clinton Taylor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_display.c | 26 -- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b

[Intel-gfx] [PATCH 2/6] drm/i915: Update format_is_yuv() to include NV12

Reviewed-by: Clinton Taylor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_sprite.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gp

[Intel-gfx] [PATCH 0/6] Adding NV12 support

This patch series is adding NV12 support for Broxton display after rebasing on latest drm-intel-nightly. Initial series of the patches can be found here: https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html Previous revision history: Patches were initial reviewed last when floated

[Intel-gfx] [PATCH 3/6] drm/i915: Upscale scaler max scale for NV12

issue here. v7: Rebased (me) Tested-by: Clinton Taylor Reviewed-by: Clinton Taylor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_display.c | 33 +++-- drivers/gpu/drm/i915/intel_drv.h

[Intel-gfx] [PATCH 1/6] drm/i915: Set scaler mode for NV12

Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_atomic.c | 8 +++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e2908ae..ac61135 100644 --- a

[Intel-gfx] [PATCH 5/6] drm/i915: Add NV12 as supported format for sprite plane

for SKL. v6: Addressed review comments by Ville Restricting the NV12 to BXT and PIPE A and B v7: Rebased (me) Tested-by: Clinton Taylor Reviewed-by: Clinton Taylor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm

[Intel-gfx] [PATCH] Revert "drm/i915/bxt: Disable device ready before shutdown command"

single link DSI panels, the change is not required. This will cause failure in sending SHUTDOWN packet during disable. Hence reverting the change. Will handle the change as part of dual link enabling in upstream. Signed-off-by: Uma Shankar Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH] drm/i915: Enable scanline read for gen9 dsi

nduru Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_irq.c | 5 + drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_dsi.c | 46 4 files changed, 56 insertions(+) diff --git a/dr

[Intel-gfx] [PATCH 05/15] drm/i915/skl+: NV12 related changes for WM

From: Mahesh Kumar NV12 requires WM calculation for UV plane as well. UV plane WM should also fulfill all the WM related restrictions. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 54 +++

[Intel-gfx] [PATCH 03/15] drm/i915/skl+: add NV12 in skl_format_to_fourcc

From: Mahesh Kumar Add support of recognizing DRM_FORMAT_NV12 from plane_format register value. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/intel_display.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.

[Intel-gfx] [PATCH 01/15] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

From: Mahesh Kumar skl_wm_values struct contains values of pipe/plane DDB only. so rename it for better readability of code. Similarly skl_copy_wm_for_pipe copies DDB values. s/skl_wm_values/skl_ddb_values s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe Changes since V1: - also change name of skl

[Intel-gfx] [PATCH 08/15] drm/i915/skl+: nv12 workaround disable WM level 1-7

able latency levels 1 through 7 (WM1 - WM7) on NV12 planes. v2: Addressed review comments by Maarten. Reviewed-by: Maarten Lankhorst Signed-off-by: Mahesh Kumar Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_pm.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/dri

[Intel-gfx] [PATCH 04/15] drm/i915/skl+: support verification of DDB HW state for NV12

From: Mahesh Kumar NV12 formats have two registers for DDB. Verify both the registers for NV12 during verify_wm_state. v2: Addressed review comments by Maarten. Signed-off-by: Mahesh Kumar Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_display.c | 2 +- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 07/15] drm/i915/skl+: make sure higher latency level has higher wm value

From: Mahesh Kumar DDB allocation optimization algorithm requires/assumes ddb allocation for any memory C-state level DDB value to be as high as level below. Render decompression requires level WM to be as high as wm level-0. This patch fulfils both the requirements. Signed-off-by: Mahesh Kumar

[Intel-gfx] [PATCH 00/15] Adding NV12 support

This patch series is adding NV12 support for Broxton display after rebasing on latest drm-tip. Initial series of the patches can be found here: https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html Previous revision history: The first version of patches were reviewed when floated b

[Intel-gfx] [PATCH 02/15] drm/i915/skl+: refactor WM calculation for NV12

rten Lankhorst Signed-off-by: Mahesh Kumar Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_drv.h | 4 +- drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 121 --- 3 files changed, 64 insertions(+), 62 deletions(-) diff --g

[Intel-gfx] [PATCH 06/15] drm/i915/skl+: pass skl_wm_level struct to wm compute func

From: Mahesh Kumar This will reduce number of arguments required to be passed in skl_compute_plane_wm function. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/intel_pm.c | 18 +++--- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.

[Intel-gfx] [PATCH 13/15] drm/i915: Add NV12 as supported format for primary plane

: Rebased (me) Tested-by: Clinton Taylor Reviewed-by: Clinton Taylor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_display.c | 26 -- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a

[Intel-gfx] [PATCH 15/15] drm/i915: Add NV12 support to intel_framebuffer_init

aylor Reviewed-by: Clinton Taylor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_display.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_disp

[Intel-gfx] [PATCH 12/15] drm/i915: Upscale scaler max scale for NV12

: Rebased (me) Tested-by: Clinton Taylor Reviewed-by: Clinton Taylor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/intel_display.c | 33 +++-- drivers/gpu/drm/i915/intel_drv.h | 3 ++- drivers

[Intel-gfx] [PATCH 10/15] drm/i915: Set scaler mode for NV12

Reviewed-by: Clinton Taylor Signed-off-by: Chandra Konduru Signed-off-by: Nabendu Maiti Signed-off-by: Vidya Srinivas --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_atomic.c | 8 +++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm

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