e 4GB (Chris, Daniel Vetter).
Cc: Chris Wilson
Cc: Akash Goel
Cc: Vinay Belgaumkar
Cc: Michal Winiarski
Cc: Zou Nanhai
Cc: Kristian Høgsberg
Cc: Tvrtko Ursulin
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/i915_dma.c| 3 ++
drivers/gpu/drm/i915/i915_drv.h
patch cleanup.
v6: Trivial rebase on latest drm-intel-nightly
Cc: Chris Wilson
Cc: Akash Goel
Cc: Vinay Belgaumkar
Cc: Michal Winiarski
Cc: Zou Nanhai
Cc: Kristian Høgsberg
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/i915_dma.c| 3 ++
drivers/gpu/drm/i915/i915_
A typo resulted in the watermarks for cursor planes not being calculated
correctly. Fixed the typo.
Cc: Ville Syrjälä
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers
Write HWS_PGA address even in execlists mode as the global hardware status
page is still required. This address was previously uninitialized and
HWSP writes would clobber whatever buffer happened to reside at GGTT
address 0.
Issue: VIZ-2020
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915
functions.
Downgraded pinning check BUG_ONs to WARN_ONs.
Issue: VIZ-4277
Signed-off-by: Oscar Mateo
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/intel_lrc.c| 110 ++-
drivers/gpu/drm/i915/intel_lrc.h|1 +
drivers/gpu/drm/i915/intel_ringbuffer.c
nterrupt time :(
v3: Use a mutex rather than atomic_t to protect pin count to avoid races.
Do not unpin default context in free_request.
v4: Break out pin and unpin into functions. Fix style problems reported
by checkpatch
Issue: VIZ-4277
Signed-off-by: Oscar Mateo
Signed-off-by: Thoma
.
Issue: VIZ-2020
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/intel_lrc.c | 34 ++
1 file changed, 26 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 87ce445..6b8bf0d 100644
--- a/drivers
-4274
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/i915_gem.c |4 +++
drivers/gpu/drm/i915/intel_lrc.c| 52 ++-
drivers/gpu/drm/i915/intel_lrc.h|2 +-
drivers/gpu/drm/i915/intel_ringbuffer.h |1 +
4 files changed, 36
execlist lock when checking queue state
Issue: VIZ-4274
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/i915_gem.c |9 ++
drivers/gpu/drm/i915/intel_lrc.c| 52 ++-
drivers/gpu/drm/i915/intel_lrc.h|2 +-
drivers/gpu/drm/i915
execlist lock when checking queue state
v5: Fix leaking requests by freeing in execlists_retire_requests.
Issue: VIZ-4274
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/i915_gem.c |9 ++
drivers/gpu/drm/i915/intel_lrc.c| 53 ++-
drivers
functions.
Downgraded pinning check BUG_ONs to WARN_ONs.
v5: Reinstated WARN_ONs for unexpected execlist states. Removed unused
variable.
Issue: VIZ-4277
Signed-off-by: Oscar Mateo
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/intel_lrc.c| 102
ct
mutex already locked. Add WARN_ONs to make sure this is the case in future.
Issue: VIZ-4277
Signed-off-by: Oscar Mateo
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +-
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/i915_gem.c
LRC object does not need to be mapped into the GGTT when dumping. Just use
pin_pages. A side-effect of this patch is that a compiler warning goes away
(not checking return value of i915_gem_obj_ggtt_pin).
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/i915_debugfs.c | 19
Dynamic context pinning for LRCs introduced a leak in legacy mode.
Reinstate context unreference in i915_gem_free_request for legacy contexts.
Leak reported by i-g-t/drv_module_reload fixed by this patch.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86507
Signed-off-by: Thomas Daniel
ed_create
for other contexts.
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/i915_gem_context.c | 25 ++---
drivers/gpu/drm/i915/intel_lrc.c| 30 +++---
2 files changed, 37 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915
s are gathered from the backing storage and pinned into our object").
Improved error checking - get_pages and get_page are checked for failure.
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/i915_debugfs.c | 84 ---
1 file changed, 49 insertions(+), 35
-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/i915_params.c |2 +-
drivers/gpu/drm/i915/intel_lrc.c |3 +--
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index c91cb20..ad685d8 100644
--- a
MODULE_PARM_DESC too.
Issue: VIZ-2020
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/i915_params.c |4 ++--
drivers/gpu/drm/i915/intel_lrc.c |3 +--
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
From: Oscar Mateo
For the most part, logical ring context objects are similar to hardware
contexts in that the backing object is meant to be opaque. There are
some exceptions where we need to poke certain offsets of the object for
initialization, updating the tail pointer or updating the PDPs.
F
From: Oscar Mateo
Any given ringbuffer is unequivocally tied to one context and one engine.
By setting the appropriate pointers to them, the ringbuffer struct holds
all the infromation you might need to submit a workload for processing,
Execlists style.
Signed-off-by: Oscar Mateo
---
drivers/g
From: Oscar Mateo
As we have said a couple of times by now, logical ring contexts have
their own ringbuffers: not only the backing pages, but the whole
management struct.
In a previous version of the series, this was achieved with two separate
patches:
drm/i915/bdw: Allocate ringbuffer backing o
From: Thomas Daniel
For a description of this patchset, please check the previous cover letters:
[1], [2], [3] and [4].
I have taken ownership of this patchset from Oscar, and this version represents
his last work on the execlists patchset. The narrative below is from him.
I have been given
From: Oscar Mateo
For the moment this is just a placeholder, but it shows one of the
main differences between the good ol' HW contexts and the shiny
new Logical Ring Contexts: LR contexts allocate and free their
own backing objects. Another difference is that the allocation is
deferred (as the c
From: Oscar Mateo
GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
These expanded contexts enable a number of new abilities, especially
"Execlists".
The macro is defined to off until we have things in place to hope to
work.
v2: Rename "advanced contexts" to the more correct
From: Oscar Mateo
In this patch:
commit 78382593e921c88371abd019aca8978db3248a8f
Author: Oscar Mateo
Date: Thu Jul 3 16:28:05 2014 +0100
drm/i915: Extract the actual workload submission mechanism from execbuffer
So that we isolate the legacy ringbuffer submission mechanism, which be
From: Oscar Mateo
The backing objects and ringbuffers for contexts created via open
fd are actually empty until the user starts sending execbuffers to
them. At that point, we allocate & populate them. We do this because,
at create time, we really don't know which engine is going to be used
with t
From: Oscar Mateo
A context backing object only makes sense for a given engine (because
it holds state data specific to that engine).
In legacy ringbuffer sumission mode, the only MI_SET_CONTEXT we really
perform is for the render engine, so one backing object is all we nee.
With Execlists, how
From: Oscar Mateo
These two functions make no sense in an Logical Ring Context & Execlists
world.
v2: We got rid of lrc_enabled and centralized everything in the sanitized
i915.enbale_execlists instead.
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_gem_context.c |9 +
1
From: Oscar Mateo
Allocate and populate the default LRC for every ring, call
gen-specific init/cleanup, init/fini the command parser and
set the status page (now inside the LRC object). These are
things all engines/rings have in common.
Stopping the ring before cleanup and initializing the seqno
From: Oscar Mateo
On a previous iteration of this patch, I created an Execlists
version of __i915_add_request and asbtracted it away as a
vfunc. Daniel Vetter wondered then why that was needed:
"with the clean split in command submission I expect every
function to know wether it'll submit to an
From: Oscar Mateo
This is mostly for correctness so that we know we are running the LR
context correctly (this is, the PDPs are contained inside the context
object).
v2: Move the check to inside the enable PPGTT function. The switch
happens in two places: the legacy context switch (that we won't
From: Oscar Mateo
Execlists are indeed a brave new world with respect to workload
submission to the GPU.
In previous version of these series, I have tried to impact the
legacy ringbuffer submission path as little as possible (mostly,
passing the context around and using the correct ringbuffer wh
From: Oscar Mateo
Each logical ring context has the tail pointer in the context object,
so update it before submission.
v2: New namespace.
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_lrc.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm
From: Oscar Mateo
This is what i915_gem_do_execbuffer calls when it wants to execute some
worload in an Execlists world.
v2: Check arguments before doing stuff in intel_execlists_submission. Also,
get rel_constants parsing right.
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_drv.h
From: Oscar Mateo
This is a hard one, since there is no direct hardware ring to
control when in Execlists.
We reuse intel_ring_idle here, but it should be fine as long
as i915_add_request does the ring thing.
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_lrc.c | 24 +
Force Wakeup bit to prevent GT from entering C6 while
ELSP writes are in progress") as noted by Thomas Daniel
(thomas.dan...@intel.com).
- Rename functions and use an execlists/intel_execlists_ namespace.
- The BUG_ON only checked that the LRCA was <32 bits, but it didn't make
From: Oscar Mateo
The normal flip function places things in the ring in the legacy
way, so we either fix that or force MMIO flips always as we do in
this patch.
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_display.c |2 ++
drivers/gpu/drm/i915/intel_lrc.c |3 ++-
2 fil
From: Oscar Mateo
The time has come, the Walrus said, to talk of many things.
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_drv.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b7cf0ec..1
waiting
on a sequence number. Therefore, this commit adds a bitmask of interrupts to
be kept unmasked at all times.
v2: Disable HWSTAM, as suggested by Damien (nobody listens to these interrupts,
anyway).
v3: Add new get/put_irq functions.
Signed-off-by: Thomas Daniel (v1)
Signed-off-by: Oscar Mateo
From: Oscar Mateo
No mistery here: the seqno is still retrieved from the engine's
HW status page (the one in the default context. For the moment,
I see no reason to worry about other context's HWS page).
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_lrc.c | 20 +++
From: Ben Widawsky
This has turned out to be really handy in debug so far.
Update:
Since writing this patch, I've gotten similar code upstream for error
state. I've used it quite a bit in debugfs however, and I'd like to keep
it here at least until preemption is working.
Signed-off-by: Ben Wida
From: Oscar Mateo
Since the ringbuffer does not belong per engine anymore, we have to
make sure that we are always recording the correct ringbuffer.
TODO: This is only a small fix to keep basic error capture working, but
we need to add more information for it to be useful (e.g. dump the
context
(still TODO).
v2: Use a spinlock, do not remove the requests on unqueue (wait for
context switch completion).
Signed-off-by: Thomas Daniel
v3: Several rebases and code changes. Use unique ID.
v4:
- Move the queue/lock init to the late ring initialization.
- Damien's kmalloc review com
handle the forcewake get/put directly.
Signed-off-by: Thomas Daniel
v2: Unreferencing the context when we are freeing the request might free
the backing bo, which requires the struct_mutex to be grabbed, so defer
unreferencing and freeing to a bottom half.
v3:
- Ack the interrupt inmediately
From: Oscar Mateo
Very similar to the legacy add_request, only modified to account for
logical ringbuffer.
v2: Use MI_GLOBAL_GTT, as suggested by Brad Volkin.
v3: Unify render and non-render in the same function, as noticed by
Brad Volkin.
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/
From: Oscar Mateo
If we reset a ring after a hang, we have to make sure that we clear
out all queued Execlists requests.
v2: The ring is, at this point, already being correctly re-programmed
for Execlists, and the hangcheck counters cleared.
v3: Daniel suggests to drop the "if (execlists)" beca
From: Oscar Mateo
v2: Warn and return if LRCs are not enabled.
v3: Grab the Execlists spinlock (noticed by Daniel Vetter).
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_debugfs.c | 73 +++
drivers/gpu/drm/i915/intel_lrc.c|6 ---
drivers/gpu
From: Oscar Mateo
Dispatch_execbuffer's evil twin.
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_lrc.c| 28
drivers/gpu/drm/i915/intel_ringbuffer.h |2 ++
2 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/d
NY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *Ben Widawsky
+ *Michel Thierry
+ *Thomas Daniel
+ *Oscar
From: Oscar Mateo
Now that we have the ability to allocate our own context backing objects
and we have multiplexed one of them per engine inside the context structs,
we can finally allocate and free them correctly.
Regarding the context size, reading the register to calculate the sizes
can work,
From: Oscar Mateo
Up until recently, semaphores weren't enabled in BDW so we didn't care
about them. But then Rodrigo came and enabled them:
commit 521e62e49a42661a4ee0102644517dbe2f100a23
Author: Rodrigo Vivi
drm/i915: Enable semaphores on BDW
So now we have to explicitly disable
From: Oscar Mateo
In the current Execlists feeding mechanism, full preemption is not
supported yet: only lite-restores are allowed (this is: the GPU
simply samples a new tail pointer for the context currently in
execution).
But we have identified an scenario in which a full preemption occurs:
1)
From: Oscar Mateo
Well, new-ish: if all this code looks familiar, that's because it's
a clone of the existing submission mechanism (with some modifications
here and there to adapt it to LRCs and Execlists).
And why did we do this instead of reusing code, one might wonder?
Well, there are some fe
From: Oscar Mateo
Up until now, we have pinned every logical ring context backing object
during creation, and left it pinned until destruction. This made my life
easier, but it's a harmful thing to do, because we cause fragmentation
of the GGTT (and, eventually, we would run out of space).
This
From: Oscar Mateo
The batchbuffer that sets the render context state is submitted
in a different way, and from different places.
We needed to make both the render state preparation and free functions
outside accesible, and namespace accordingly. This mess is so that all
LR, LRC and Execlists fun
From: Oscar Mateo
Same as the legacy-style ring->flush.
v2: The BSD invalidate bit still exists in GEN8! Add it for the VCS
rings (but still consolidate the blt and bsd ring flushes into one).
This was noticed by Brad Volkin.
v3: The command for BSD and for other rings is slightly different:
ge
From: Oscar Mateo
Same as with the context, pinning to GGTT regardless is harmful (it
badly fragments the GGTT and can even exhaust it).
Unfortunately, this case is also more complex than the previous one
because we need to map and access the ringbuffer in several places
along the execbuffer pat
From: Oscar Mateo
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_debugfs.c | 25 +++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 903ed67..0980cdd 100644
--- a/dr
From: Oscar Mateo
Add theory of operation notes to intel_lrc.c and comments to externally
visible functions.
v2: Add notes on logical ring context creation.
v3: Use kerneldoc.
v4: Integrate it in the DocBook template.
Signed-off-by: Thomas Daniel (v1)
Signed-off-by: Oscar Mateo (v2, v3
From: Oscar Mateo
If we receive a storm of requests for the same context (see gem_storedw_loop_*)
we might end up iterating over too many elements in interrupt time, looking for
contexts to squash together. Instead, share the burden by giving more
intelligence to the queue function. At most, the
From: Oscar Mateo
Logical rings do not need most of the initialization their
legacy ringbuffer counterparts do: we just need the pipe
control object for the render ring, enable Execlists on the
hardware and a few workarounds.
v2: Squash with: "drm/i915: Extract pipe control fini & make
init outs
From: Oscar Mateo
As suggested by Daniel Vetter. The idea, in subsequent patches, is to
provide an alternative to these vfuncs for the Execlists submission
mechanism.
v2: Splitted into two and reordered to illustrate our intentions, instead
of showing it off. Also, remove the add_request vfunc a
required when using LRCs as the
PPGTT is enabled in the context descriptor and the PDPs are written
in the LRC.
Signed-off-by: Oscar Mateo
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/i915_gem_gtt.c |5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_
From: Oscar Mateo
v2: Warn and return if LRCs are not enabled.
v3: Grab the Execlists spinlock (noticed by Daniel Vetter).
Signed-off-by: Oscar Mateo
v4: Lock the struct mutex for atomic state capture
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/i915_debugfs.c | 80
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/i915_debugfs.c | 52 +++
1 file changed, 52 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index aca5ff1..a3c958c 100644
--- a/drivers/gpu/drm/i915/i915_
ff-by: Thomas Daniel
---
drivers/gpu/drm/i915/i915_drv.h|4 +++
drivers/gpu/drm/i915/i915_gem.c| 51
drivers/gpu/drm/i915/i915_gem_evict.c | 38 +
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 16 +++--
in
-by: Thomas Daniel
---
drivers/gpu/drm/i915/i915_gem_context.c |1 +
drivers/gpu/drm/i915/intel_lrc.c|1 -
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index bf9778e..cc100c9 100644
--
aulo Zanoni
Cc: Daniel Vetter
Cc: Dave Gordon
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/intel_lrc.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 7670a0f..e405b61 100644
--- a/drivers/g
https://bugs.freedesktop.org/show_bug.cgi?id=87627
Signed-off-by: Thomas Daniel
---
tests/prime_self_import.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/tests/prime_self_import.c b/tests/prime_self_import.c
index 1eb5a04..ded92cf 100644
--- a/tests/prime_self_imp
text_reset() to reset head and tail on a LRC and
its ringbuffer.
Call intel_lr_context_reset() for each context in i915_gem_context_reset() when
in execlists mode.
Testcase: igt/pm_rps --run-subtest reset #bdw
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88096
Signed-off-by: Thomas Danie
As of Gen6, the general purpose area of the hardware status page has shrunk and
now begins at dword 0x30. i915 driver uses dword 0x20 to store the seqno which
is now reserved. So shift our HWSP dwords up into the general purpose range
before this bites us.
Signed-off-by: Thomas Daniel
patch cleanup.
Cc: Chris Wilson
Cc: Akash Goel
Cc: Vinay Belgaumkar
Cc: Michal Winiarski
Cc: Zou Nanhai
Cc: Kristian Høgsberg
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/i915_dma.c|3 ++
drivers/gpu/drm/i915/i915_drv.h|4 +++
drivers/gpu/drm
required when using LRCs as the
PPGTT is enabled in the context descriptor and the PDPs are written
in the LRC.
v4: Clarify comment based on review feedback.
Signed-off-by: Oscar Mateo
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/i915_gem_gtt.c |6 ++
1 file changed, 6 insertions(
A previous commit broke aliasing PPGTT for lrc, resulting in a kernel oops
on boot. Add a check so that is full PPGTT is not in use the context is
populated with the aliasing PPGTT.
Issue: VIZ-4278
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/intel_lrc.c |7 +++
1 file changed
A previous commit broke aliasing PPGTT for lrc, resulting in a kernel oops
on boot. Add a check so that is full PPGTT is not in use the context is
populated with the aliasing PPGTT.
Issue: VIZ-4278
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/intel_lrc.c |5 +
1 file changed, 5
longer be called in execlists mode.
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 22ad38b..00267b3 100644
--- a
ed a comment that it should not be called in execlist mode. Added
WARN_ON if i915_switch_context is called in execlist mode. Moved check
for execlist mode out of i915_switch_context and into callers. Added
comment in context_reset explaining why nothing is done in execlist
mode.
Signed-off-by: Thomas Da
tch. Rebased.
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/i915_drv.h |4 +-
drivers/gpu/drm/i915/i915_gem_render_state.c | 40 --
drivers/gpu/drm/i915/i915_gem_render_state.h | 47 +
drivers/gpu/drm/i915/intel_lrc.c |
No longer create a work item to clean each execlist queue item.
Instead, move retired execlist requests to a queue and clean up the
items during retire_requests.
Issue: VIZ-4274
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915/i915_gem.c |1 +
drivers/gpu/drm/i915/intel_lrc.c
No longer create a work item to clean each execlist queue item.
Instead, move retired execlist requests to a queue and clean up the
items during retire_requests.
v2: Fix legacy ring path broken during overzealous cleanup
Issue: VIZ-4274
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915
Write HWS_PGA address even in execlists mode as the global hardware status
page is still required. This address was previously uninitialized and
HWSP writes would clobber whatever buffer happened to reside at GGTT
address 0.
Issue: VIZ-2020
Signed-off-by: Thomas Daniel
---
drivers/gpu/drm/i915
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