Chris Wilson
Cc: Rodrigo Vivi
Cc: Daniele Ceraolo Spurio
Cc: John Spotswood
Cc: Vinay Belgaumkar
Cc: Tony Ye
Cc: Anusha Srivatsa
Cc: Jeff Mcgee
Cc: Antonio Argenziano
Cc: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/intel_uc.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
On 2/15/19 5:28 PM, Daniele Ceraolo Spurio wrote:
On 2/14/19 1:45 PM, Sujaritha Sundaresan wrote:
This aim of this patch is to call guc_disable_communication in all
suspend paths. The reason to introduce this is to resolve a bug that
occured due to suspend late not being called in the
On 2/14/19 2:46 PM, Daniele Ceraolo Spurio wrote:
On 2/14/19 1:45 PM, Sujaritha Sundaresan wrote:
The aim of this patch is to allow enabling and disabling
of CTB without requiring the mutex lock.
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha Sundaresan
On 3/5/19 2:06 PM, Daniele Ceraolo Spurio wrote:
On 3/5/19 2:05 PM, Daniele Ceraolo Spurio wrote:
On 3/4/19 4:55 PM, Sujaritha Sundaresan wrote:
Replacing the -E2BIG error code return for WOPCM
initialization with -ENODEV. This will prevent the pci from
picking this up as a warning during
this issue will be flagging up in
the public CI as well.
-Sujaritha
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er the flush_workqueues.
-Chris
But shouldn't this be taken care of by the switch_to_kernel_context_sync ?
And would be better have uc_suspend after drain_delayed_work instead of
just after flush_workqueue ?
-Sujaritha
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On 3/21/19 10:54 AM, Chris Wilson wrote:
Quoting Daniele Ceraolo Spurio (2019-03-21 17:49:55)
On 3/21/19 10:14 AM, Sujaritha Sundaresan wrote:
Adding a call to intel_uc_suspend in i915_gem_suspend, which
is a common point for the suspend/resume and hibernate paths.
This fixes an unbalanced
On 3/21/19 1:08 PM, Chris Wilson wrote:
Quoting Sujaritha (2019-03-21 19:41:17)
On 3/21/19 12:37 PM, Chris Wilson wrote:
Quoting Patchwork (2019-03-21 19:26:27)
== Series Details ==
Series: drm/i915/guc: GuC suspend path cleanup
URL : https://patchwork.freedesktop.org/series/58370/
State
On 3/21/19 1:23 PM, Chris Wilson wrote:
Quoting Sujaritha (2019-03-21 20:02:36)
On 3/21/19 1:08 PM, Chris Wilson wrote:
Quoting Sujaritha (2019-03-21 19:41:17)
On 3/21/19 12:37 PM, Chris Wilson wrote:
Quoting Patchwork (2019-03-21 19:26:27)
== Series Details ==
Series: drm/i915/guc: GuC
Wilson
Cc: Joonas Lahtinen
Cc: Sagar Arun Kamble
Cc: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_debugfs.c | 47 ++---
1 file changed, 23 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915
On 11/28/2017 07:42 AM, Michal Wajdeczko wrote:
Instead of trying different seq_puts messages, lets use common
-ENODEV error code to indicate missing/unsupported feature.
I agree that this is the simplest way to unify the message.
Regards,
Sujaritha
Suggested-by: Chris Wilson
Signed-off
Sure, I will rename the commit message. Thanks.
On 09/19/2017 10:11 AM, Daniele Ceraolo Spurio wrote:
Since we're not decoupling just logs, maybe the commit could be
renamed to "Decouple ADS and logs from submission"
On 19/09/17 09:15, Sujaritha Sundaresan wrote:
The Additio
On 09/28/2017 03:36 PM, Srivatsa, Anusha wrote:
-Original Message-
From: Sundaresan, Sujaritha
Sent: Thursday, September 21, 2017 11:38 AM
To: intel-gfx@lists.freedesktop.org
Cc: Sundaresan, Sujaritha ; Wajdeczko, Michal
; Srivatsa, Anusha ;
Mateo Lozano, Oscar ; Ceraolo Spurio
On 09/29/2017 12:10 AM, Michal Wajdeczko wrote:
On Fri, 29 Sep 2017 00:36:56 +0200, Srivatsa, Anusha
wrote:
-Original Message-
From: Sundaresan, Sujaritha
Sent: Thursday, September 21, 2017 11:38 AM
To: intel-gfx@lists.freedesktop.org
Cc: Sundaresan, Sujaritha ;
Wajdeczko
On 10/03/2017 11:13 PM, Sagar Arun Kamble wrote:
On 10/4/2017 4:25 AM, Sujaritha Sundaresan wrote:
Unifying the various seq_puts messages to the simplest one
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messages, Re-factoring code as per review (Michal)
v4: Rebase
v5
On 10/04/2017 12:06 AM, Sagar Arun Kamble wrote:
Hi Sujaritha,
I am Unable to locate single series on patchwork for these changes.
Please send all patches together in single series with cover letter.
It will also enable CI BAT/IGT testing for the series.
Thanks
Sagar
Sorry, I was not aware
On 10/04/2017 04:39 AM, Michal Wajdeczko wrote:
On Wed, 04 Oct 2017 08:13:12 +0200, Sagar Arun Kamble
wrote:
On 10/4/2017 4:25 AM, Sujaritha Sundaresan wrote:
Unifying the various seq_puts messages to the simplest one
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts
On 10/03/2017 11:45 PM, Sagar Arun Kamble wrote:
Subject is missing "parameter" in the end. Either keep module
parameter or i915_modparams.
Will fix the subject line.
On 10/4/2017 4:26 AM, Sujaritha Sundaresan wrote:
We currently have two module parameters that c
On 10/29/2017 09:49 PM, Sagar Arun Kamble wrote:
On 10/26/2017 11:24 PM, Daniele Ceraolo Spurio wrote:
On 25/10/17 06:31, Michal Wajdeczko wrote:
On Tue, 24 Oct 2017 19:21:20 +0200, Sujaritha Sundaresan
wrote:
Unifying the various seq_puts messages in debugfs to the simplest
one for
On 10/25/2017 06:31 AM, Michal Wajdeczko wrote:
On Tue, 24 Oct 2017 19:21:20 +0200, Sujaritha Sundaresan
wrote:
Unifying the various seq_puts messages in debugfs to the simplest one
for
feature support.
v2: Clarifying the commit message (Anusha)
v3: Re-factoring code as per review
On 10/26/2017 10:54 AM, Daniele Ceraolo Spurio wrote:
On 25/10/17 06:31, Michal Wajdeczko wrote:
On Tue, 24 Oct 2017 19:21:20 +0200, Sujaritha Sundaresan
wrote:
Unifying the various seq_puts messages in debugfs to the simplest
one for
feature support.
v2: Clarifying the commit message
On 11/02/2017 02:23 AM, Sagar Arun Kamble wrote:
On 10/25/2017 9:49 PM, Michal Wajdeczko wrote:
On Tue, 24 Oct 2017 19:21:25 +0200, Sujaritha Sundaresan
wrote:
The Additional Data Struct (ADS) contains objects that are required by
guc post FW load and are not necessarily submission-only
On 10/25/2017 08:26 AM, Michal Wajdeczko wrote:
On Tue, 24 Oct 2017 19:21:21 +0200, Sujaritha Sundaresan
wrote:
We currently have two module parameters that control GuC:
"enable_guc_loading" and "enable_guc_submission". Whenever
we need submission=1, we also need lo
On 10/25/2017 08:56 AM, Michal Wajdeczko wrote:
On Tue, 24 Oct 2017 19:21:23 +0200, Sujaritha Sundaresan
wrote:
Updating GuC and HuC firmware select function to support removing
i915_modparams.enable_guc_loading module parameter.
Hmm, is it correct order of patches ? this modparam was
On 11/12/2017 09:22 AM, Michal Wajdeczko wrote:
On Sat, 11 Nov 2017 01:06:38 +0100, Sujaritha Sundaresan
wrote:
Placing the call to intel_guc_init after i915_gem_contexts_init,
based on the dependency within i915_gem_init.
Will move the function if required, depending on the review
On 11/12/2017 08:18 AM, Michal Wajdeczko wrote:
On Sat, 11 Nov 2017 01:06:31 +0100, Sujaritha Sundaresan
wrote:
Unifying the various seq_puts messages in debugfs to the simplest one
for
feature support.
v2: Clarifying the commit message (Anusha)
v3: Re-factoring code as per review
Forwarded Message
Subject: Re: [PATCH v9 2/8] drm/i915/guc : Removing
i915_modparams.enable_guc_loading module parameter
Date: Wed, 22 Nov 2017 10:07:23 -0800
From: Sujaritha
To: Michal Wajdeczko , Sagar Arun Kamble
On 11/12/2017 08:21 AM, Michal Wajdeczko
On 11/12/2017 08:25 AM, Michal Wajdeczko wrote:
On Sat, 11 Nov 2017 01:06:33 +0100, Sujaritha Sundaresan
wrote:
Updating GuC and HuC firmware select function to support removing
i915_modparams.enable_guc_loading module parameter.
v2: Clarifying the commit message (Anusha)
v3: Unify
On 11/12/2017 08:29 AM, Michal Wajdeczko wrote:
On Sat, 11 Nov 2017 01:06:34 +0100, Sujaritha Sundaresan
wrote:
Replacing conditions to remove dependance on enable_guc_submission
typo ;)
Oops. :)
v9: Including guc_log_level in the condition (Sagar)
Signed-off-by: Sujaritha
On 11/12/2017 08:52 AM, Michal Wajdeczko wrote:
On Sat, 11 Nov 2017 01:06:36 +0100, Sujaritha Sundaresan
wrote:
Replacing enable_guc_submission with enable_guc modparam.
In effect enable_guc is replacing enable_guc_loading and
enable_guc_submission.
Maybe it will be better if we replace
On 10/04/2017 06:58 AM, Michal Wajdeczko wrote:
On Wed, 04 Oct 2017 00:57:00 +0200, Sujaritha Sundaresan
wrote:
The previous patch has split up the initialization of some of the GuC
objects in 2 different functions, let's pull them back together.
v3: Group initialization of GuC ob
On 10/04/2017 06:50 AM, Michal Wajdeczko wrote:
On Wed, 04 Oct 2017 00:56:38 +0200, Sujaritha Sundaresan
wrote:
The Additional Data Struct (ADS) contains objects that are required by
guc post FW load and are not necessarily submission-only (although
that's
our current only use-case
7 12:02 AM, Sujaritha Sundaresan wrote:
Unifying the various seq_puts messages in debugfs to the simplest one
for
feature support.
v2: Clarifying the commit message (Anusha)
v3: Re-factoring code as per review (Michal)
v4: Rebase
v5: Split from following patch
v6: Re-factoring code (Mic
On 10/13/2017 02:42 AM, Sagar Arun Kamble wrote:
On 10/11/2017 12:02 AM, Sujaritha Sundaresan wrote:
We currently have two module parameters that control GuC:
"enable_guc_loading" and "enable_guc_submission".
Whenever we need i915_modparams.enable_guc_submis
#x27;t fit into the unified "early return" pattern.
Sujaritha
On 10/11/2017 12:02 AM, Sujaritha Sundaresan wrote:
Unifying the various seq_puts messages in debugfs to the simplest one
for
feature support.
v2: Clarifying the commit message (Anusha)
v3: Re-factoring code as per review
On 10/18/2017 03:58 AM, Joonas Lahtinen wrote:
On Tue, 2017-10-17 at 15:50 -0700, Sujaritha Sundaresan wrote:
We currently have two module parameters that control GuC:
"enable_guc_loading" and "enable_guc_submission". Whenever
we need i915_modparams.enable_guc_submis
On 10/18/2017 09:50 AM, Joonas Lahtinen wrote:
On Wed, 2017-10-18 at 09:25 -0700, Sujaritha wrote:
On 10/18/2017 03:58 AM, Joonas Lahtinen wrote:
On Tue, 2017-10-17 at 15:50 -0700, Sujaritha Sundaresan wrote:
We currently have two module parameters that control GuC:
"enable_guc_loading
On 10/17/2017 03:57 PM, Chris Wilson wrote:
Quoting Sujaritha Sundaresan (2017-10-17 23:50:47)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dd141b2..5b9bdd0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3201,9
On 10/18/2017 04:53 AM, Michal Wajdeczko wrote:
On Wed, 18 Oct 2017 00:50:47 +0200, Sujaritha Sundaresan
wrote:
We currently have two module parameters that control GuC:
"enable_guc_loading" and "enable_guc_submission". Whenever
we need i915_modparams.enable_guc_submis
On 10/18/2017 03:29 AM, Sagar Arun Kamble wrote:
On 10/18/2017 4:20 AM, Sujaritha Sundaresan wrote:
Updating GuC and HuC firmware select function to support removing
i915_modparams.enable_guc_loading module parameter.
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messages
On 10/18/2017 02:17 PM, Michal Wajdeczko wrote:
On Wed, 18 Oct 2017 12:29:13 +0200, Sagar Arun Kamble
wrote:
On 10/18/2017 4:20 AM, Sujaritha Sundaresan wrote:
Updating GuC and HuC firmware select function to support removing
i915_modparams.enable_guc_loading module parameter.
v2
On 10/18/2017 04:53 AM, Michal Wajdeczko wrote:
On Wed, 18 Oct 2017 00:50:47 +0200, Sujaritha Sundaresan
wrote:
We currently have two module parameters that control GuC:
"enable_guc_loading" and "enable_guc_submission". Whenever
we need i915_modparams.enable_guc_submis
On 5/27/2021 5:44 PM, Dale B Stimson wrote:
As part of the System Managemenent Interface (SMI), use the HWMON
subsystem to display power utilization.
The following standard HWMON power sensors are currently supported
(and appropriately scaled):
/sys/class/drm/card0/device/hwmon/hwmon
On 6/1/2021 5:42 PM, Dale B Stimson wrote:
On 2021-06-01 14:39:11, Sundaresan, Sujaritha wrote:
Date: Tue, 1 Jun 2021 14:39:11 -0700
From: "Sundaresan, Sujaritha"
To: Dale B Stimson ,
intel-gfx@lists.freedesktop.org, dri-de...@lists.freedesktop.org
CC: Jon Ewins , Jani Nikula
S
- throttle_reason_ratl
- throttle_reason_vr_thermalert
- throttle_reason_vr_tdc
Signed-off-by: Sujaritha Sundaresan
Cc: Dale B Stimson
---
drivers/gpu/drm/i915/gt/intel_rps.c | 83 +
drivers/gpu/drm/i915/gt/intel_rps.h | 10 +++
drivers/gpu/drm/i915/i915_reg.h | 11
On 10/8/2021 4:03 PM, Andi Shyti wrote:
Hi Sujaritha,
On Fri, Oct 08, 2021 at 01:44:54PM -0700, Sujaritha Sundaresan wrote:
This patch adds the following new sysfs frequency attributes;
- punit_req_freq_mhz
- throttle_reason_status
- throttle_reason_pl1
├── gt_max_freq_mhz+─-> kept as existing ABI;
├── gt_min_freq_mhz|it points to gt0/
├── gt_RP0_freq_mhz|
└── gt_RP1_freq_mhz|
└── gt_RPn_freq_mhz -+
Signed-off-by: Andi Shyti
Signed-off-by: Lucas De Marchi
Cc: Matt Roper
Cc:
ters.
+ * Used herein as a 64-bit bit register.
+ * These masks are defined using GENMASK_ULL as REG_GENMASK is limited to u32
+ * and as GENMASK is "long" and therefore 32-bits on a 32-bit system.
+ * PKG_PKG_TDP, PKG_MIN_PWR, and PKG_MAX_PWR are scaled in the same way as
+ * PKG_PWR_LIM_*, above.
+ * PKG_MAX_WIN has sub-fields for x and y, and has the value: is 1.x * 2^y.
+ */
+#define PKG_PKG_TDP GENMASK_ULL(14, 0)
+#define PKG_MIN_PWR GENMASK_ULL(30, 16)
+#define PKG_MAX_PWR GENMASK_ULL(46, 32)
+#define PKG_MAX_WIN GENMASK_ULL(54, 48)
+#define PKG_MAX_WIN_Y GENMASK_ULL(54, 53)
+#define PKG_MAX_WIN_X GENMASK_ULL(52, 48)
+
/*
* Logical Context regs
*/
Looks good to me. If the CI failures are not related to the patch
changes then;
Reviewed-by: Sujaritha Sundaresan
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lockless reset.
Sujaritha Sundaresan (2):
drm/i915/guc: Splitting CT channel open/close functions
drm/i915/guc: Calling guc_disable_communication in all suspend paths
drivers/gpu/drm/i915/i915_reset.c | 2 +-
drivers/gpu/drm/i915/intel_guc.c| 12
drivers/gpu/drm/i915/intel_guc_ct.c
The aim of this patch is to allow enabling and disabling
of CTB without requiring the mutex lock.
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/intel_guc.c| 12
drivers/gpu/drm/i915/intel_guc_ct.c | 85
This aim of this patch is to call guc_disable_communication in all
suspend paths. The reason to introduce this is to resolve a bug that
occured due to suspend late not being called in the hibernate devices
path.
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha Sundaresan
This aim of this patch is to call guc_disable_communication in all
suspend paths. The reason to introduce this is to resolve a bug that
occurred due to suspend late not being called in the hibernate devices
path.
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha
lockless reset.
Sujaritha Sundaresan (2):
drm/i915/guc: Splitting CT channel open/close functions
drm/i915/guc: Calling guc_disable_communication in all suspend paths
drivers/gpu/drm/i915/i915_reset.c | 2 +-
drivers/gpu/drm/i915/intel_guc.c| 12
drivers/gpu/drm/i915/intel_guc_ct.c
The aim of this patch is to allow enabling and disabling
of CTB without requiring the mutex lock.
v2: Phasing out ctch_is_enabled function and replacing it with
ctch->enabled (Daniele)
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha Sundaresan
---
drivers/
lockless reset.
Sujaritha Sundaresan (2):
drm/i915/guc: Splitting CT channel open/close functions
drm/i915/guc: Calling guc_disable_communication in all suspend paths
drivers/gpu/drm/i915/i915_reset.c | 2 +-
drivers/gpu/drm/i915/intel_guc.c| 12
drivers/gpu/drm/i915/intel_guc_ct.c
This aim of this patch is to call guc_disable_communication in all
suspend paths. The reason to introduce this is to resolve a bug that
occurred due to suspend late not being called in the hibernate devices
path.
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha
The aim of this patch is to allow enabling and disabling
of CTB without requiring the mutex lock.
v2: Phasing out ctch_is_enabled function and replacing it with
ctch->enabled (Daniele)
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/
Replacing the -E2BIG error code return for WOPCM
initialization with -ENODEV. This will prevent the pci from
picking this up as a warning during fault injection testing.
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/intel_wopcm.c
Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index c42c5ccf38fe..f962b5c0b3c1 100644
--- a/drivers
-Original Message-
From: Chris Wilson
Sent: Wednesday, March 6, 2019 1:08 AM
To: Wajdeczko, Michal ; Sundaresan, Sujaritha
; intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/guc: Fixing error code for WOPCM
initialization
Quoting Michal Wajdeczko (2019-03
Adding the call to prepare for guc reset along with engine
reset. intel_uc_reset_prepare() calls to disable guc communication
and to sanitize.
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_reset.c | 2 ++
1 file changed, 2
: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_gem.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1a684b7e8c09..980855ebdeda 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4371,6
(Chris)
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_gem.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1a684b7e8c09
rivate;
struct i915_ggtt;
+struct intel_gt;
-void mock_init_ggtt(struct drm_i915_private *i915, struct i915_ggtt *ggtt);
+void mock_init_ggtt(struct intel_gt *gt);
void mock_fini_ggtt(struct i915_ggtt *ggtt);
struct i915_ppgtt *mock_ppgtt(struct drm_i915_private *i915, const char *name);
Seems like a straightforward change.
Reviewed-by : Sujaritha Sundaresan
i915_gem_drain_freed_objects(i915);
- mock_fini_ggtt(&i915->ggtt);
+ mock_fini_ggtt(to_gt(i915)->ggtt);
destroy_workqueue(i915->wq);
intel_region_ttm_device_fini(i915);
Reviewed-by : Sujaritha Sundaresan
const char *msg)
{
- struct i915_ggtt *ggtt = >->i915->ggtt;
+ struct i915_ggtt *ggtt = gt->ggtt;
const struct resource *dsm = >->i915->dsm;
resource_size_t num_pages, page;
struct intel_engine_cs *engine;
Reviewed-by : Sujaritha Sundaresan
, NULL);
if (IS_ERR(vma))
goto err_obj;
Reviewed-by : Sujaritha Sundaresan
;base.dev)->ggtt))
+ !i915_ggtt_has_aperture(to_gt(i915)->ggtt))
return false;
i915_gem_object_lock(obj, NULL);
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c
index 740ee8086a27..fe0a890775e2 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c
@@ -43,7 +43,7 @@ static int igt_gem_huge(void *arg)
obj = huge_gem_object(i915,
nreal * PAGE_SIZE,
- i915->ggtt.vm.total + PAGE_SIZE);
+ to_gt(i915)->ggtt->vm.total + PAGE_SIZE);
if (IS_ERR(obj))
return PTR_ERR(obj);
--
2.34.1
- Reviewed-by : Sujaritha Sundaresan
On 12/16/2021 3:30 PM, Vinay Belgaumkar wrote:
By default, GT (and GuC) run at RPn. Requesting for RP0
before firmware load can speed up DMA and HuC auth as well.
In addition to writing to 0xA008, we also need to enable
swreq in 0xA024 so that Punit will pay heed to our request.
SLPC will rest
On 12/21/2021 10:11 AM, Ewins, Jon wrote:
On 12/20/2021 3:52 PM, Sundaresan, Sujaritha wrote:
On 12/16/2021 3:30 PM, Vinay Belgaumkar wrote:
By default, GT (and GuC) run at RPn. Requesting for RP0
before firmware load can speed up DMA and HuC auth as well.
In addition to writing to 0xA008
q_mhz+─-> kept as existing ABI;
├── gt_min_freq_mhz|it points to gt0/
├── gt_RP0_freq_mhz|
└── gt_RP1_freq_mhz|
└── gt_RPn_freq_mhz -+
Signed-off-by: Andi Shyti
Signed-off-by: Lucas De Marchi
Cc: Matt Roper
Cc: Sujaritha Sundaresan
q_mhz+─-> kept as existing ABI;
├── gt_min_freq_mhz|it points to gt0/
├── gt_RP0_freq_mhz|
└── gt_RP1_freq_mhz|
└── gt_RPn_freq_mhz -+
Signed-off-by: Andi Shyti
Signed-off-by: Lucas De Marchi
Cc: Matt Roper
Cc: Sujaritha Sundaresan
intel_runtime_pm(gt->uncore->rpm, wakeref)
+ val = intel_uncore_read(gt->uncore, reg32);
+
+ return val;
+}
Yes, you are right!
@Sujaritha: shall I move "__rps_read_mmio()" in intel_gt.c and
call it intel_gt_read_mmio()?
[...]
Sure since it is kind of a
rt out the register mask value since the sysfs is
supposed to a 0/1 status.
[...]
+#define GT0_PERF_LIMIT_REASONS _MMIO(0x1381A8)
+#define GT0_PERF_LIMIT_REASONS_MASK 0x0de3
This mask is really weird! Sujaritha, can you please explain it?
It looks something like this,
On 9/8/2022 4:12 PM, Andi Shyti wrote:
Hi,
On Wed, Sep 07, 2022 at 10:21:53PM -0700, Ashutosh Dixit wrote:
Perf limit reasons bit positions were off by one.
Fixes: fa68bff7cf27 ("drm/i915/gt: Add sysfs throttle frequency interfaces")
Cc: sta...@vger.kernel.org # v5.18+
Cc:
On 7/23/2020 6:07 PM, Chris Wilson wrote:
Gracefully skip over the failures in the frequency scaling for the
moment, the results are under review.
Signed-off-by: Chris Wilson
Cc: "Sundaresan, Sujaritha"
Cc: "Ewins, Jon"
---
drivers/gpu/drm/i915/gt/selftest_rps.c | 4 +
and even if GuC submission
is disable to debug issues with GuC loading or with whatever we're using
GuC for. To make a concrete example, the pages used by GuC to save state
during suspend are allocated as part of the ADS.
Signed-off-by: Sujaritha Sundaresan
Cc: Daniele Ceraolo Spurio
Cc: M
Including GEM_BUG_ON for GuC reset function in
intel_uncore.
Signed-off-by: Sujaritha Sundaresan
Cc: Chris Wilson
Cc: Michal Wajdeczko
Cc: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_uncore.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915
and even if GuC submission
is disable to debug issues with GuC loading or with whatever we're using
GuC for. To make a concrete example, the pages used by GuC to save state
during suspend are allocated as part of the ADS.
Signed-off-by: Sujaritha Sundaresan
Cc: Chris Wilson
Cc: Michal Wajd
Instead of returning -EINVAL, GEM_BUG_ON when GuC reset is invoked for
platforms not supporting as we don't expect to invoke it.
v2: re-wording commit message and subject (Sagar)
Signed-off-by: Sujaritha Sundaresan
Cc: Chris Wilson
Cc: Michal Wajdeczko
Cc: Sagar Arun Kamble
---
driver
and even if GuC submission
is disable to debug issues with GuC loading or with whatever we're using
GuC for. To make a concrete example, the pages used by GuC to save state
during suspend are allocated as part of the ADS.
Signed-off-by: Sujaritha Sundaresan
Cc: Chris Wilson
Cc: Michal Wajd
Instead of returning -EINVAL, GEM_BUG_ON when GuC reset is invoked for
platforms not supporting as we don't expect to invoke it.
v2: re-wording commit message and subject (Sagar)
Signed-off-by: Sujaritha Sundaresan
Cc: Chris Wilson
Cc: Michal Wajdeczko
Cc: Sagar Arun Kamble
---
driver
Instead of returning -EINVAL, GEM_BUG_ON when GuC reset is invoked for
platforms not supporting as we don't expect to invoke it.
v2: re-wording commit message and subject (Sagar)
Signed-off-by: Sujaritha Sundaresan
Cc: Chris Wilson
Cc: Michal Wajdeczko
Cc: Sagar Arun Kamble
Review
even if GuC submission
is disabled, to debug issues with GuC loading or with whatever we're using
GuC for.
v2: re-wording commit message (Sagar)
Signed-off-by: Sujaritha Sundaresan
Cc: Chris Wilson
Cc: Michal Wajdeczko
Cc: Sagar Arun Kamble
Reviewed-by: Sagar Arun Kamble
---
drivers/gp
e we have a HuC (but all platforms with HuC have a GuC and viceversa).
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messages, correcting inconsistencies (Michal)
Cc: Michal Wajdeczko
Cc: Anusha Srivatsa
Cc: Oscar Mateo
Cc: Daniele Ceraolo Spurio
Signed-off-by: Sujaritha Sund
ialization of GuC objects
Cc: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Anusha Srivatsa
Cc: Daniele Ceraolo Spurio
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_guc_submission.c | 108 ++
drivers/gpu/drm/i915/intel_uc.c
ialization of GuC objects
Cc: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Anusha Srivatsa
Cc: Daniele Ceraolo Spurio
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_guc_submission.c | 108 ++
drivers/gpu/drm/i915/intel_uc.c
e we have a HuC (but all platforms with HuC have a GuC and
viceversa).
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messages, correcting inconsistencies (Michal)
v4: Rebased
Cc: Michal Wajdeczko
Cc: Anusha Srivatsa
Cc: Oscar Mateo
Cc: Daniele Ceraolo Spurio
Signed-off-by:
ialization of GuC objects
v4: Rebased
Cc: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Anusha Srivatsa
Cc: Daniele Ceraolo Spurio
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_guc_submission.c | 121 +---
drivers/gpu/drm/i915/intel_guc_log.c | 6 +-
d
warning generated as a result of patch
4.
Cc: Anusha Srivatsa
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Sagar Arun Kamble
Sujaritha Sundaresan (5):
drm/i915/guc : Unifying seq_puts messages
drm/i915/guc : Removing i915_modparams.enable_guc_loading module
drm
Srivatsa
Cc: Oscar Mateo
Cc: Sagar Arun Kamble
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_debugfs.c | 11 +--
drivers/gpu/drm/i915/i915_drv.h | 9 --
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
Kamble
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_debugfs.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 847f8e8..53e40dd 100644
--- a/drivers/gpu/drm/i915
essage
Cc: Anusha Srivatsa
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Sagar Arun Kamble
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_guc_submission.c | 114 +---
drivers/gpu/drm/i915/intel_guc_log.c | 6 +-
drive
nusha Srivatsa
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Sagar Arun Kamble
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_guc_submission.c | 7 ++---
drivers/gpu/drm/i915/intel_uc.c| 41 +-
drivers/gpu/drm
Reverting argument type (struct intel_guc *guc) to expected type due to warning.
Cc: Anusha Srivatsa
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Sagar Arun Kamble
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_guc_submission.c | 7
Replacing conditions to remove dependance on enable_guc_submission
v9: Including guc_log_level in the condition (Sagar)
Signed-off-by: Sujaritha Sundaresan
Cc: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_guc_log.c | 6 +++---
1 file changed, 3
patch
v6: Re-factoring code (Sagar, Michal)
Rebase
v7: Separating from previuos patch (Sagar)
Rebase
v8: Including change to intel_uc.c
Applying review comments (Michal)
v9: Including HAS_HUC macro
Signed-off-by: Sujaritha Sundaresan
Cc: Anusha Srivatsa
Cc: Michal Wajdeczko
Cc
(Sagar)
v7: Generalizing subject to drm/i915 (Sagar)
v8: Omitting DRRS seq_puts unification (Michal)
v9: Including the HAS_HUC condition (Michal)
Updating more functions with unified message (Sagar)
Suggested by : Michal Wajdeczko
Signed-off-by: Sujaritha Sundaresan
Cc: Daniele Ceraolo Spurio
verting to goto err format (Michal)
Moved guc_ads functions to dedicated file
Rebase
v7: Rebase
v8: Applying review comments (Michal)
v9: Defining intel_guc_init function (Sagar)
Applying review comments (Michal, Sagar)
Signed-off-by: Sujaritha Sundaresan
Cc: Chris Wilson
Cc: Danie
GuC logs and ADS from submission.
Cc: Anusha Srivatsa
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Sagar Arun Kamble
Sujaritha Sundaresan (8):
drm/i915 : Unifying seq_puts messages for feature support
drm/i915/guc : Removing
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