On 7/22/2015 3:37 PM, Sonika Jindal wrote:
As per bspec, on BXT A0/A1, sw needs to activate DDIA HPD logic
and interrupts to check the external panel connection and DDIC HPD
logic for edp panel.
v2: For DP, irq_port is used to determine the encoder instead of
hpd_pin and removing the edp HPD l
On 7/22/2015 4:39 PM, Jindal, Sonika wrote:
On 7/22/2015 4:03 PM, Sivakumar Thulasimani wrote:
On 7/22/2015 3:37 PM, Sonika Jindal wrote:
As per bspec, on BXT A0/A1, sw needs to activate DDIA HPD logic
and interrupts to check the external panel connection and DDIC HPD
logic for edp panel
On 7/22/2015 5:32 PM, Jindal, Sonika wrote:
On 7/22/2015 5:01 PM, Sivakumar Thulasimani wrote:
On 7/22/2015 4:39 PM, Jindal, Sonika wrote:
On 7/22/2015 4:03 PM, Sivakumar Thulasimani wrote:
On 7/22/2015 3:37 PM, Sonika Jindal wrote:
As per bspec, on BXT A0/A1, sw needs to activate
From: "Thulasimani,Sivakumar"
DP spec requires the checksum of the last block read to be written
when replying to TEST_EDID_READ. This patch fixes the current code
to do the same.
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c |9 -
1 file
On 7/22/2015 5:30 PM, Daniel Vetter wrote:
On Wed, Jul 22, 2015 at 03:36:48PM +0530, Sivakumar Thulasimani wrote:
From: "Thulasimani,Sivakumar"
DP spec requires the checksum of the last block read to be written
when replying to TEST_EDID_READ. This patch fixes the current code
Reviewed-by: Sivakumar Thulasimani
On 7/24/2015 5:04 AM, Rodrigo Vivi wrote:
By Vesa's DP 1.2 Spec this counter has 4 bits [3:0].
This mask is wrong since when the counter was introduced by myself
on commit ad9dc91b6e21266bfc6f466db4b95e10211f31ee
Author: Rodrigo Vivi
Date: Tue Sep
On 7/6/2015 4:35 PM, Vandana Kannan wrote:
From: Deepak M
LFP brighness control from the VBT block 43 indicates which
controller is used for brightness.
LFP1 brightness control method:
Bit 7-4 = This field controller number of the brightnes controller.
0 = Controller 0
1 = Controller 1
2 = Co
Any comments for this change ?
On 7/22/2015 6:31 PM, Sivakumar Thulasimani wrote:
From: "Thulasimani,Sivakumar"
DP spec requires the checksum of the last block read to be written
when replying to TEST_EDID_READ. This patch fixes the current code
to do the same.
Signed-off-by:
Reviewed-by: Sivakumar Thulasimani
On 7/27/2015 11:02 AM, Sonika Jindal wrote:
WA for BXT A0/A1, where DDIB's HPD pin is swapped to DDIA, so enabling
DDIA HPD pin in place of DDIB.
v2: For DP, irq_port is used to determine the encoder instead of
hpd_pin and removing the edp HPD
why not detect reverse in intel_dp_detect/intel_hpd_pulse ? that way you
can identify both lane count and reversal state without touching
anything in the link training code. i am yet to upstream my changes for
CHT that i can share if required that does the same in intel_dp_detect
without touchi
On 7/29/2015 8:52 PM, Benjamin Tissoires wrote:
On Jul 29 2015 or thereabouts, Sivakumar Thulasimani wrote:
why not detect reverse in intel_dp_detect/intel_hpd_pulse ? that way you can
identify both lane count and reversal state without touching anything in the
link training code. i am yet to
From: "Thulasimani,Sivakumar"
BPP bits defined in VBT should be used only on panels whose
edid version is 1.3 or older. EDID version 1.4 introduced offsets
where bpp is defined and hence should be preferred over any value
programmed in VBT.
Signed-off-by: Sivakumar Thulasimani
---
d
From: "Thulasimani,Sivakumar"
CHV does not support intermediate link rates nor does it support
HBR2. This patch removes those entries and returns HBR as the max
link rate supported on CHV platform.
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c | 11 +++-
On 7/30/2015 3:27 PM, Jani Nikula wrote:
On Thu, 30 Jul 2015, Sivakumar Thulasimani
wrote:
From: "Thulasimani,Sivakumar"
BPP bits defined in VBT should be used only on panels whose
edid version is 1.3 or older. EDID version 1.4 introduced offsets
where bpp is defined and hence
On 7/30/2015 3:31 PM, Jani Nikula wrote:
On Thu, 30 Jul 2015, Sivakumar Thulasimani
wrote:
From: "Thulasimani,Sivakumar"
CHV does not support intermediate link rates nor does it support
HBR2. This patch removes those entries and returns HBR as the max
link rate supported on CH
On 7/30/2015 10:48 PM, Hindman, Gavin wrote:
This applies to all CHV derivatives, including BSW?
Gavin Hindman
yes, this will apply to all CHV derivatives.
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Sivakumar Thulasimani
Sent
.
v2: use display_info.bpc for deciding when to use vbt_bpp (Jani)
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 44f8a32..ae00e86 10
From: "Thulasimani,Sivakumar"
This reverts
commit fe51bfb95c996733150c44d21e1c9f4b6322a326.
Author: Ville Syrjälä
Date: Thu Mar 12 17:10:38 2015 +0200
CHV does not support intermediate frequencies so reverting the
patch that added it in the first place
Signed-off-by: Sivakumar T
From: "Thulasimani,Sivakumar"
This patch removes 5.4Gbps from supported link rate for CHV since
it is not supported in it.
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gp
On 8/5/2015 3:23 PM, Imre Deak wrote:
On Mon, 2015-07-27 at 11:02 +0530, Sonika Jindal wrote:
WA for BXT A0/A1, where DDIB's HPD pin is swapped to DDIA, so enabling
DDIA HPD pin in place of DDIB.
v2: For DP, irq_port is used to determine the encoder instead of
hpd_pin and removing the edp HPD
On 7/27/2015 6:05 PM, Maarten Lankhorst wrote:
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/intel_display.c | 7 --
drivers/gpu/drm/i915/intel_dp_mst.c | 45 +++-
2 files changed, 44 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/
On 8/6/2015 1:04 AM, Benjamin Tissoires wrote:
On Jul 30 2015 or thereabouts, Sivakumar Thulasimani wrote:
On 7/29/2015 8:52 PM, Benjamin Tissoires wrote:
On Jul 29 2015 or thereabouts, Sivakumar Thulasimani wrote:
why not detect reverse in intel_dp_detect/intel_hpd_pulse ? that way you
thanks for the change :)
Reviewed-by: Sivakumar Thulasimani
On 8/6/2015 5:17 PM, Maarten Lankhorst wrote:
Fully remove the MST connector from the atomic state, and remove the
early returns in check_*_state for MST connectors.
With atomic the state can be made consistent all the time
ned-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c |9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f1b9f93..fa6e202 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gp
Reviewed-by: Sivakumar Thulasimani
On 8/10/2015 10:35 AM, Sonika Jindal wrote:
With HPD support added for all ports including PORT_A, setting hpd_pin will
result in enabling of hpd to edp as well. There is no need to enable HPD on
PORT_A hence this patch removes hpd_pin update for PORT_A
Reviewed-by: Sivakumar Thulasimani
On 8/10/2015 10:35 AM, Sonika Jindal wrote:
Also remove redundant comments.
Signed-off-by: Sonika Jindal
---
drivers/gpu/drm/i915/i915_irq.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c
Reviewed-by: Sivakumar Thulasimani
On 8/10/2015 10:35 AM, Sonika Jindal wrote:
WA for BXT A0/A1, where DDIB's HPD pin is swapped to DDIA, so enabling
DDIA HPD pin in place of DDIB.
v2: For DP, irq_port is used to determine the encoder instead of
hpd_pin and removing the edp HPD logic be
On 7/14/2015 5:21 PM, Sonika Jindal wrote:
Adding this for SKL onwards.
v2: Adding checks for VLV/CHV as well. Reusing old ibx and g4x functions
to check digital port status. Adding a separate function to get bxt live
status (Daniel)
Signed-off-by: Sonika Jindal
---
drivers/gpu/drm/i915/in
hi Mengdong,
is there any reason why you cannot modify VBT ? unless it is
shipped version you
can just flash the modified VBT along with BIOS.
Chris,
i would be even more surprised if VBIOS/GOP can enable some display
when it is
configured incorrectly in VBT. Give me a day to check wit
have a quirk for this config since this seems to be reported atleast for
now as suggested
by Lukas
i would recommend the first method, if we confirm the root cause is as
explained above.
On 8/10/2015 11:35 AM, Sivakumar Thulasimani wrote:
hi Mengdong,
is there any reason why you cannot
On 8/10/2015 5:07 PM, Jani Nikula wrote:
On Mon, 10 Aug 2015, Sivakumar Thulasimani
wrote:
Reviewed-by: Sivakumar Thulasimani
On 8/10/2015 10:35 AM, Sonika Jindal wrote:
With HPD support added for all ports including PORT_A, setting hpd_pin will
result in enabling of hpd to edp as well
On 8/10/2015 5:44 PM, Jani Nikula wrote:
On Mon, 10 Aug 2015, Sivakumar Thulasimani
wrote:
On 8/10/2015 5:07 PM, Jani Nikula wrote:
On Mon, 10 Aug 2015, Sivakumar Thulasimani
wrote:
Reviewed-by: Sivakumar Thulasimani
On 8/10/2015 10:35 AM, Sonika Jindal wrote:
With HPD support added
Hi Daniel,
any comments for the patch below ?
regards,
Sivakumar
On Friday 07 August 2015 03:14 PM, Sivakumar Thulasimani wrote:
From: "Thulasimani,Sivakumar"
DP spec requires the checksum of the last block read to be written
when replying to TEST_EDID_READ. This patch fixes t
hi Ville,
can you review these patches ?
regards,
Sivakumar
On Friday 31 July 2015 11:32 AM, Sivakumar Thulasimani wrote:
From: "Thulasimani,Sivakumar"
This reverts
commit fe51bfb95c996733150c44d21e1c9f4b6322a326.
Author: Ville Syrjälä
Date: Thu Mar 12 17:10:38 2015 +0200
CH
On 8/12/2015 5:02 PM, Ville Syrjälä wrote:
On Fri, Jul 31, 2015 at 11:32:52AM +0530, Sivakumar Thulasimani wrote:
From: "Thulasimani,Sivakumar"
This reverts
commit fe51bfb95c996733150c44d21e1c9f4b6322a326.
Author: Ville Syrjälä
Date: Thu Mar 12 17:10:38 2015 +0200
CHV does n
On 8/12/2015 6:26 PM, Daniel Vetter wrote:
On Mon, Aug 10, 2015 at 05:51:48PM +0530, Sivakumar Thulasimani wrote:
On 8/10/2015 5:44 PM, Jani Nikula wrote:
On Mon, 10 Aug 2015, Sivakumar Thulasimani
wrote:
On 8/10/2015 5:07 PM, Jani Nikula wrote:
On Mon, 10 Aug 2015, Sivakumar
sdvo is still using color_range name in it's functions. would be good to
rename that as well along with dp & hdmi done here.
otherwise changes are fine
Reviewed-by: Sivakumar Thulasimani
On Monday 06 July 2015 05:40 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Cur
Reviewed-by: Sivakumar Thulasimani
On Monday 06 July 2015 07:09 PM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Currently we clobber intel_dp->lane_count in compute config, which means
after a rejected modeset we may no longer be able to retrain the current
link. Move lane_co
On 8/14/2015 12:29 PM, Jani Nikula wrote:
On Wed, 12 Aug 2015, Daniel Vetter wrote:
On Wed, Aug 12, 2015 at 04:02:17PM +0300, Ville Syrjälä wrote:
On Wed, Aug 12, 2015 at 05:31:55PM +0530, Sivakumar Thulasimani wrote:
On 8/12/2015 5:02 PM, Ville Syrjälä wrote:
On Fri, Jul 31, 2015 at 11
From: "Thulasimani,Sivakumar"
These two patches together help detect DP displays on short pulse HPD
and pass the respective compliance test case (4.2.2.8)
Thulasimani,Sivakumar (2):
drm/i915: Read sink_count dpcd always for short hpd
drm/i915: Perform full detect on sink_count change
drive
From: "Thulasimani,Sivakumar"
This patch checks for changes in sink_count during short pulse hpd
in check_link_status and forces full detect when sink_count
changes. Compliance test 4.2.2.8 expects this behavior in
compliant driver.
Signed-off-by: Sivakumar Thulasimani
---
drive
oving crtc enabled checks post sink_count read call
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c | 117 ---
1 file changed, 59 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_
From: "Thulasimani,Sivakumar"
This patch removes 5.4Gbps from supported link rate for CHV since
it is not supported in it.
v2: change the ordering for better readability (Ville)
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c |7 ---
1 file
From: "Thulasimani,Sivakumar"
This reverts
commit fe51bfb95c996733150c44d21e1c9f4b6322a326.
Author: Ville Syrjälä
Date: Thu Mar 12 17:10:38 2015 +0200
CHV does not support intermediate frequencies so reverting the
patch that added it in the first place
Signed-off-by: Sivakumar T
From: "Thulasimani,Sivakumar"
This patch series cleans up the code to remove HBR2 support
for CHV since it is not supported on CHV. Also fixes a bug
for SKL platforms where HBR2 is not supported.
Thulasimani,Sivakumar (4):
Revert "drm/i915: Add eDP intermediate frequencies for CHV"
drm/i915:
From: "Thulasimani,Sivakumar"
This patch fixes the bug that SKL SKUs before B0 might return
HBR2 as supported even though it is not supposed to be enabled
on such platforms.
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c | 14 --
1 file
From: "Thulasimani,Sivakumar"
This patch removes TP3 support on CHV since there is no support
for HBR2 on this platform.
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
di
oving crtc enabled checks post sink_count read call
v2: avoid code movement with functionality changes (Ville)
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/in
From: "Thulasimani,Sivakumar"
This patch checks for changes in sink_count during short pulse hpd
in check_link_status and forces full detect when sink_count
changes. Compliance test 4.2.2.8 expects this behavior in
compliant driver.
Signed-off-by: Sivakumar Thulasimani
---
drive
From: "Thulasimani,Sivakumar"
These two patches together help detect DP displays on short pulse HPD
and pass the respective compliance test case (4.2.2.8)
Thulasimani,Sivakumar (2):
drm/i915: Read sink_count dpcd always for short hpd
drm/i915: Perform full detect on sink_count change
drive
On 8/17/2015 5:39 PM, Jani Nikula wrote:
On Mon, 17 Aug 2015, Sivakumar Thulasimani
wrote:
From: "Thulasimani,Sivakumar"
Compliance test 4.2.2.8 requires driver to read the sink_count for
short pulse interrupt even when the panel is not enabled.
This patch performs the f
On 8/17/2015 6:11 PM, Ville Syrjälä wrote:
On Mon, Aug 17, 2015 at 05:45:11PM +0530, Sivakumar Thulasimani wrote:
From: "Thulasimani,Sivakumar"
This patch fixes the bug that SKL SKUs before B0 might return
HBR2 as supported even though it is not supposed to be enabled
on such
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c |6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index b905c19..bfe0567 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/
From: "Thulasimani,Sivakumar"
This patch fixes the bug that SKL SKUs before B0 might return
HBR2 as supported even though it is not supposed to be enabled
on such platforms.
v2: optimize if else condition (Jani)
Reviewed-by: Ville Syrjälä
Signed-off-by: Sivakumar Thulasimani
---
d
From: "Thulasimani,Sivakumar"
This patch removes 5.4Gbps from supported link rate for CHV since
it is not supported in it.
v2: change the ordering for better readability (Ville)
Reviewed-by: Ville Syrjälä
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_d
From: "Thulasimani,Sivakumar"
This patch removes TP3 support on CHV since there is no support
for HBR2 on this platform.
v2: rename the function to indicate it checks source rates (Jani)
Reviewed-by: Ville Syrjälä
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/
From: "Thulasimani,Sivakumar"
This patch series cleans up the code to remove HBR2 support
for CHV since it is not supported on CHV. Also fixes a bug
for SKL platforms where HBR2 is not supported.
V2:
Added RB from Ville Syrjälä
patches 3 & 4 updated with comments from Jani.
Thulasimani,Siva
On 8/17/2015 5:59 PM, Jani Nikula wrote:
On Mon, 17 Aug 2015, Sivakumar Thulasimani
wrote:
From: "Thulasimani,Sivakumar"
This patch fixes the bug that SKL SKUs before B0 might return
HBR2 as supported even though it is not supposed to be enabled
on such platforms.
Sig
On 8/18/2015 12:14 PM, Jani Nikula wrote:
On Tue, 18 Aug 2015, Sivakumar Thulasimani
wrote:
From: "Thulasimani,Sivakumar"
This patch removes TP3 support on CHV since there is no support
for HBR2 on this platform.
v2: rename the function to indicate it checks source rates (Jani)
-by: Ville Syrjälä
Signed-off-by: Sivakumar Thulasimani
---
drivers/gpu/drm/i915/intel_dp.c | 31 +++
1 file changed, 23 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 475d8cb..051614a 100644
--- a/drive
On 8/18/2015 12:42 PM, Jani Nikula wrote:
On Tue, 18 Aug 2015, Sivakumar Thulasimani
wrote:
On 8/18/2015 12:14 PM, Jani Nikula wrote:
On Tue, 18 Aug 2015, Sivakumar Thulasimani
wrote:
From: "Thulasimani,Sivakumar"
This patch removes TP3 support on CHV since there is no s
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