On 3/14/2018 3:07 PM, Chris Wilson wrote:
As we know that whenever the GT is awake, rc6 and rps are enabled (if
available), then we can remove the individual tracking and enabling to
the gen6_rps_busy/gen6_rps_idle() (now called intel_gt_pm_busy and
intel_gt_pm_idle) entry points.
Signed-off-b
On 3/14/2018 3:07 PM, Chris Wilson wrote:
When choosing the initial frequency in intel_gt_pm_busy() we also need
to calculate the current min/max bounds. As this calculation is going to
become more complex with the intersection of several different limits,
refactor it to a common function. The
On 3/17/2018 8:36 PM, Michal Wajdeczko wrote:
We already try to keep all GuC log related code in separate file,
handling flush event should be placed there too. This will also
allow future code reuse.
Signed-off-by: Michal Wajdeczko
Cc: Michal Winiarski
Cc: Sagar Arun Kamble
Cc: Chris
On 3/14/2018 3:07 PM, Chris Wilson wrote:
Resetting the GPU doesn't affect the RPS/RC6 state, so we can stop
forcibly reloading the registers.
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
Changes look good to me.
Reviewed-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_gem.
On 3/14/2018 3:07 PM, Chris Wilson wrote:
In preparation for more layers of limits, rename the existing limits to
hw and user.
Signed-off-by: Chris Wilson
Reviewed-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_debugfs.c | 34
drivers/gpu/drm/i915/i915_drv.h | 21
S merge is happening in next patch.
Reviewed-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.h| 37 -
drivers/gpu/drm/i915/i915_irq.c| 21 +-
drivers/gpu/drm/i915/intel_gt_pm.c | 83 +-
drivers/gpu/drm/i915/intel_pm
On 3/14/2018 3:07 PM, Chris Wilson wrote:
We always start off at an "efficient frequency" and can let the system
autotune from there, eliminating the need to clamp the available range.
Signed-off-by: Chris Wilson
Reviewed-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_g
On 3/14/2018 3:07 PM, Chris Wilson wrote:
Often, we find ourselves facing a workload where the user knows in
advance what GPU frequency they require for it to complete in a timely
manner, and using past experience they can outperform the HW assisted
RPS autotuning. An example might be kodi (HTP
Move guc_log_flush_irq_disable up to avoid movement in following
patches (Sagar).
v3: s/guc_log_flush_irq_*/guc_flush_log_msg_*, rebase after mass rename
Signed-off-by: Michał Winiarski
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
Cc: Sagar Arun Kamble
Cc: Michal Wajdeczko
Reviewed-by: Sagar
1 Non-verbose log
2-5 Verbose log
v2: Adjust naming after rebase.
v3: Fixed the log_level logic error introduced on rebase.
Signed-off-by: Michał Winiarski
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
Cc: Sagar Arun Kamble
Cc: Michal Wajdeczko
Reviewed-by: Sagar Arun Kamble (v2
i
Cc: Vinay Belgaumkar
Cc: Tvrtko Ursulin
Cc: Michal Wajdeczko
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
Cc: Sagar Arun Kamble
Signed-off-by: Rodrigo Vivi
Signed-off-by: Oscar Mateo
Reviewed-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.c | 4 +++
drivers/gpu/drm/i9
On 3/19/2018 8:58 PM, Michal Wajdeczko wrote:
There is no need to mix parameter types in public CT functions
as we can always accept intel_guc_ct.
Signed-off-by: Michal Wajdeczko
Cc: Sagar Arun Kamble
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_guc_ct.c | 34
On 3/20/2018 6:30 PM, Michal Wajdeczko wrote:
On Tue, 20 Mar 2018 08:24:14 +0100, Sagar Arun Kamble
wrote:
On 3/19/2018 8:58 PM, Michal Wajdeczko wrote:
There is no need to mix parameter types in public CT functions
as we can always accept intel_guc_ct.
Signed-off-by: Michal Wajdeczko
n
v3:
- Updated GuC Address Space kernel-doc based on Michal's suggestion
Signed-off-by: Jackie Li
Cc: Michal Wajdeczko
Cc: Sagar Arun Kamble
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/intel_guc.c | 56 --
drivers/gpu/drm/i915/intel_wo
arski
Cc: Michal Wajdeczko
Cc: Sagar Arun Kamble
Cc: Joonas Lahtinen
Cc: Jackie Li
Cc: Radoslaw Szwichtenberg
Reviewed-by: Michal Wajdeczko
Reviewed-by: Jackie Li
---
drivers/gpu/drm/i915/intel_uc_fw.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/dr
On 3/23/2018 8:44 PM, Michal Wajdeczko wrote:
In function gem_init_hw() we are calling uc_init_hw() but in case
of error later in function, we missed to call matching uc_fini_hw()
Signed-off-by: Michal Wajdeczko
Cc: Sagar Arun Kamble
Cc: Chris Wilson
Looks good.
Reviewed-by: Sagar Arun
On 3/23/2018 8:44 PM, Michal Wajdeczko wrote:
We should not leave GuC submission enabled after sanitize,
as we are going to reset all GuC/HuC hardware.
Signed-off-by: Michal Wajdeczko
Cc: Sagar Arun Kamble
Cc: Chris Wilson
Either we need now destroy the doorbells cleanly or remove the
-off-by: Michal Wajdeczko
Cc: Sagar Arun Kamble
Cc: Chris Wilson
We should drop call to uc_fini_hw from gem_fini as part of this patch as
GuC won't be available then.
---
drivers/gpu/drm/i915/intel_uc.c | 14 ++
1 file changed, 2 insertions(+), 12 deletions(-)
diff --
On 3/27/2018 1:18 AM, Michal Wajdeczko wrote:
As we are going to extend our use of MMIO based communication,
try to explain its mechanics and update corresponding definitions.
v2: fix checkpatch MACRO_ARG_REUSE
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Sagar Arun
On 3/28/2018 2:05 AM, Michal Wajdeczko wrote:
We should not leave GuC submission enabled after sanitize,
as we are going to reset all GuC/HuC hardware.
Signed-off-by: Michal Wajdeczko
Cc: Sagar Arun Kamble
Cc: Chris Wilson
Reviewed-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915
paths, we can restore symmetry in
doorbell cleanup, as GuC should be still active by now.
Suggested-by: Sagar Arun Kamble
Signed-off-by: Michal Wajdeczko
Cc: Sagar Arun Kamble
Cc: Michal Winiarski
Cc: Chris Wilson
This looks good.
Reviewed-by: Sagar Arun Kamble
We should extend this fun
-off-by: Michal Wajdeczko
Cc: Sagar Arun Kamble
Cc: Chris Wilson
Reviewed-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_uc.c | 14 ++
1 file changed, 2 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index
won't have to bother if GuC is loaded or not.
w/ or w/o that change patch looks good though.
Reviewed-by: Sagar Arun Kamble
+
intel_uc_sanitize(i915);
}
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h b/drivers/gpu/drm/i915/intel_uc_fw.h
index dc33b12..77ad2aa 100644
---
On 3/28/2018 2:05 AM, Michal Wajdeczko wrote:
v2: except running with HYPERVISOR
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_uc.c| 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i91
ring min/max frequency limits.
Signed-off-by: Sagar Arun Kamble
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Radoslaw Szwichtenberg
Cc: Michal Wajdeczko
Cc: Sujaritha Sundaresan
Cc: Jeff McGee
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_irq.c | 18 --
: Enabling Balancer task in SLPC.
v10: Rebase.
v11: Rebase. Added lock specific to SLPC.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Radoslaw Szwichtenberg
Cc: Michal Wajdeczko
Cc: Sujaritha Sundaresan
Cc: Jeff McGee
---
drive
o GuC action.
v1: Use intel_slpc_enabled() (Paulo)
v2-v4: Rebase.
v5: Changed intel_slpc_enabled() to i915.enable_slpc. (Sagar)
v6: Changed i915.enable_slpc to intel_slpc_enabled(). (Sagar)
v7: Rebase.
v8: Rebase.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
Cc: Chris
changed.
VIZ-6889, VIZ-6890
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Beuchat Marc
Cc: Wang Zhe1
Cc: Sun Daisy
Cc: Oscar Mateo
Cc: Radoslaw Szwichtenberg
Cc: Michal Wajdeczko
Cc: Sujaritha Sundaresan
Cc: Jeff McGee
Tested-by: Radoslaw Szwichtenberg
Sagar Arun Kamble (12):
drm/i915/guc
-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Radoslaw Szwichtenberg
Cc: Michal Wajdeczko
Cc: Sujaritha Sundaresan
Cc: Jeff McGee
---
drivers/gpu/drm/i915/intel_guc_slpc.c | 173 ++
drivers/gpu/drm
they are used.
v10: Rebase. Prepared separate header for SLPC firmware interface.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Radoslaw Szwichtenberg
Cc: Michal Wajdeczko
Cc: Sujaritha Sundaresan
Cc: Jeff McGee
---
drivers/gp
itialized and guc_slpc_enabled to track state
of SLPC initialization and enabling.
v12: s/guc_slpc_cleanup/guc_slpc_fini. Updated SLPC flows w.r.t uC flows.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Radoslaw Szwichtenberg
Cc: Mi
: Sagar Arun Kamble
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Radoslaw Szwichtenberg
Cc: Michal Wajdeczko
Cc: Sujaritha Sundaresan
Cc: Jeff McGee
---
drivers/gpu/drm/i915/intel_guc_slpc.c | 239 ++
1 file changed, 239 insertions(+)
diff --git a/drivers/gpu/drm
20us. (Sagar)
v9: Updated the status check wait time to 5ms for safe margin as it is
handled similar to reset by SLPC. s/slpc_disabled/slpc_stopped
v10: Rebase.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Radoslaw Szwicht
Signed-off-by: Sagar Arun Kamble
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Radoslaw Szwichtenberg
Cc: Michal Wajdeczko
Cc: Sujaritha Sundaresan
Cc: Jeff McGee
---
drivers/gpu/drm/i915/i915_params.c | 5 +++--
drivers/gpu/drm/i915/i915_params.h | 1 +
drivers/gpu/drm/i915/intel_uc
.
Signed-off-by: Sagar Arun Kamble
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Radoslaw Szwichtenberg
Cc: Michal Wajdeczko
Cc: Sujaritha Sundaresan
Cc: Jeff McGee
---
drivers/gpu/drm/i915/i915_irq.c | 3 +++
drivers/gpu/drm/i915/intel_guc_slpc.c | 36
parsing that was misplaced at tokenize function.
v2: Moved buffer_tokenize to i915_debugfs.c (Michal Wajdeczko)
Signed-off-by: Sagar Arun Kamble
Cc: Tomeu Vizoso
Cc: Michal Wajdeczko
Acked-by: Radoslaw Szwichtenberg
---
drivers/gpu/drm/i915/i915_debugfs.c | 31 +++
drivers
tions to intel_slpc.c. RPM Get/Put added before setting
parameters and sending RESET event explicitly. (Sagar)
v7: Rebase.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Radoslaw Szwichtenberg
Cc: Michal Wajdeczko
Cc: Sujaritha Sundares
l_guc_slpc_enabled
instead of accessing status variable. Optimized token parsing.
(Michal Wajdeczko) s/i915_slpc_paramlist/i915_guc_slpc_params and
s/i915_slpc_param_ctl/i915_guc_slpc_param_ctl
v3: Rebase.
Signed-off-by: Sagar Arun Kamble
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Radoslaw Szwichtenbe
->pm.rps structure.
v8: Updated returns from gt_min_freq_mhz_store and gt_max_freq_mhz_store
and i915_min_freq_set and i915_max_freq_set.
v9: Rebase. Debugfs interfaces will be removed hence only updated sysfs.
Signed-off-by: Sagar Arun Kamble
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Rados
ty. (Sagar)
v4: idle_freq, boost_freq are also not used with SLPC.
v5: Added SLPC banner to i915_rps_boost_info and keep printing
driver internal values. (Chris)
v6: Commit message update.
v7: Rebase.
v8: Rebase.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
Cc: Chri
_info/i915_guc_slpc_info. Prepared helpers platform_sku
_to_string, power_plan_to_string and power_source_to_string.
(Michal Wajdeczko)
v7: Moved all SLPC data printing changes to guc_slpc.c and making use of
drm_printer.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 2484925..dd2de06 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b
Thanks for the review. Will update with all suggestions in the next rev.
On 3/30/2018 6:07 PM, Michal Wajdeczko wrote:
On Fri, 30 Mar 2018 10:31:46 +0200, Sagar Arun Kamble
wrote:
From: Tom O'Rourke
GuC is currently being used for submission and HuC authentication.
Choices c
On 3/30/2018 7:07 PM, Michal Wajdeczko wrote:
On Fri, 30 Mar 2018 10:31:50 +0200, Sagar Arun Kamble
wrote:
diff --git a/drivers/gpu/drm/i915/intel_guc_slpc.h
b/drivers/gpu/drm/i915/intel_guc_slpc.h
index 66c76fe..81250c0 100644
--- a/drivers/gpu/drm/i915/intel_guc_slpc.h
+++ b/drivers/gpu
On 4/5/2018 6:03 AM, Patchwork wrote:
== Series Details ==
Series: series starting with [v6,01/12] drm/i915: Correctly handle error path
in i915_gem_init_hw
URL : https://patchwork.freedesktop.org/series/41159/
State : failure
== Summary ==
Possible new issues:
Test gem_eio:
On 4/5/2018 4:32 PM, Chris Wilson wrote:
As different backends may have different park/unpark callbacks, we
should only ever switch backends (reset_default_submission on wedge
recovery, or on enabling the guc) while parked.
Signed-off-by: Chris Wilson
Cc: Michal Wajdeczko
Cc: Sagar Arun
to
modify the engine vfuncs pointer on a live system after reset (not just
wedging). We will just have to hope that the system is balanced.
v3: Rebase onto __i915_gem_park and improve grammar.
Signed-off-by: Chris Wilson
Cc: Michal Wajdeczko
Cc: Sagar Arun Kamble
Cc: Tvrtko Ursulin
Cc: Mika
On 4/9/2018 5:53 PM, Michal Wajdeczko wrote:
We should keep i915_gem_init/fini functions together for easier
tracking of their symmetry.
Signed-off-by: Michal Wajdeczko
Cc: Sagar Arun Kamble
Cc: Chris Wilson
Reviewed-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.c | 20
paths.
Signed-off-by: Michal Wajdeczko
Cc: Sagar Arun Kamble
Cc: Chris Wilson
Reviewed-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem.c | 13 +++--
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm
On 4/9/2018 5:53 PM, Michal Wajdeczko wrote:
By calling i915_gem_init_hw in i915_gem_resume and not calling
i915_gem_fini_hw in i915_gem_suspend we introduced asymmetry
in init_hw/fini_hw calls. Let's fix that.
Signed-off-by: Michal Wajdeczko
Cc: Sagar Arun Kamble
Cc: Chris W
On 4/9/2018 5:53 PM, Michal Wajdeczko wrote:
As we always call intel_uc_sanitize after every call to
intel_uc_fini_hw we may drop redundant call and sanitize
uC from the fini_hw function.
Signed-off-by: Michal Wajdeczko
Cc: Sagar Arun Kamble
Cc: Chris Wilson
With change to sanitize during
On 4/9/2018 9:02 PM, Michal Wajdeczko wrote:
On Mon, 09 Apr 2018 17:09:18 +0200, Patchwork
wrote:
== Series Details ==
Series: series starting with [v8,01/12] drm/i915: Park before
resetting the submission backend
URL : https://patchwork.freedesktop.org/series/41365/
State : failure
=
: Akash Goel
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_guc_submission.c | 8
drivers/gpu/drm/i915/i915_irq.c| 14 --
drivers/gpu/drm/i915/i915_reg.h| 3 ++-
drivers/gpu/drm/i915/intel_guc.h | 3 +++
drivers/gpu/drm/i915
from intel_guc. (ChrisW)
Cc: Chris Harris
Cc: Zhe Wang
Cc: Deepak S
Cc: Satyanantha, Rama Gopal M
Cc: Akash Goel
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_irq.c | 16 ++--
drivers/gpu/drm/i915
From: Ville Syrjälä
v2: s/gen6_rps_pm_mask/gen6_sanitize_rps_pm_mask/ (Chris)
Signed-off-by: Ville Syrjälä
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/i
from intel_guc. (ChrisW)
v3: restructuring the mask update and rebase w.r.t Ville's patch. (ChrisW)
Cc: Chris Harris
Cc: Zhe Wang
Cc: Deepak S
Cc: Satyanantha, Rama Gopal M
Cc: Akash Goel
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gp
From: Ville Syrjälä
SNB (and IVB too I suppose) starts to misbehave if the GPU gets stuck
in an infinite batch buffer loop. The GPU apparently hogs something
critical and CPUs start to lose interrupts and whatnot. We can keep
the system limping along by unmasking some interrupts in
GEN6_PMINTRMSK
from intel_guc. (ChrisW)
v3: restructuring the mask update and rebase w.r.t Ville's patch. (ChrisW)
v4: Updating the pm_intr_keep during direct_interrupts_to_guc. (Sagar)
Cc: Chris Harris
Cc: Zhe Wang
Cc: Deepak S
Cc: Satyanantha, Rama Gopal M
Cc: Akash Goel
Signed-off-by: Sagar Arun K
. (Daniel)
Runtime PM enabling happens before gen9_enable_rc6.
Moved the updation of enable_rc6 parameter in intel_uncore_sanitize.
v4: Added elaborate check for BIOS RC6 setup. Prepared check_pctx for bxt.
(Imre)
Change-Id: If89518708e133be6b3c7c6f90869fb66224b7b87
Signed-off-by: Sagar Arun Kamble
From: Sagar Kamble
With BXT, now all platforms from GEN6 to GEN9 support Runtime PM except IVB.
Cc: Paulo Zanoni
Cc: Imre Deak
Change-Id: I700bf5092d6462b64499d876efeaea9dfa540380
Signed-off-by: A.Sunil Kamath
Signed-off-by: Sagar Kamble
---
drivers/gpu/drm/i915/i915_drv.h | 7 +++
1 fi
Cc: Chris Wilson
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_sysfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index 47590ab..3df8d3d 100644
--- a/drivers/gpu/drm/i915
If min/max frequency is updated from debugfs/sysfs and device is
suspended, just update the driver tracking state cur_freq and it will
come into effect when HW becomes busy next.
v2: Folded awake check into if/else. (Jon)
Signed-off-by: Chris Wilson
Signed-off-by: Sagar Arun Kamble
ernal values. (Chris)
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_debugfs.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index bce3880..8f24fdf 100644
-
rlier patch.
v2-v3: Rebase.
v4: Updated support for GuC firmware v9.
v5: Commit subject updated.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_guc_loader.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_l
T
with SLPC Enabled.
v4: Updated support for GuC v9. s/slice_total/hweight8(slice_mask)/(Dave).
v5: SLPC vma mapping changes and removed explicit type conversions.(Chris).
s/freq_unslice_max|min/unslice__max|min_freq.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c0fcd73..9c75371 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -679,6 +679,7
separated RPS and RC6 handling and rebase. Commit message
update.(Sagar)
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.c | 6 -
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_pm.c | 54 +
3 files changed, 51
rious
driver scenarios is prepared.
VIZ-6773, VIZ-6889, VIZ-6890
Cc: Chris Wilson
Cc: Daniel Vetter
Cc: Beuchat, Marc
Cc: Jeff McGee
Sagar Arun Kamble (3):
drm/i915/gen9: Separate RPS and RC6 handling
drm/i915/slpc: Only enable GTPERF task, Disable other tasks/parameters
drm/i915
: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_pm.c | 8 +++
drivers/gpu/drm/i915/intel_slpc.c | 103 ++
drivers/gpu/drm/i915/intel_slpc.h | 4 ++
3 files changed, 115 insertions(+)
diff --git a/drivers/gpu/drm/i915/in
ntel_slpc_task_status
and s/slpc_enable_disable_set/intel_slpc_task_control. Prepared
separate functions to update the task status only in the SLPC
shared memory. Passing dev_priv as parameter.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_d
: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_debugfs.c | 165
1 file changed, 165 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 87d83d7..5e141c0 100644
--- a/d
es to u32. (Chris)
Changed intel_slpc_active to guc.slpc.enabled. Carved out
SLPC helpers to set min and max frequencies.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_debugfs.c | 26 +++--
drivers/gpu/drm/i915/i915_sysf
: fix whitespace (Sagar)
v2-v3: Rebase.
v4: Updated with GuC firmware v9.
v5: Added definition of input and output data structures for SLPC
events. Updated commit message.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_slpc.c | 30
C active status in GuC. State setup/cleanup needed
for SLPC is handled using kernel parameter i915.enable_slpc. Moved SLPC
init and enabling to GuC enable path as SLPC in GuC can start doing the
setup post GuC init. Commit message update. (Sagar)
Signed-off-by: Tom O'Rourke
Si
pdate.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_guc_submission.c | 22 +++---
drivers/gpu/drm/i915/intel_guc.h | 2 ++
2 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submi
Added SLPC state update during disable, suspend and reset.
Changed semantics of reset. It is supposed to just disable. (Sagar)
v2-v4: Rebase.
v5: Updated the input data structure. (Sagar)
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_s
ebase.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_guc_loader.c | 5 -
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/
state setup during to GuC load. (Sagar)
Suggested-by: Paulo Zanoni
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_params.c | 6 ++
drivers/gpu/drm/i915/i915_params.h | 1 +
drivers/gpu/drm/i915/intel_guc_loa
iewed-by: David Weinehall
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 2a41950..a1eb92d 100644
--- a/drivers/gp
bugfs interfaces.
A later patch in this series updates sysfs/debugfs
interfaces for setting max/min frequencies with SLPC.
v1: Use intel_slpc_active instead of HAS_SLPC (Paulo)
v2-v4: Rebase.
v5: Changed intel_slpc_active to i915.enable_slpc. (Sagar)
Signed-off-by: Tom O'Rourke
Signed-off-by:
v1: Updated tasks and frequency post reset.
Added DFPS param update for MAX_FPS and FPS Stall.
v2-v3: Rebase.
v4: Updated with GuC firmware v9.
v5: Rebase. Replaced H2G interrupts for parameter override with memory
setup with required parameters.
Signed-off-by: Sagar Arun Kamble
indicated status as RUNNING in the shared
data. i915_load_enable is used to read default parameters set by
SLPC like min and max frequency on boot. Post that on re-activation
of SLPC, user set min and max frequencies will be communicated to SLPC.
Signed-off-by: Sagar Arun Kamble
---
drivers
setup shared data with all parameters and send
single event to SLPC take them into effect. Commit message
update. (Sagar)
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_slpc.c | 104 ++
drivers/gp
From: Tom O'Rourke
If slpc enabled, then add enable SLPC flag to guc
control parameter during guc load.
v1: Use intel_slpc_enabled() (Paulo)
v2-v4: Rebase.
v5: Changed intel_slpc_enabled() to i915.enable_slpc. (Sagar)
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar A
This tests whether SLPC in GuC is configured properly through shared data.
It checks whether GTPERF is running in default state, post reset and post
system suspend/resume.
This test will be extended further based on enablement of other SLPC tasks.
Signed-off-by: Sagar Arun Kamble
---
lib
earlier in
driver load for handling uncore sanitization properly.
Testcase: igt/pm_slpc
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.c| 9 +
drivers/gpu/drm/i915/i915_params.c | 4 ++--
2 files changed, 11 insertions(+), 2 del
: If89518708e133be6b3c7c6f90869fb66224b7b87
Reviewed-by: Imre Deak
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_gem_gtt.h| 2 ++
drivers/gpu/drm/i915/i915_gem_stolen.c | 3 ++
drivers/gpu/drm/i915/i915_reg.h| 11 +++
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c
The RC6 residency time unit is 1.33us on SKL according to the
specification, so update the calculation accordingly.
Cc: Imre Deak
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_sysfs.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915
functional issue where
RC6 ctx size check was missing. (Imre)
Cc: Imre Deak
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_gem_gtt.h| 2 ++
drivers/gpu/drm/i915/i915_gem_stolen.c | 3 ++
drivers/gpu/drm/i915/i915_reg.h| 11 +++
drivers/gpu/drm/i915
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_sysfs.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index c6188dd..bb2fd78 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm
: Added elaborate commit message. (Jani)
Fixing RPM reference drop in early exit paths. (Ville)
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_sysfs.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915
Since wake count is released asynchronously, *drpc_info output indicates
blitter wake count to be 1. Print these wake counts before reading
registers in *drpc_info.
Acked-by: Chris Wilson
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_debugfs.c | 8 ++--
1 file changed, 6
dfps and turbo merged and renamed "gtperf"
ibc split out and renamed "balancer"
Avoid magic numbers (Jon Bloomfield)
v2-v3: Rebase.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_debugfs.c | 252
bugfs interfaces.
A later patch in this series updates sysfs/debugfs
interfaces for setting max/min frequencies with SLPC.
v1: Use intel_slpc_active instead of HAS_SLPC (Paulo)
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_pm.c | 3 +++
1 file
This will help avoid Host to GuC actions being called till GuC gets
loaded during i915_drm_resume.
v2-v3: Rebase.
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm
From: Tom O'Rourke
Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.
v1: Update for SLPC 2015.2.4 (params for both slice and unslice)
Replace HAS_SLPC with intel_slpc_active() (Paulo)
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar A
firmware for better readability. If needed, other SLPC interfaces
for different GuC version will be added later. Incorporated change related
slice suggested by Dave. (rebase miss).
VIZ-6773, VIZ-6889, VIZ-6890
Cc: Chris Wilson
Cc: Daniel Vetter
Cc: Beuchat, Marc
Cc: Jeff McGee
Cc: Paulo Zanoni
te cur_freq as it is driver internal request. (Chris)
v3: Removing sysfs interface gt_req_freq_mhz out of this patch
for proper division of functionality. (Sagar)
v4: idle_freq, boost_freq are also not used with SLPC.
Signed-off-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
ff-by: Tom O'Rourke
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_guc_submission.c | 16
drivers/gpu/drm/i915/intel_guc.h | 2 ++
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gp
v2: Removing checks for vma obj and kmap_atomic validity. (Chris)
v3: Rebase.
v4: Updated to make sure SLPC enable keeps min/max freq softlimits
unchanged after initializing once. (Chris)
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_slpc.c | 47
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