[Intel-gfx] [PATCH 0/2] Sanitycheck PCI BARs

2022-07-25 Thread Piorkowski, Piotr
From: Piotr Piórkowski When initializing the i915, we want to be sure that the PCI BARs have been properly initialized. As part of this series, I have prepared two patches, one that introduces BARs names to use in code instead of numbers, and another that adds function to validate BARs before use

[Intel-gfx] [PATCH 1/2] drm/i915: Use of BARs names instead of numbers

2022-07-25 Thread Piorkowski, Piotr
From: Piotr Piórkowski At the moment, when we refer to some PCI BAR we use the number of this BAR in the code. The meaning of BARs between different platforms may be different. Therefore, in order to organize the code, let's start using defined names instead of numbers. Signed-off-by: Piotr Piór

[Intel-gfx] [PATCH 2/2] drm/i915: Sanitycheck PCI BARs

2022-07-25 Thread Piorkowski, Piotr
From: Piotr Piórkowski For proper operation of i915 we need usable PCI GTTMMADDR BAR 0 (1 for GEN2). In most cases we also need usable PCI GFXMEM BAR 2. Let's add functions to check if BARs are set, and that it have a size greater than 0. In case GTTMMADDR BAR, let's validate at the beginning of

[Intel-gfx] [PATCH v2 0/2] Sanitycheck PCI BARs

2022-08-03 Thread Piorkowski, Piotr
From: Piotr Piórkowski When initializing the i915, we want to be sure that the PCI BARs have been properly initialized. As part of this series, I have prepared two patches, one that introduces BARs names to use in code instead of numbers, and another that adds function to validate BARs before use

[Intel-gfx] [PATCH v2 1/2] drm/i915: Use of BARs names instead of numbers

2022-08-03 Thread Piorkowski, Piotr
From: Piotr Piórkowski At the moment, when we refer to some PCI BAR we use the number of this BAR in the code. The meaning of BARs between different platforms may be different. Therefore, in order to organize the code, let's start using defined names instead of numbers. v2: Add lost header in cf

[Intel-gfx] [PATCH v2 2/2] drm/i915: Sanitycheck PCI BARs

2022-08-03 Thread Piorkowski, Piotr
From: Piotr Piórkowski For proper operation of i915 we need usable PCI GTTMMADDR BAR 0 (1 for GEN2). In most cases we also need usable PCI GFXMEM BAR 2. Let's add functions to check if BARs are set, and that it have a size greater than 0. In case GTTMMADDR BAR, let's validate at the beginning of

[Intel-gfx] [PATCH v3 1/2] drm/i915: Use of BARs names instead of numbers

2022-08-05 Thread Piorkowski, Piotr
From: Piotr Piórkowski At the moment, when we refer to some PCI BAR we use the number of this BAR in the code. The meaning of BARs between different platforms may be different. Therefore, in order to organize the code, let's start using defined names instead of numbers. v2: Add lost header in cf

[Intel-gfx] [PATCH v3 0/2] Sanitycheck PCI BARs

2022-08-05 Thread Piorkowski, Piotr
From: Piotr Piórkowski When initializing the i915, we want to be sure that the PCI BARs have been properly initialized. As part of this series, I have prepared two patches, one that introduces BARs names to use in code instead of numbers, and another that adds function to validate BARs before use

[Intel-gfx] [PATCH v3 2/2] drm/i915: Sanitycheck PCI BARs

2022-08-05 Thread Piorkowski, Piotr
From: Piotr Piórkowski For proper operation of i915 we need usable PCI GTTMMADDR BAR 0 (1 for GEN2). In most cases we also need usable PCI GFXMEM BAR 2. Let's add functions to check if BARs are set, and that it have a size greater than 0. In case GTTMMADDR BAR, let's validate at the beginning of

[Intel-gfx] [PATCH] drm/i915: Sanitycheck PCI BARs on probe

2022-01-20 Thread Piorkowski, Piotr
From: Piotr Piórkowski For proper operation of i915 we need usable PCI BARs: - GTTMMADDR BAR 0 (1 for GEN2) - GFXMEM BAR 2. Lets check before we start the i915 probe that these BARs are set, and that they have a size greater than 0. Signed-off-by: Piotr Piórkowski Cc: Michal Wajdeczko Cc: Ja

[Intel-gfx] [PATCH] drm/i915: Verify dma_addr in gen8_ggtt_pte_encode

2021-02-24 Thread Piorkowski, Piotr
From: Piotr Piórkowski Until now, the gen8_ggtt_pte_encode function, responsible for the preparation of GGTT PTE, has not verified in any way whether the address given as the parameter is correct. By adding a GGTT address mask, we can easily verify that dma_addr will not fit in the PTE field. Whi

Re: [Intel-gfx] [PATCH v2] drm/i915/guc: Remove GUC_CTL_DEVICE_INFO parameter

2018-04-13 Thread Piorkowski, Piotr
On Tue, 2018-03-06 at 10:07 +0530, Sagar Arun Kamble wrote: > > On 3/5/2018 6:43 PM, Piotr Piórkowski wrote: > > It looks that GuC does not actively use GUC_CTL_DEVICE_INFO > > parameter > > where we are passing GT type and Core family values. > > Lets stop setup this parameter and remove related

Re: [Intel-gfx] [PATCH 7/7] drm/i915/guc: Add support for define guc_log_size in megabytes.

2018-06-04 Thread Piorkowski, Piotr
On Wed, 2018-05-30 at 18:46 +0200, Michal Wajdeczko wrote: > On Wed, 30 May 2018 15:53:34 +0200, Piotr Piorkowski > wrote: > > > At this moment we can define GuC logs sizes only using pages. > > But GuC also allows use for this values expressed in megabytes. > > Lets add support for define guc_

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/7] drm/i915/guc: Don't store runtime GuC log level in modparam (rev3)

2018-06-12 Thread Piorkowski, Piotr
On Tue, 2018-06-05 at 21:56 +, Patchwork wrote: > == Series Details == > > Series: series starting with [v2,1/7] drm/i915/guc: Don't store > runtime GuC log level in modparam (rev3) > URL : https://patchwork.freedesktop.org/series/44201/ > State : failure > > == Summary == > > = CI Bug Log

Re: [Intel-gfx] [PATCH] drm/i915/guc: Removed unused GuC parameters.

2018-03-05 Thread Piorkowski, Piotr
On Fri, 2018-03-02 at 12:53 +0530, Sagar Arun Kamble wrote: > > On 3/2/2018 12:44 AM, John Spotswood wrote: > > On Thu, 2018-03-01 at 17:35 +0530, Sagar Arun Kamble wrote: > > > On 3/1/2018 1:32 PM, Chris Wilson wrote: > > > > Quoting Michel Thierry (2018-02-28 22:07:51) > > > > > On 28/02/18 12:2