Kahola
Cc: Paulo Zanoni
Cc: Dhinakaran Pandiyan
Signed-off-by: Manasi Navare
Signed-off-by: Lucas De Marchi
[Paulo: implement v2]
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 3 ++
drivers/gpu/drm/i915/intel_ddi.c | 26 +
drivers/gpu/drm/i915
From: Manasi Navare
For ICL, on Combo PHY the allowed max rates are:
- HBR3 8.1 eDP (DDIA)
- HBR2 5.4 DisplayPort (DDIB)
and for MG PHY/TC DDI Ports allowed DP rates are:
- HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
- DP on legacy connector - DDIC/D/E/F)
Cc: Rodrigo Vivi
Cc: Jani
From: Mahesh Kumar
ICP has GPIO pin 1/2 mapped to combo-phy ports & GPIO pins 9/10/11/12
mapped to tc ports[1-4].
This patch defines GPIOCTL registers for GPIO pins 9-12 & uses them in GPIO
pin mapping table.
Cc: Anusha Srivatsa
Cc: Madhav Chauhan
Cc: Lucas De Marchi
Signed-off-by: Mahesh Kum
From: Manasi Navare
DP spec 1.4 supports training pattern set 4 (TPS4) for HBR3 link
rate. This will be used in link training's channel equalization
phase if supported by both source and sink.
This patch adds the helpers to check if HBR3 is supported and uses
TPS4 in training pattern selection du
by DDI ports")
Cc: Ville Syrjälä
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_cdclk.c | 46 +++---
drivers/gpu/drm/i915/intel_ddi.c | 2 ++
2 files changed, 45 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
Some bits from the flags2 field are going to be used in the next
patches, so replace the whole-byte definition with the actual bits and
document their versions.
This patch is based on a patch by Animesh Manna.
Cc: Animesh Manna
Credits-to: Animesh Manna
Signed-off-by: Paulo Zanoni
From: James Ausmus
Add support for DP_AUX_E. Here we also introduce the bits for the AUX
power well E, however ICL power well support is still not enabled yet,
so the power well is not used.
Cc: Paulo Zanoni
Cc: Rodrigo Vivi
Cc: Dhinakaran Pandiyan
Signed-off-by: James Ausmus
Signed-off-by
Em Qui, 2018-05-24 às 16:42 -0700, Paulo Zanoni escreveu:
> From: James Ausmus
>
> Add support for DP_AUX_E. Here we also introduce the bits for the AUX
> power well E, however ICL power well support is still not enabled
> yet,
> so the power well is not used.
>
>
Em Seg, 2018-05-21 às 17:25 -0700, Paulo Zanoni escreveu:
> From: Manasi Navare
>
> DFLEXDPMLE register is required to tell the FIA hardware which
> main links of DP are enabled on TCC Connectors. FIA uses this
> information to program PHY to Controller signal mapping.
>
Em Seg, 2018-05-21 às 17:25 -0700, Paulo Zanoni escreveu:
> From: Anusha Srivatsa
>
> This patch adds the support to detect PCH_ICP.
>
> Suggested-by: Paulo Zanoni
Reviewed-by: Paulo Zanoni
> Signed-off-by: Anusha Srivatsa
> Signed-off-by: Michel Thierry
> ---
Em Seg, 2018-05-21 às 17:25 -0700, Paulo Zanoni escreveu:
> From: Arkadiusz Hiler
>
> Start using the new registers for ICL and on.
I previously put this patch in a series that did not make use of
cnl_calc_wrpll_link() for ICL yet. This series makes ICL run
cnl_calc_wrpll_link(), so t
Em Seg, 2018-05-07 às 11:46 +0300, Joonas Lahtinen escreveu:
> Ingo, do you prefer to merge through our tree with your ack?
Ping?
>
> Quoting Paulo Zanoni (2018-05-04 23:32:51)
> > ICL changes the registers and addresses to 64 bits.
> >
> > I also briefly looked at
Em Sex, 2018-05-25 às 09:26 -0700, Lucas De Marchi escreveu:
> On Mon, May 21, 2018 at 05:25:41PM -0700, Paulo Zanoni wrote:
> > From: Manasi Navare
> >
> > This patch adds a proper HDMI DDI entry level for vswing
> > programming sequences on ICL.
> >
> &g
Em Seg, 2018-05-21 às 17:25 -0700, Paulo Zanoni escreveu:
> Hi
>
> This series contains some more ICL patches that haven't seen the
> mailing list yet. While I'll definitely help re-review the patches
> not
> authored by me, please help me with the ones I can't
Em Sex, 2018-05-25 às 08:52 -0700, Lucas De Marchi escreveu:
> From: Mahesh Kumar
>
> All connectors may not have best_encoder attached, so don't
> dereference
> encoder pointer for each connector.
>
> Fixes: c27e917e2bda (drm/i915/icl: add basic support for the ICL
> clocks)
> Signed-off-by: Ma
Em Sex, 2018-05-25 às 11:32 -0700, James Ausmus escreveu:
> On Thu, May 24, 2018 at 04:42:37PM -0700, Paulo Zanoni wrote:
> > From: Manasi Navare
> >
> > For ICL, on Combo PHY the allowed max rates are:
> > - HBR3 8.1 eDP (DDIA)
> > - HBR2 5.4 DisplayPort (DDIB
ixes: aa9664ffe863 ("drm/i915/icl: Enable 2nd DBuf slice only when
> needed")
> Signed-off-by: Mahesh Kumar
Reviewed-by: Paulo Zanoni
I'll merge it.
> ---
> drivers/gpu/drm/i915/intel_pm.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/d
While things may have been different before, right now the function is
very simple and has a single caller. IMHO any possible benefits from
an abstraction here are gone and not worth the price of the current
indirection while reading the code.
Cc: Mahesh Kumar
Signed-off-by: Paulo Zanoni
From: Manasi Navare
DP spec 1.4 supports training pattern set 4 (TPS4) for HBR3 link
rate. This will be used in link training's channel equalization
phase if supported by both source and sink.
This patch adds the helpers to check if HBR3 is supported and uses
TPS4 in training pattern selection du
: Jani Nikula
Reviewed-by: James Ausmus
Signed-off-by: Manasi Navare
Signed-off-by: James Ausmus
[Paulo: bikeshed to keep future platforms on "else".]
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_dp.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletion
Em Qui, 2018-05-24 às 17:12 -0700, Paulo Zanoni escreveu:
> Em Qui, 2018-05-24 às 16:42 -0700, Paulo Zanoni escreveu:
> > From: James Ausmus
> >
> > Add support for DP_AUX_E. Here we also introduce the bits for the
> > AUX
> > power well E, however ICL power
Em Seg, 2018-06-11 às 22:35 +, Patchwork escreveu:
> == Series Details ==
>
> Series: series starting with [CI,1/2] drm/i915/icl: Add allowed DP
> rates for Icelake
> URL : https://patchwork.freedesktop.org/series/44595/
> State : warning
>
> == Summary ==
>
> $ dim checkpatch origin/drm-t
From: Mahesh Kumar
ICP has GPIO pin 1/2 mapped to combo-phy ports & GPIO pins 9/10/11/12
mapped to tc ports[1-4].
This patch defines GPIOCTL registers for GPIO pins 9-12 & uses them in GPIO
pin mapping table.
Cc: Anusha Srivatsa
Cc: Madhav Chauhan
Cc: Lucas De Marchi
Reviewed-by: Lucas De Mar
From: James Ausmus
Add support for DP_AUX_E. Here we also introduce the bits for the AUX
power well E, however ICL power well support is still not enabled yet,
so the power well is not used.
Cc: Rodrigo Vivi
Cc: Dhinakaran Pandiyan
Reviewed-by: Paulo Zanoni
Signed-off-by: James Ausmus
eps
appearing on the mailing list.
Thanks,
Paulo
Paulo Zanoni (3):
drm/i915/i915_reg.h: fix the checkpatch SPACING issues
drm/i915/i915_reg.h: fix the checkpatch SPACE_BEFORE_TAB issues
drm/i915/i915_reg.h: fix the checkpatch MACRO_ARG_PRECEDENCE issues
drivers/gpu/drm/i9
Since I'm touching the file I might as well fix this class of errors
since they are just a few. Also drive-by fix the styling of the
VLV_TURBO_SOC_OVERRIDE definitions instead of just the spaces before
the tabs.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h
While I don't see any issue with the way these macros are being called
today, let's protect them against operator precedence issues before
they happen.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 42 -
1 file changed, 21
Em Qua, 2018-06-13 às 11:07 +0300, Jani Nikula escreveu:
> On Tue, 12 Jun 2018, Rodrigo Vivi wrote:
> > Do we really want BIT everywhere?!
>
> I think I'd go for everywhere except part of a register field value:
>
While I completely agree with your reasoning, this means we'll kinda
always want
Em Ter, 2018-06-12 às 11:37 -0700, Manasi Navare escreveu:
> On Tue, Jun 12, 2018 at 03:15:53PM +0300, Ville Syrjälä wrote:
> > On Mon, Jun 11, 2018 at 03:26:54PM -0700, Paulo Zanoni wrote:
> > > From: Manasi Navare
> > >
> > > For ICL, on Combo PHY the allo
Em Qua, 2018-06-13 às 13:15 -0700, Manasi Navare escreveu:
> On Wed, Jun 13, 2018 at 12:42:20PM -0700, Paulo Zanoni wrote:
> > Em Ter, 2018-06-12 às 11:37 -0700, Manasi Navare escreveu:
> > > On Tue, Jun 12, 2018 at 03:15:53PM +0300, Ville Syrjälä wrote:
> > > > On M
Em Sex, 2018-06-08 às 13:19 -0700, Srivatsa, Anusha escreveu:
> > -Original Message-
> > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On
> > Behalf Of
> > Paulo Zanoni
> > Sent: Monday, May 21, 2018 5:26 PM
> > To: intel-gfx@lists.fre
Use the hardcoded tables provided by our spec.
v2:
- SSC stays disabled.
- Use intel_port_is_tc().
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915
Em Qua, 2018-06-13 às 16:34 -0700, Lucas De Marchi escreveu:
> On Mon, May 21, 2018 at 05:25:47PM -0700, Paulo Zanoni wrote:
> > On ICP, port present straps are no longer supported. Software
> > should
>
> ICP?? Doesn't it make more sense to say on ICL here?
The regi
Em Qua, 2018-06-13 às 16:15 -0700, Lucas De Marchi escreveu:
> On Mon, May 21, 2018 at 05:25:44PM -0700, Paulo Zanoni wrote:
> > Implement the hardware state readout code.
> >
> > Thanks to Animesh Manna for spotting this problem.
> >
> > Cc: Animesh Man
wrote:
> > > > On Thu, 2018-05-24 at 16:53 -0700, Lucas De Marchi wrote:
> > > > > On Mon, May 21, 2018 at 05:25:39PM -0700, Paulo Zanoni wrote:
> > > > > >
> > > > > > From: Anusha Srivatsa
> > > > > >
> > >
Em Qui, 2018-06-14 às 12:07 -0700, Rodrigo Vivi escreveu:
> On Thu, May 24, 2018 at 04:42:36PM -0700, Paulo Zanoni wrote:
> > From: Mahesh Kumar
> >
> > ICP has GPIO pin 1/2 mapped to combo-phy ports & GPIO pins
> > 9/10/11/12
> > mapped to tc ports[1-4].
>
by DDI ports")
Cc: Ville Syrjälä
Reviewed-by: Rodrigo Vivi
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_cdclk.c | 46 +++---
drivers/gpu/drm/i915/intel_ddi.c | 2 ++
2 files changed, 45 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/dr
: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_vbt_defs.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h
b/drivers/gpu/drm/i915/intel_vbt_defs.h
index c132d0c3a500..c614c9f3f28b 100644
--- a/drivers/gpu/drm/i915/intel_vbt_defs.h
+++ b
Em Sex, 2018-06-15 às 15:51 +0530, Madhav Chauhan escreveu:
> Escape Clock is used for LP communication across the DSI
> Link. To achieve the constant frequency of the escape clock
> from the variable DPLL frequency output, a variable divider(M)
> is needed. This patch programs the same.
>
> Signe
Em Sex, 2018-06-15 às 23:30 +0530, Chauhan, Madhav escreveu:
> > -Original Message-
> > From: Zanoni, Paulo R
> > Sent: Friday, June 15, 2018 11:00 PM
> > To: Chauhan, Madhav ; intel-
> > g...@lists.freedesktop.org
> > Cc: Nikula, Jani ; Shankar, Uma
> > ; Vivi, Rodrigo
> > Subject: Re: [P
ion doesn't even say "max" and the other similar
parts of the code such as buffer max width/height don't use
definitions.
Reviewed-by: Paulo Zanoni
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_display.c | 8
> drivers/gpu/dr
. Which may
> be larger than the max hdisplay/vdisplay.
Verified against the specs. I can also confirm that the gen2+ specs
still exist at the old URLs :).
Reviewed-by: Paulo Zanoni
While at it, can't you try to implement the other restrictions listed
in those active/sync registers? Like hdi
y > 4096 ||
> + adjusted_mode->crtc_hblank_start > 4096)
> + return false;
Meh, doubling checks is not cool.
By the way, doesn't this chunk make more sense inside
ironlake_fdi_compute_config()?
Just to make sure: the only cases that could escape mode_valid
errupt (Chris)
Looks like all the requests have been implemented:
Reviewed-by: Paulo Zanoni
>
> Cc: Chris Wilson
> Cc: Mika Kuoppala
> Signed-off-by: Dhinakaran Pandiyan
> [Paulo: bikesheds and rebases]
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/i915_i
Em Qua, 2018-06-13 às 15:20 -0700, Lucas De Marchi escreveu:
> +Chris
>
> On Mon, May 21, 2018 at 05:25:38PM -0700, Paulo Zanoni wrote:
> > From: Dhinakaran Pandiyan
> >
> > The hotplug interrupts for the ports can be routed to either North
> > Display or Sout
South
Display in PCH. This patch adds hotplug interrupt handling support for
DP Alternate mode.
Cc: Jani Nikula
Cc: Anusha Srivatsa
Reviewed-by: Paulo Zanoni
Signed-off-by: Dhinakaran Pandiyan
[Paulo: coding style changes]
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 95
From: Dhinakaran Pandiyan
This patch enables hotplug interrupts for DP over TBT output on TC
ports. The TBT interrupts are enabled and handled irrespective of the
actual output type which could be DP Alternate, DP over TBT, native DP
or native HDMI.
Cc: Animesh Manna
Cc: Paulo Zanoni
Cc
ts to Paulo for pointing out
the register change.
v2: from DK
raw_reg_[read/write], branch prediction hint and drop platform check (Mika)
v3: From DK
Early re-enable of master interrupt (Chris)
Cc: Chris Wilson
Cc: Mika Kuoppala
Reviewed-by: Paulo Zanoni
Signed-off-by: Dhinakaran Pandiyan
[
Em Ter, 2018-06-19 às 15:28 -0700, Lucas De Marchi escreveu:
> On Mon, May 21, 2018 at 05:25:52PM -0700, Paulo Zanoni wrote:
> > Do like the other functions and check for the ISR bits. We have
> > plans
> > to add a few more checks in this code in the next patches, that's
Em Qui, 2018-06-14 às 12:59 -0700, Rodrigo Vivi escreveu:
> On Mon, May 21, 2018 at 05:25:53PM -0700, Paulo Zanoni wrote:
> > The type is detected based on the interrupt ISR bit. Once detected,
> > it's not supposed to be changed, so we have some sanity checks for
> >
handler().
>
> v2:
> - remove redundant register defines.(Lucas)
> - Change register names to be more consistent with
> previous platforms (Lucas)
>
> Cc: Lucas De Marchi
> Cc: Paulo Zanoni
> Cc: Dhinakaran Pandiyan
> Cc: Ville Syrjala
> Signed-off-by: Anusha Sri
rgo taking the separate power ref for PSR
> > functionality.
> >
> > v2:
> > - Make sure DC states stay enabled when taking the ref on port A.
> > (Ville)
> >
> > v3: (Ville)
> > - Fix comment about logic for encoders without a crtc state and
> &g
Introduce these registers and their intended values.
> >
> > Introduce icp_irq_handler().
> >
> > v2:
> > - remove redundant register defines.(Lucas)
> > - Change register names to be more consistent with
> > previous platforms (Lucas)
> >
> > Cc: Luc
mments. Confirm in the commit message that
> icp_irq_postinstall() need not go to
> ibx_irq_pre_postinstall() and ibx_irq_postinstall()
> as in earlier platforms. (Paulo)
>
> Cc: Lucas De Marchi
> Cc: Paulo Zanoni
> Cc: Dhinakaran Pandiyan
> Cc: Ville Syrjala
> Si
(Chris)
Cc: Chris Wilson
Reviewed-by: Daniel Vetter
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/i915_gem.c | 14 +++---
2 files changed, 17 insertions(+), 3 deletions(-)
Chris, can you give your Signed-off-by on this patch, please
perly on this machine, IMHO it's better if we minimize the
amount of possible problems by just giving up FBC whenever we detect
an underrun.
v2: new version, different implementation and commit message.
Cc: Stefan Richter
Cc: Lyude
Cc: Steven Honeyman
Signed-off-by: Paulo Zanoni
---
drive
(Chris)
v3 (from Paulo):
- Remove huge comment since now we have WRITE_ONCE (Chris)
- Remove uneeded new line (Chris)
- Add Chris' Signed-off-by, authorized via IRC
Cc: Chris Wilson
Reviewed-by: Daniel Vetter
Signed-off-by: Chris Wilson
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm
dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
> dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
> --
> 1.8.5.5
>
> _______
> Intel-gfx mailing list
> Intel-gfx@lists.freedeskto
deep PC states
anyway.
v2: Rebase after changing the patch order.
v3:
- Remove references to the stride change case being "uncommon" and
paste Chris' example.
- Rebase after a change in a previous patch.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_fbc.c | 1
2015-11-19 18:06 GMT-02:00 Ville Syrjälä :
> On Thu, Nov 19, 2015 at 05:44:51PM -0200, Paulo Zanoni wrote:
>> 2014-05-26 11:26 GMT-03:00 :
>> > From: Ville Syrjälä
>> >
>> > Now that the vblank races are plugged, we can opt out of using
>> >
iend when comparing results.
Signed-off-by: Paulo Zanoni
---
tools/.gitignore| 1 +
tools/Makefile.sources | 1 +
tools/intel_residency.c | 700
3 files changed, 702 insertions(+)
create mode 100644 tools/intel_residency.c
diff --g
ces-equal on my snb.
The main question here is: why did this work reliably before?
>
> Cc: Paulo Zanoni
> Signed-off-by: Daniel Vetter
> ---
> tests/pm_rpm.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/tests/pm_rpm.c b/tests/pm_rpm.c
> index 37aef96ed267..
2015-12-01 14:47 GMT-02:00 Daniel Vetter :
> On Tue, Dec 01, 2015 at 02:40:22PM -0200, Paulo Zanoni wrote:
>> 2015-12-01 14:37 GMT-02:00 Daniel Vetter :
>> > The kernel is free to allocate blob ids however it wants to. And also
>> > to reallocate them whenever it sees
Unified idle_frame definition.
Reducing from 4 different possibilities to 2 is good.
Reviewed-by: Paulo Zanoni
>
> Cc: Paulo Zanoni
> Signed-off-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_psr.c | 20 +++-
> 1 file changed, 7 insertions(+), 13 deleti
ol intel_crt_present(struct drm_device *dev)
> if (IS_CHERRYVIEW(dev))
> return false;
>
> + if (HAS_PCH_LPT(dev) && I915_READ(SFUSE_STRAP) &
> SFUSE_STRAP_CRT_DISABLED)
Bonus points if you use your new HAS_PCH_LPT_H() here.
With o
2015-12-01 11:08 GMT-02:00 :
> From: Ville Syrjälä
Subject: s/connectro/connector/
>
> On HSW/BDW DDI A and E share 2 lanes, so when DDI A requires the
> shared lanes DDI E can't be used. The lanes are not suppsoed to
s/suppsoed/supposed/
Reviewed-by: Paulo Zanoni
> be
>
> v2: Move the platform checks into the VBT parsing code
> Also check that the VBT version is at least 155
You could also add that HAS_DDI platforms are already believing the
VBT for versions >= 155: see intel_ddi_init(), so we have a precedent.
(by the way, I'm trusting you
at
the default case, such as the one we have in bxt_get_ddi_pll()?
Reviewed-by: Paulo Zanoni
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_display.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/
Hi
This series includes the implementation for the review feedback given by Chris.
I also removed the patch that transformed our 50ms timeout into a vblank-based
timeout due to performance concerns. The only patch that still needs review is
patch 6.
Thanks,
Paulo
Paulo Zanoni (11):
drm/i915
deep PC states
anyway.
v2: Rebase after changing the patch order.
v3:
- Remove references to the stride change case being "uncommon" and
paste Chris' example.
- Rebase after a change in a previous patch.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_fbc.c | 1
ter.
v2: Use drm_mm_node_allocated() (Chris).
Reviewed-by: Chris Wilson
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_fbc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 11fc528.
ts the very basic code on enable() and
disable(). The next commits will take care of moving more stuff from
update() to the new functions.
v2:
- Rebase.
- Improve commit message (Chris).
v3: Rebase after changing the patch order.
v4: Rebase again after upstream changes.
Reviewed-by: Chr
p track
of the previously selected CRTC when we do invalidate/flush. We're
also going to continue the enable/disable/activate/deactivate concept
in the next patches.
v2: Rebase.
v3: Rebase after changing the patch order.
Reviewed-by: Chris Wilson
Signed-off-by: Paulo Zanoni
---
drive
g fixes.
- Rebase after changing the patch order.
- Fix ms/jiffies confusion.
Reviewed-by: Chris Wilson (v1)
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++-
drivers/gpu/drm/i915/intel_fbc.c | 107 ++-
2 files changed, 52 insert
anging the patch order.
Reviwed-by: Chris Wilson
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_fbc.c | 15 ---
1 file changed, 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 0ad9585..af621de 100644
--- a/drivers/gp
atch order changes.
v4: Rewrite commit message (Chris).
Reviewed-by: Chris Wilson
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_fbc.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
ind
patch order.
Reviewed-by: Chris Wilson
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/intel_fbc.c | 22 +-
2 files changed, 9 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_d
This patch by itself has no benefits other than
making review and rebase easier. Please see the next patches for more
details on the conversion.
v2:
- Rebase.
- Improve commit message (Chris).
v3: Rebase after changing the patch order.
Reviewed-by: Chris Wilson
Signed-off-by: Paulo Z
Directly call intel_fbc_calculate_cfb_size() in the only place that
actually needs it, and use the proper check before removing the stolen
node. IMHO, this change makes our code easier to understand.
v2: Use drm_mm_node_allocated() (Chris).
Reviewed-by: Chris Wilson
Signed-off-by: Paulo Zanoni
This moves the pre-gen4 check from update() to enable(). The HAS_DDI
in the original code is not needed since only gen 2/3 have the plane
swapping code.
v2: Rebase.
v3: Extract fbc_on_plane_a_only() (Chris).
Reviewed-by: Chris Wilson
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915
buffers.
I also need to export the size computation function so I won't need to
reimplement it inside kms_frontbuffer_tracking.
The tiling size checking code is based on the Kernel's
intel_tile_height() and i915_tiling_ok().
Requested-by: Daniel Vetter
Cc: Daniel Vetter
Signed-off-by: Pa
checks for buffer sizes.
v2: Use the new igt_calc_fb_size() instead of implementing our own
size calculation (Daniel).
Signed-off-by: Paulo Zanoni
---
tests/kms_frontbuffer_tracking.c | 51 ++--
1 file changed, 34 insertions(+), 17 deletions(-)
diff --g
lpt_init_pch_refclk(struct drm_device
> *dev)
> }
> }
>
> - if (has_vga)
> + if (has_vga) {
> + lpt_bend_clkout_dp(to_i915(dev), 0);
> lpt_enable_clkout_dp(dev, true, true);
> - else
> + } else {
> lpt_disable_clkout_dp(dev);
> + }
> }
>
> /*
> --
> 2.4.10
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Paulo Zanoni
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
2015-12-01 11:08 GMT-02:00 :
> From: Ville Syrjälä
>
> Bspec says we should round to closest when computong the LPT-H VGA
s/computong/computing/
Reviewed-by: Paulo Zanoni
> dotclock, so let's do that.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i91
e(struct intel_crtc *crtc)
> --
> 2.4.10
>
> _______
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Paulo Zanoni
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
l_disp_power_wells {
> /* LPT PIXCLK_GATE */
> #define PIXCLK_GATE_MMIO(0xC6020)
> #define PIXCLK_GATE_UNGATE(1<<0)
> -#define PIXCLK_GATE_GATE (0<<0)
I actually liked the #define...
Reviewed-by: Paulo Zanoni
>
> /* SP
2015-12-01 11:08 GMT-02:00 :
> From: Ville Syrjälä
>
> Currently we leave the LPT-H VGA dotclock running after turning
> the pipe/fdi/port/etc. Propoerly disable the VGA dotclock as
s/Propoerly/Properly/
(DId you also notice that steps 13 and 18 are the same?)
Reviewed-by:
t code. So instead just leave FDI
> up and running in its untrained state, and log an error. This is
> what we do on older platforms too.
Reviewed-by: Paulo Zanoni
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 24 +++-
> 1 file
2015-12-03 8:03 GMT-02:00 Ville Syrjälä :
> On Wed, Dec 02, 2015 at 11:35:00AM -0200, Paulo Zanoni wrote:
>> 2015-12-01 11:08 GMT-02:00 :
>> > From: Ville Syrjälä
>> >
>> > When we want to use SPLL for FDI we want SSC, which means we have to
>> > di
2015-12-03 14:39 GMT-02:00 Rodrigo Vivi :
> Unfortunately Sink CRC is not 100% reliable for all platforms.
> So we cannot block FBC tests nor skip them when we are getting
> unreliable Sink CRC results, or not getting them at all.
>
> Cc: Paulo Zanoni
> Signed-off-by: Rodrigo Vi
e idea you're implementing is what we want, then
the patch looks correct and Acked-by: Paulo Zanoni
.
My problem is the whole idea of "silently" skipping the tests in case
the sink CRC fails. What if QA's only machines always have this
problem with sink CRCs and always skip ev
Because just running dim help doesn't give you the greater picture of
the workflow. All the text here is based on an email written by Daniel
Vetter, so the credits go to him. Any mistakes were introduced by me.
Credits-to: Daniel Vetter
Signed-off-by: Paulo Zanoni
---
dim.rst
es: true
With quotes: false
In addition, print a little message telling us that the message-ids
are missing. This may help by reminding us that we should apply the
mail file, not the original patch. I'm not enforcing it since I don't
know all our use cases.
Cc: Jani Nikula
Signed-off-b
2015-12-03 17:44 GMT-02:00 Vivi, Rodrigo :
> On Thu, 2015-12-03 at 15:05 -0200, Paulo Zanoni wrote:
>> 2015-12-03 14:39 GMT-02:00 Rodrigo Vivi :
>> > Even with all sink crc re-works we still have platforms
>> > where after 6 vblanks it is unable to calculate the
>>
sanity check (Paulo)
> Fix typos in commit message (Paulo)
>
> Cc: Paulo Zanoni
Reviewed-by: Paulo Zanoni
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_display.c | 67
> +++
ge with more details (Paulo)
Since I seem to recall that the DDI disable sequence for CRT was
correct at some point in a distant past, I suppose your commit is a
regression fix, and maybe we'd like a backportable version. Maybe we
could also provide explicit information on the first bad co
you choose exactly this value?
Thanks,
Paulo
> }
>
> if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
> --
> 1.9.1
>
> _______
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/
c
>> create mode 100644 lib/pm_workarounds.h
>>
>> --
>> 2.6.2
>>
>> ___
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
&g
bigger usleep range so kernel doesn't need to be interrupted
> on a exact time, as suggested by Paulo.
> But anyway we should discuss the better time
> ranges on the EBUSY handle re-org at drm level since this one here
> is temporary.
>
> Cc: Paulo Zanoni
>
R_MIN_LINK_ENTRY_TIME_8_LINES;
It's kinda weird that we used the variable "val" for nothing. At least
we're using it now :).
Reviewed-by: Paulo Zanoni
>
> I915_WRITE(EDP_PSR_CTL, val |
> - (IS_BROADWELL(dev) ? 0 :
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