allocate an array of i915_power_well objects in i915 dev_priv,
> and link to each of these objects their corresponding
> i915_power_well_desc object.
>
> Cc: Ville Syrjala
> Cc: Paulo Zanoni
> Cc: Jani Nikula
> Signed-off-by: Imre Deak
Quite a few issues pointed by checkp
#x27;t we also move .ops
down when relevant, and keep the ordering "perfect" for every member?
Anyway, the patch does what it says, so with or without the new color:
Reviewed-by: Paulo Zanoni
>
> Cc: Ville Syrjala
> Cc: Paulo Zanoni
> Cc: Jani Nikula
> Signed-of
al machines before
submitting or are we entirely relying on the CI results?
I'm not sure the CI is running enough tests to validate this patch with
confidence, we'll probably need to do some manual testing here.
>
> Cc: Imre Deak
> Cc: Rodrigo Vivi
> Cc: Paulo
trol registers.
>
> This also fixes a problem on ICL, where we incorrectly read the KVMR
> control register in hsw_power_well_requesters() even for DDI and AUX
> power wells.
>
> Cc: Ville Syrjala
> Cc: Paulo Zanoni
> Cc: Jani Nikula
> Signed-off-by: Imre Deak
> --
just the enum's code
> comment
> accordingly.
I would probably have kept every enum, but let's proceed with your
colors.
More below:
>
> Cc: Ville Syrjala
> Cc: Paulo Zanoni
> Cc: Jani Nikula
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i
Em Sex, 2018-07-20 às 17:15 +0300, Imre Deak escreveu:
> The format for the ID names is _DISP_PW_* so rename the IDs
> not following this accordingly. Leave BXT_DPIO_CMN_BC as-is since
> we'll
> change that to use another existing ID in the next patch.
>
> Cc: Ville Syrj
ssible
> after the previous patches where we removed dependence on the actual
> enum values.
>
> Cc: Ville Syrjala
> Cc: Paulo Zanoni
> Cc: Jani Nikula
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 ---
> drivers/gpu/drm/i915
Em Sex, 2018-07-20 às 17:15 +0300, Imre Deak escreveu:
> On ICL there are 5 fused power gates, so add the two missing ones for
> clarity.
>
> Cc: Ville Syrjala
> Cc: Paulo Zanoni
Reviewed-by: Paulo Zanoni
> Cc: Jani Nikula
> Signed-off-by: Imre Deak
> ---
Em Qui, 2018-08-02 às 15:03 +0300, Imre Deak escreveu:
> On Wed, Aug 01, 2018 at 02:39:31PM -0700, Paulo Zanoni wrote:
> > Em Sex, 2018-07-20 às 17:14 +0300, Imre Deak escreveu:
> > > It makes sense to keep unchanging data const. Extract such fields
> > > from
> >
Lucas De Marchi
>
> >
> > Cc: Chris Wilson
> > Cc: Ville Syrjala
> > Cc: Paulo Zanoni
> > Cc: Jani Nikula
> > Signed-off-by: Imre Deak
> > ---
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 22 +++
> > ---
> > 1 fil
Em Seg, 2018-08-06 às 21:22 +0100, Chris Wilson escreveu:
> Save the module parameters from setup and restore them on teardown,
> so
> that we leave the system in the same state as we found it.
Currently kms_fbt uses igt_set_module_param_int() which uses
igt_save_module_param(), which installs an
Em Seg, 2018-08-06 às 22:07 +0100, Chris Wilson escreveu:
> Quoting Paulo Zanoni (2018-08-06 21:56:15)
> > Em Seg, 2018-08-06 às 21:22 +0100, Chris Wilson escreveu:
> > > Save the module parameters from setup and restore them on
> > > teardown,
> > > so
> &
check for unique IDs to __set_power_wells().
>
> Cc: Ville Syrjala
> Cc: Paulo Zanoni
> Cc: Jani Nikula
> Signed-off-by: Imre Deak
> Reviewed-by: Paulo Zanoni (v1)
R-B still valid for v2 (or v3) as long as the kcalloc checkpatch issue
is fixed.
> ---
> driver
ssible
> after the previous patches where we removed dependence on the actual
> enum values.
>
> v2:
> - Keep an ID assigned for the ICL PW#2 power well too. (Paulo)
A brief mention in the commit message that this actually fixes a bug on
ICL may be good.
Reviewed-by: Paulo Zano
st the enum's code
> comment
> accordingly.
>
> v2:
> - Keep required ID assignments for HSW_DISP_PW_GLOBAL and
> ICL_DISP_PW_2.
> (Paulo)
>
> Cc: Ville Syrjala
> Cc: Paulo Zanoni
Reviewed-by: Paulo Zanoni
> Cc: Jani Nikula
> Signed-off-by: Imre Deak
Use the nice helper function to make the implementation simpler.
Cc: Imre Deak
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915
tter use of our
time once a bug is found in the wild.
Cc: Imre Deak
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
ind
There's no need for that forward declaration.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 32 ++--
1 file changed, 14 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm
Use the same coding pattern as we use in the other functions of the
same file: just call lookup_power_well() directly in the only caller.
Cc: Imre Deak
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 20 +++-
1 file changed, 3 insertions(+), 17
Em Qua, 2018-08-08 às 15:22 -0700, Souza, Jose escreveu:
> On Wed, 2018-08-08 at 15:16 -0700, Paulo Zanoni wrote:
> > Use the same coding pattern as we use in the other functions of the
> > same file: just call lookup_power_well() directly in the only
> > caller.
> >
&g
Em Qua, 2018-08-08 às 22:22 +, Patchwork escreveu:
> == Series Details ==
>
> Series: series starting with [1/4] drm/i915: kill
> intel_display_power_well_is_enabled()
> URL : https://patchwork.freedesktop.org/series/47908/
> State : warning
>
> == Summary ==
>
> $ dim checkpatch origin/dr
Em Qui, 2018-08-09 às 08:29 +0200, Michal Wajdeczko escreveu:
> On Thu, 09 Aug 2018 00:58:53 +0200, Paulo Zanoni
> wrote:
>
> > Em Qua, 2018-08-08 às 22:22 +, Patchwork escreveu:
> > > == Series Details ==
> > >
> > > Series:
gt/drv_selftest/live_hangcheck/others-priority
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107399
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_lrc.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
As you may notice from the TODO comments, my GEM-fu is still not
ed-by: José Roberto de Souza
Suggested-by: James Ausmus
Signed-off-by: Manasi Navare
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 5 -
drivers/gpu/drm/i915/intel_dpll_mgr.c | 13 +++--
2 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/driver
.
v2 (from Paulo):
* Make the algorithm look more like what's in the spec, also document
where we differ form the spec and why.
* Make the code a little more consistent with our coding style.
Reviewed-by: José Roberto de Souza
Signed-off-by: Manasi Navare
Signed-off-by: Paulo Z
Em Sex, 2018-08-17 às 09:25 -0700, Srivatsa, Anusha escreveu:
> > -Original Message-
> > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On
> > Behalf Of
> > Paulo Zanoni
> > Sent: Wednesday, August 1, 2018 10:35 AM
> > To: intel-gfx@
Em Qua, 2018-08-15 às 23:27 +0300, Imre Deak escreveu:
> On Wed, Aug 08, 2018 at 03:16:11PM -0700, Paulo Zanoni wrote:
> > Use the same coding pattern as we use in the other functions of the
> > same file: just call lookup_power_well() directly in the only
> > caller.
&
Em Sex, 2018-08-17 às 16:41 -0700, Paulo Zanoni escreveu:
> Em Qua, 2018-08-15 às 23:27 +0300, Imre Deak escreveu:
> > On Wed, Aug 08, 2018 at 03:16:11PM -0700, Paulo Zanoni wrote:
> > > Use the same coding pattern as we use in the other functions of
> > > the
ild.
v2: Avoid the BUG() with a WARN() return a random PW (Michal).
Cc: Michal Wajdeczko
Cc: Imre Deak
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
Use the nice helper function to make the implementation simpler.
v2: Rebase.
Cc: Imre Deak
Reviewed-by: José Roberto de Souza (v1)
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers
Use the same coding pattern as we use in the other functions of the
same file: just call lookup_power_well() directly in the only caller.
Cc: Imre Deak
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 20 +++-
1 file changed, 3 insertions(+), 17
There's no need for that forward declaration.
Cc: Imre Deak
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 46 +++--
1 file changed, 21 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gp
I can't find a reason why we would want to call is_enabled(), which
does a register read, instead of just relying on our tracking with
hw_enabled. Let's try to trust our hardware sync.
Cc: Imre Deak
Requested-by: José Roberto de Souza
Signed-off-by: Paulo Zanoni
---
drivers/gp
Em Ter, 2018-08-21 às 14:12 +0300, Imre Deak escreveu:
> On Mon, Aug 20, 2018 at 04:11:27PM -0700, Paulo Zanoni wrote:
> > Em Sex, 2018-08-17 às 16:41 -0700, Paulo Zanoni escreveu:
> > > Em Qua, 2018-08-15 às 23:27 +0300, Imre Deak escreveu:
> > > > On Wed, Aug 08, 2
is
incorrect that we would have to add a few dozen more WARNs. Why add
this specific check at this specific case and not all other checks in
other possible cases that could break?
> So let's just add a protection and warn here.
>
> Cc: Paulo Zanoni
> Signed-off-by: Rodrigo Vivi
Em Ter, 2018-09-11 às 14:26 -0700, Rodrigo Vivi escreveu:
> On Tue, Sep 11, 2018 at 01:39:53PM -0700, Paulo Zanoni wrote:
> > Em Dom, 2018-09-02 às 22:15 -0700, Rodrigo Vivi escreveu:
> > > In case we forget to change intel_port_is_tc
> > > we would be trying to acces
Em Qua, 2018-09-12 às 09:31 -0500, Gustavo A. R. Silva escreveu:
> Function intel_port_to_tc() returns PORT_TC_NONE on error, which is
> a negative value -1. In case PORT_TC_NONE is returned, there is an
> undefined behavior when shifting by a negative number of bits in
> both DP_PHY_MODE_STATUS_NO
Em Qui, 2018-09-13 às 15:15 -0700, Anusha Srivatsa escreveu:
> We were using the default CFGCR0/1 instead of using
> TBT specific CFGCR0 and CFGCR1 registers during
> PLL sequence.
>
> Add missing TBTPLL_CFGCR0/1 registers and plumb
> them in the existing PLL sequence.
>
>
lve the bug
referenced? What is the real problem here? Please improve the commit
message: it not only helps future git log readers, but it also helps
reviewers like me understand where you're trying to get. I'm lost here.
> Signed-off-by: Maarten Lankhorst
> Cc: Paulo Zanoni
>
Em Ter, 2018-02-27 às 14:22 -0800, James Ausmus escreveu:
> On Thu, Feb 22, 2018 at 12:55:03AM -0300, Paulo Zanoni wrote:
> > There's a lot of code for the PLL enabling, so let's first only
> > introduce the register definitions in order to make patch reviewing
> > a
Em Qui, 2018-02-22 às 00:55 -0300, Paulo Zanoni escreveu:
> From: Manasi Navare
>
> This is an important part of the DDI initalization as well as
> for changing the voltage during DisplayPort link training.
>
> The Voltage swing seqeuence is similar to Cannonlake.
> How
Em Qui, 2018-02-22 às 00:55 -0300, Paulo Zanoni escreveu:
> From: Manasi Navare
>
> This sequence is used to setup voltage swing before enabling MG PHY
> DDI
> as well as for changing the voltage during DisplayPort Link training.
>
> For ICL, there are two types of DDIs. T
Em Qui, 2018-02-22 às 00:55 -0300, Paulo Zanoni escreveu:
> From: Arkadiusz Hiler
>
> Start using the new registers for ICL and on.
This patch doesn't make sense at this point of the series since we
don't run this code on ICL. I'll put it at the correct series.
>
Em Qui, 2018-02-22 às 00:55 -0300, Paulo Zanoni escreveu:
> Hello
>
> Here are some more ICL patches, now with the Combo & MG PLLs, some
> DP/HDMI
> initialization code and a few misc fixes.
>
> Again, the R-B tags already present in some of the patches (including
> t
There's a lot of code for the PLL enabling, so let's first only
introduce the register definitions in order to make patch reviewing a
little easier.
v2: Coding style (Jani).
v3: Preparation for upstreaming.
v4: Fix MG_CLKTOP2_CORECLKCTL1 address and random typos (James).
Signed-off
usmus
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_debugfs.c | 22 +++
drivers/gpu/drm/i915/intel_ddi.c | 96 ++-
drivers/gpu/drm/i915/intel_display.c | 16 ++
drivers/gpu/drm/i915/intel_dpll_mgr.c | 311 +-
drivers/gpu/drm
NG_MODE_SEL.
* Adjust the output type handling according to how the other platforms
do it now.
Cc: Jani Nikula
Cc: James Ausmus
Signed-off-by: Manasi Navare
Signed-off-by: Rodrigo Vivi
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_ddi.c | 191 ++-
1 f
(from Paulo):
* Use _PORT instead of _PICK
* Change some mask names to our current coding standards
* Stay under 80 columns
v3:
* Rebase on new revision of patches
v2:
* Remove whitespaces in the #defines (Paulo)
Cc: Rodrigo Vivi
Cc: Jani Nikula
Reviewed-by: Paulo Zanoni
Signed-off-by: Manasi
From: Dhinakaran Pandiyan
Extend enum hpd_pin to port F so that we can start using this for ICL.
v2: Rebase.
Cc: Rodrigo Vivi
Cc: Paulo Zanoni
Reviewed-by: Rodrigo Vivi
Signed-off-by: Dhinakaran Pandiyan
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_hotplug.c
done.
v2: Drop useless comment, and change !(GEN >= 11) to (GEN < 11). (Ville)
v3: No changes
v4 (from Paulo): Rebase.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Reviewed-by: Paulo Zanoni
Signed-off-by: James Ausmus
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++
From: Nabendu Maiti
Gen11 supports upto 5k source scaling
v2: Re-factoring of code as per review
v3: Corrected max Vertical size and indentation
v4: Added max Vertical dst size in same patch
Reviewed-by: Paulo Zanoni
Signed-off-by: Nabendu Maiti
---
drivers/gpu/drm/i915/intel_display.c | 11
Let's see that the CI has to say about them before we merge them.
These are taken from: [PATCH 00/17] ICL PLLs, DP/HDMI and misc display
Dhinakaran Pandiyan (1):
drm/i915/icl: HPD pin for port F
James Ausmus (1):
drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL
Manasi Navare (4):
s, same as DP (Paulo)
* Use combo_phy in ddi buf trans table defs (Paulo)
v2:
* Added DW4_scaling_hex column to the translation tables (Rodrigo)
Cc: Jani Nikula
Cc: Rodrigo Vivi
Reviewed-by: Paulo Zanoni
Signed-off-by: Manasi Navare
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/int
From: Manasi Navare
This table is used for voltage swing programming sequence during DDI
Buffer initialization for MG PHY DDI Buffers on Icelake.
v2 (from Paulo):
* Fix white space issues.
Cc: Rodrigo Vivi
Cc: Jani Nikula
Reviewed-by: Paulo Zanoni
Signed-off-by: Manasi Navare
Signed-off-by
in a diff patch (Paulo)
v2:
* Add new defs fro ICL regs (Paulo)
Cc: Jani Nikula
Cc: Rodrigo Vivi
Reviewed-by: Paulo Zanoni
Signed-off-by: Manasi Navare
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 44 +
1 file changed, 44 insertions
: commit 04416108ccea ("drm/i915/cnl: Add registers related to voltage
swing sequences.")
Cc: Rodrigo Vivi
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gp
s (Michal)
> >- When RC6 is enabled by BIOS, the fuse register cannot be read
> > until
> > the blitter powerwell is awake. Shuffle where the fuse is
> > read, prune
> > the forcewake domains after the fact and change the commit
> > message
> &
Em Ter, 2018-03-27 às 15:42 -0700, Paulo Zanoni escreveu:
> Em Sex, 2018-03-23 às 16:28 +, Lionel Landwerlin escreveu:
> > Hi Mika,
> >
> > Even after this series, we're still missing support for reading
> > the
> > timestamp frequency (read_timestam
us
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 149
1 file changed, 149 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 250ff271bcf1..b79b2a8930da 100644
--- a/drivers/gpu/drm/i915/
ed it.
Thanks,
Paulo
James Ausmus (1):
drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL
Manasi Navare (2):
drm/i915/icl: Implement voltage swing programming sequence for Combo
PHY DDI
drm/i915/icl: Fix the DP Max Voltage for ICL
Paulo Zanoni (5):
drm/i915/icl: add defin
HDMI mode DPLL programming on ICL is the same as CNL, so just reuse
the CNL code.
v2:
- Properly detect HDMI crtcs.
- Rebase after changes to the cnl function (clock * 1000).
v3:
- Add a comment to clarify why we treat 38.4 as 19.2 (James).
Reviewed-by: James Ausmus
Signed-off-by: Paulo
per before reviewing
this patch.
v2:
- Correctly identify DP encoders after upstream change.
- Small checkpatch issues.
- Rebase.
v3:
- Try to impove the comment on the tdc_targetcnt calculation based on
Manasi's feedback (Manasi).
- Rebase.
Reviewed-by; Manasi Navare
Signed-off-b
after the pll struct changes.
Cc: James Ausmus
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_debugfs.c | 22 +++
drivers/gpu/drm/i915/intel_ddi.c | 98 ++-
drivers/gpu/drm/i915/intel_display.c | 16 ++
drivers/gpu/drm/i915/intel_dpll_mgr.c
NG_MODE_SEL.
* Adjust the output type handling according to how the other platforms
do it now.
Cc: Jani Nikula
Cc: James Ausmus
Signed-off-by: Manasi Navare
Signed-off-by: Rodrigo Vivi
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_ddi.c | 191 ++-
1 f
done.
v2: Drop useless comment, and change !(GEN >= 11) to (GEN < 11). (Ville)
v3: No changes
v4 (from Paulo): Rebase.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Reviewed-by: Paulo Zanoni
Signed-off-by: James Ausmus
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++
) (Paulo)
v2:
* Rebase after patch that adds voltage check inside buf trans
function (Rodrigo)
Cc: Rodrigo Vivi
Cc: Paulo Zanoni
Reviewed-by: Rodrigo Vivi
Signed-off-by: Manasi Navare
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_ddi.c | 8 +++-
1 file changed, 7 insertions(+), 1
Just use the hardcoded tables provided by our spec.
v2: Rebase.
v3: Clarify that 38.4 uses the 19.2 table (James).
Reviewed-by: James Ausmus
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 87 ++-
1 file changed, 86 insertions(+), 1
Em Ter, 2018-04-10 às 09:51 +0100, Chris Wilson escreveu:
> Quoting Paulo Zanoni (2018-03-23 17:24:16)
> > From: Manasi Navare
> >
> > This table is used for voltage swing programming sequence during
> > DDI
> > Buffer initialization for MG PHY DDI Buffers on Ic
Em Ter, 2018-04-10 às 12:12 +0300, Jani Nikula escreveu:
> Apparently caused by a merge fail at some point. Due to the nature of
> the duplicated block, the second one will have no effect, and there's
> no
> need to backport.
>
> Signed-off-by: Jani Nikula
Re
Em Ter, 2018-04-10 às 22:07 +0100, Chris Wilson escreveu:
> Quoting Chris Wilson (2018-04-10 22:01:33)
> > Quoting Paulo Zanoni (2018-04-10 21:39:31)
> > > Em Ter, 2018-04-10 às 09:51 +0100, Chris Wilson escreveu:
> > > > Quoting Paulo Zanoni (2018-03-23 17:24:16)
Em Ter, 2018-04-10 às 22:01 +0100, Chris Wilson escreveu:
> Quoting Paulo Zanoni (2018-04-10 21:39:31)
> > Em Ter, 2018-04-10 às 09:51 +0100, Chris Wilson escreveu:
> > > Quoting Paulo Zanoni (2018-03-23 17:24:16)
> > > > From: Manasi Navare
> > > >
&g
Em Qui, 2018-05-17 às 10:04 -0700, Oscar Mateo Lozano escreveu:
>
> On 5/17/2018 9:55 AM, Michel Thierry wrote:
> > On 5/16/2018 4:39 PM, Paulo Zanoni wrote:
> > > Em Qui, 2018-05-10 às 14:59 -0700, Oscar Mateo escreveu:
> > > > Stop reading some now depre
gt; enable CSC and gamma again.
>
> BSpec: 4278 and 7635
>
> Cc: James Ausmus
> Cc: Paulo Zanoni
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/intel_display.c | 10 ++
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff
k for ICL based on PLLs.
Paulo Zanoni (11):
drm/i915/icl: introduce tc_port
drm/i915/icl: add icelake_get_ddi_pll()
drm/i915/icl: unconditionally init DDI for every port
drm/i915/icl: start adding the TBT pll
drm/i915/icl: compute the TBT PLL registers
drm/i915/icl: implement icl_digital
ts to Paulo for pointing out
the register change.
Signed-off-by: Dhinakaran Pandiyan
[Paulo: bikesheds and rebases]
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 38 --
drivers/gpu/drm/i915/i915_reg.h | 7 +++
2 files changed, 43 inser
From: Anusha Srivatsa
This patch adds the support to detect PCH_ICP.
Suggested-by: Paulo Zanoni
Signed-off-by: Anusha Srivatsa
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers
From: Anusha Srivatsa
This patch addresses Interrupts from south display engine (SDE).
ICP has two registers - SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
Introduce these registers and their intended values.
Introduce icp_irq_handler().
Cc: Paulo Zanoni
Cc: Dhinakaran Pandiyan
Cc: Ville Syrjala
From: Arkadiusz Hiler
Start using the new registers for ICL and on.
Cc: Manasi Navare
Cc: Rodrigo Vivi
Cc: Paulo Zanoni
Signed-off-by: Arkadiusz Hiler
---
drivers/gpu/drm/i915/intel_ddi.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915
From: Dhinakaran Pandiyan
This patch enables hotplug interrupts for DP over TBT output on TC
ports. The TBT interrupts are enabled and handled irrespective of the
actual output type which could be DP Alternate, DP over TBT, native DP
or native HDMI.
Cc: Animesh Manna
Cc: Paulo Zanoni
Cc
Just like DP, HDMI needs to implement these flows. The side effect is
that HDMI is now going to rely on the ISR bits, just like DP.
Signed-off-by: Paulo Zanoni
[Rodrigo: non-trivial rebase.]
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_hdmi.c | 11 ---
1 file changed, 8
Implement the hardware state readout code.
Thanks to Animesh Manna for spotting this problem.
Cc: Animesh Manna
Credits-to: Animesh Manna
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_display.c | 42 +++-
1 file changed, 41 insertions(+), 1
This commit just adds the register addresses and the basic skeleton of
the code. The next commits will expand on more specific functions.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_ddi.c | 16
drivers/gpu
flows
described by the "Gen11 TypeC Programming" page in our spec.
Cc: Animesh Manna
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 6 +
drivers/gpu/drm/i915/intel_dp.c | 57 -
2 files changed, 62 insertions(+), 1 deletion
Do like the other functions and check for the ISR bits. We have plans
to add a few more checks in this code in the next patches, that's why
it's a little more verbose than it could be.
Cc: Animesh Manna
Signed-off-by: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
---
drivers/gp
Programming this register is part of the Enable Sequence for
DisplayPort on ICL. Do as the spec says.
Cc: Animesh Manna
Cc: Manasi Navare
Cc: Dhinakaran Pandiyan
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 15 +
drivers/gpu/drm/i915/intel_ddi.c | 2 ++
drivers
Use the hardcoded tables provided by our spec.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 25 -
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index
The Gen11 TypeC PHY DDI Buffer chapter, PHY Clock Gating Programming
section says that PHY clock gating should be disabled before starting
voltage swing programming, then enabled after any link training is
complete.
Cc: Animesh Manna
Cc: Manasi Navare
Signed-off-by: Paulo Zanoni
---
drivers
On ICP, port present straps are no longer supported. Software should
determine the presence through BIOS VBT, hotplug or other mechanisms.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_display.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu
intel_dpll_mgr.c
to obtain the write array PLL Params and compares the set
pll_params with the table to get the corresponding link
clock.
Cc: Rodrigo Vivi
Cc: Mika Kahola
Cc: Paulo Zanoni
Signed-off-by: Manasi Navare
Signed-off-by: Lucas De Marchi
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915
From: Manasi Navare
This patch adds a proper HDMI DDI entry level for vswing
programming sequences on ICL.
Spec doesn't specify any default for HDMI tables,
so let's pick the last entry as the default for now
to stay consistent with older platform like CNL.
Cc: Paulo Zanoni
Cc: Raks
The type is detected based on the interrupt ISR bit. Once detected,
it's not supposed to be changed, so we have some sanity checks for
that.
Cc: Animesh Manna
Signed-off-by: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_display.h | 7 +++
drivers/gpu/drm
: significant rewrite of the patch.]
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_dp.c | 33 -
2 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915
From: "Sripada, Radhakrishna"
Starting Icelake silicon supports 10-bpc hdmi to support certain
media workloads. Currently hdmi supports 8 and 12 bpc. Plumbed
in support for 10 bit hdmi.
Cc: James Ausmus
Cc: Jani Nikula
Cc: Paulo Zanoni
Cc: Manasi Navare
Cc: Rodrigo Vivi
Cc: Vil
mode.
Cc: Jani Nikula
Cc: Animesh Manna
Cc: Madhav Chauhan
Cc: Anusha Srivatsa
Cc: Paulo Zanoni
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
| 0xC|
+--+---++
Cc: James Ausmus
Cc: Jani Nikula
Cc: Anusha Srivatsa
Cc: Clinton Taylor
Cc: Ville Syrjälä
Cc: Rodrigo Vivi
Cc: Paulo Zanoni
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Rodrigo Vivi
[Paulo: checkpatch fixes.]
Signed-off-by: Paulo Zanoni
--
From: Dhinakaran Pandiyan
ICL has AUX F.
Cc: Paulo Zanoni
Cc: Anusha Srivatsa
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b
written by Dhinakaran Pandiyan
and Mahesh Kumar.
Cc: Dhinakaran Pandiyan
Cc: Mahesh Kumar
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/intel_display.c | 16
drivers/gpu/drm/i915/intel_display.h | 11 +++
drivers/gpu/drm/i915/intel_drv.h | 3 +++
3 files
South
Display in PCH. This patch adds hotplug interrupt handling support for
DP Alternate mode.
Cc: Jani Nikula
Cc: Anusha Srivatsa
Signed-off-by: Dhinakaran Pandiyan
[Paulo: coding style changes]
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_irq.c | 95
Em Seg, 2018-05-21 às 17:25 -0700, Paulo Zanoni escreveu:
> From: Manasi Navare
>
> PLLs are the source clocks for the DDIs so in order
> to determine the ddi clock we need to check the PLL
> configuration.
>
> This gets a little tricky for ICL since there is
> n
Em Ter, 2018-05-22 às 14:44 +0300, Mika Kahola escreveu:
> On Mon, 2018-05-21 at 17:25 -0700, Paulo Zanoni wrote:
> > From: Manasi Navare
> >
> > PLLs are the source clocks for the DDIs so in order
> > to determine the ddi clock we need to check the PLL
> > co
201 - 300 of 3545 matches
Mail list logo
