Re: [Intel-gfx] [PATCH] x86/gpu: CNL uses the same GMS values as SKL

Em Sáb, 2017-04-08 às 03:21 +0800, kbuild test robot escreveu: > Hi Paulo, > > [auto build test ERROR on next-20170405] > [cannot apply to tip/x86/core v4.9-rc8 v4.9-rc7 v4.9-rc6 v4.11-rc5] > [if your patch is applied to the wrong git tree, please drop us a > note to help improve the system] This

Re: [Intel-gfx] [PATCH 32/67] drm/i915/cnl: DDI - PLL mapping

; v4: Spec is getting updated to do DDI -> PLL mapping > and clock on in 2 separated reg writes. (Paulo) > Also update bits definitions to use space > (1 << 1) instead of (1<<1). (Paulo) > > Cc: Paulo Zanoni > Cc: Art Runyan > Cc: Clint Taylor >

Re: [Intel-gfx] [PATCH 50/67] drm/i915/gen10+: use the SKL code for reading WM latencies

Em Seg, 2017-04-24 às 21:22 +0300, Ville Syrjälä escreveu: > On Thu, Apr 06, 2017 at 12:15:46PM -0700, Rodrigo Vivi wrote: > > > > From: Paulo Zanoni > > > > Gen 10 should use the exact same code as Gen 9, so change the check > > to > > take this into con

Re: [Intel-gfx] [PATCH 0/7] Add Y-tiling support into IGTs

kms_draw_crc it just gets stuck eating 100% of the CPU. I suppose this needs to be debugged, maybe some patch is wrong. Can you reproduce this behavior? > > Akash Goel (1): >   lib/igt_draw: Add Y-tiling support for IGT_DRAW_BLT method > > Paulo Zanoni (1): >   tests/kms_draw

Re: [Intel-gfx] [PATCH 6/7] igt/kms_frontbuffer_tracking: Add Y-tiling support

Em Sáb, 2017-03-18 às 00:45 +0530, Praveen Paneri escreveu: > Allow tests to create Y-tiled bufferes using a separate > argument to the test without increasing the number of > subtests. > > Signed-off-by: Praveen Paneri > --- >  tests/kms_frontbuffer_tracking.c | 46 +++---

Re: [Intel-gfx] [PATCH 4/7] lib/igt_draw: Add Y-tiling support for IGT_DRAW_BLT method

Em Sáb, 2017-03-18 às 00:45 +0530, Praveen Paneri escreveu: > From: Akash Goel > > Signed-off-by: Akash Goel > Signed-off-by: Praveen Paneri > --- >  lib/igt_draw.c | 35 +++ >  1 file changed, 35 insertions(+) > > diff --git a/lib/igt_draw.c b/lib/igt_draw.c > i

Re: [Intel-gfx] [PATCH 0/7] Add Y-tiling support into IGTs

Em Qua, 2017-04-26 às 10:46 -0300, Paulo Zanoni escreveu: > Em Sáb, 2017-03-18 às 00:45 +0530, Praveen Paneri escreveu: > > > > This series adds Y-tiled buffer creation support into IGT libraries > > and > > goes on to use this capability to add support into FBC tests

Re: [Intel-gfx] [PATCH RESEND i-g-t 2/2] kms_frontbuffer_tracking: Don't poke compressing status for old cpus

Em Qua, 2017-04-26 às 21:12 +0300, Ville Syrjälä escreveu: > On Wed, Apr 26, 2017 at 02:57:49PM -0300, Gabriel Krisman Bertazi > wrote: > > > > Paulo Zanoni writes: > > > > > > > > Ouch... Good catch! > > > > > > Can you please move

Re: [Intel-gfx] [PATCH v2 0/7] Add Y-tiling support into IGTs

ix it before resending. > > Akash Goel (1): >   lib/igt_draw: Add Y-tiling support for IGT_DRAW_BLT method > > Paulo Zanoni (1): >   tests/kms_draw_crc: add support for Y tiling > > Praveen Paneri (5): >   lib/igt_fb: Let others use igt_get_fb_tile_size >   lib/i

[Intel-gfx] [PATCH 2/3] drm/i915: make the primary plane func structs const

Because we can, the places where we use them already expect const structs. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] [PATCH 3/3] drm/i915: remove a copy of skl_plane_format_mod_supported()

bring back the additional copy if we need. Cc: Ville Syrjälä Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 50 drivers/gpu/drm/i915/intel_drv.h | 2 ++ drivers/gpu/drm/i915/intel_sprite.c | 4 +-- 3 files changed, 4 insertions(+

[Intel-gfx] [PATCH 1/3] drm/i915: DRM_FORMAT_C8 is not possible with Yf tiling

fix the missing /* fall through */ in the chunk we modified by just turning it into a "break;" since IMHO breaks are easier to read than fall-throughs. BSpec: 18565 Testcase: igt/kms_addfb_basic/expected-formats (not merged yet) Cc: Ville Syrjälä Signed-off-by: Paulo Zanoni --- drive

Re: [Intel-gfx] [PATCH 1/3] drm/i915: DRM_FORMAT_C8 is not possible with Yf tiling

Em Ter, 2018-09-25 às 15:02 +0300, Ville Syrjälä escreveu: > On Mon, Sep 24, 2018 at 05:19:11PM -0700, Paulo Zanoni wrote: > > Function intel_framebuffer_init() checks for the possibilities > > during > > framebuffer creation (addfb ioctl time). It is missing the fact >

Re: [Intel-gfx] [PATCH 2/3] drm/i915: make the primary plane func structs const

Em Ter, 2018-09-25 às 15:05 +0300, Ville Syrjälä escreveu: > On Mon, Sep 24, 2018 at 05:19:12PM -0700, Paulo Zanoni wrote: > > Because we can, the places where we use them already expect const > > structs. > > https://patchwork.freedesktop.org/series/44104/ already has the r

Re: [Intel-gfx] [PATCH 1/3] drm/i915: DRM_FORMAT_C8 is not possible with Yf tiling

Em Qui, 2018-09-27 às 17:16 +0300, Ville Syrjälä escreveu: > On Tue, Sep 25, 2018 at 03:02:21PM -0700, Paulo Zanoni wrote: > > Em Ter, 2018-09-25 às 15:02 +0300, Ville Syrjälä escreveu: > > > On Mon, Sep 24, 2018 at 05:19:11PM -0700, Paulo Zanoni wrote: > > > > F

[Intel-gfx] [PATCH 1/6] drm/i915: don't apply Display WAs 1125 and 1126 to GLK/CNL+

BSpec does not show these WAs as applicable to GLK, and for CNL it only shows them applicable for a super early pre-production stepping we shouldn't be caring about anymore. Remove these so we can avoid them on ICL too. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_pm.c

[Intel-gfx] [PATCH 6/6] drm/i915: promote ddb update message to DRM_DEBUG_KMS

This message is currently marked as DRM_DEBUG_ATOMIC. I would like it to be DRM_DEBUG_KMS since it is more KMS than atomic, and this will also make the message appear in the CI logs, which may or may not help us with some FIFO underrun bugs. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 3/6] drm/i915: fix the watermark result selection on glk/gen10+

On these platforms we're supposed to unconditonally pick the method 2 result instead of the minimum. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_pm.c | 23 --- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_p

[Intel-gfx] [PATCH 2/6] drm/i915: fix the transition minimums for gen9+ watermarks

The transition minimum is 14 blocks for gens 9 and 10, and 4 blocks for gen 11. This minimum value is supposed to be added to the configurable trans_amount. This matches both BSpec and additional information provided by our HW engineers. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 0/6] Watermarks small fixes/improvements

I'm investigating ICL watermarks failures and these are some of the immediate problems I was able to find in the watermarks code. I don't think they're enough to fix the problems our CI is able to reproduce, but I do think these changes are worth having. Paulo Zanoni (6): drm/i9

[Intel-gfx] [PATCH 4/6] drm/i915: transition WMs ask for Selected Result Blocks

Blocks minus 1 without any rounding errors. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_pm.c | 18 +++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 40ce99c455f3..14f13a371989 100644

[Intel-gfx] [PATCH 5/6] drm/i915: don't write PLANE_BUF_CFG twice every time

y avoiding the double write. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_pm.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 14f13a371989..53b4a9a2de69 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/d

Re: [Intel-gfx] [PATCH] firmware/dmc/icl: Add missing MODULE_FIRMWARE() for Icelake.

e definition macros") > v4: Rodrigo fixing his own mess on commit mentioning on v3 > comment above. > > Fixes: 4445930f1c4a ("firmware/dmc/icl: load v1.07 on icelake.") Yes, please. I wasted time because I lacked this commit. Tested-by: Paulo Zanoni > Cc: Rodrigo Vivi

Re: [Intel-gfx] [PATCH 1/6] drm/i915: don't apply Display WAs 1125 and 1126 to GLK/CNL+

Em Ter, 2018-10-09 às 16:55 -0700, Matt Roper escreveu: > On Thu, Oct 04, 2018 at 04:15:55PM -0700, Paulo Zanoni wrote: > > BSpec does not show these WAs as applicable to GLK, and for CNL it > > only shows them applicable for a super early pre-production > > stepping >

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/icl: Avoid Gen10 watermark workarounds in Gen11

Em Qua, 2018-09-05 às 16:41 -0700, Rodrigo Vivi escreveu: > On Wed, Sep 05, 2018 at 02:32:38PM +0530, Karthik B S wrote: > > Display Workarounds #1125 and #1126 are intended for Gen10 and > > below platforms. These workarounds can be avoided in Gen11. > > > > The result blocks for WM1-WM7 should b

[Intel-gfx] [PATCH] drm/i915/icl: enable SAGV for ICL platform

From: Mahesh Kumar Enable SAGV for ICL platform. Cc: Gwan-gyeong Mun Reviewed-by: James Ausmus Reviewed-by: Paulo Zanoni Signed-off-by: Mahesh Kumar Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) I had previously

[Intel-gfx] [PATCH] drm/i915/cnp+: update to the new RAWCLK_FREQ recommendations

ust matching the values listed in BSpec instead of recalculating them. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h| 1 - drivers/gpu/drm/i915/intel_cdclk.c | 37 ++--- 2 files changed, 6 insertions(+), 32 deletions(-) diff --git a/driv

[Intel-gfx] [PATCH 05/11] drm/i915: simplify wm->is_planar assignment

on the place to assign it. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_pm.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d1dd3ae408f9..7fd344b81d66 100644 --- a/drivers/gpu/drm/i915/i

[Intel-gfx] [PATCH 02/11] drm/i915: remove padding from struct skl_wm_level

. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3017ef037fed..3616b718b5d2 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 01/11] drm/i915: don't apply Display WAs 1125 and 1126 to GLK/CNL+

BSpec does not show these WAs as applicable to GLK, and for CNL it only shows them applicable for a super early pre-production stepping we shouldn't be caring about anymore. Remove these so we can avoid them on ICL too. Cc: Matt Roper Signed-off-by: Paulo Zanoni --- drivers/gpu/drm

[Intel-gfx] [PATCH 11/11] drm/i915: pass dev_priv instead of cstate to skl_compute_transition_wm()

Stop passing modeset state structures to functions that should work only with the skl_wm_params. The only use for cstate there was to reach dev_priv, so pass it directly. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_pm.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions

[Intel-gfx] [PATCH 06/11] drm/i915: refactor skl_write_plane_wm()

it's on a void function really doesn't help readability IMHO. Refactor the function so that the first level of checks is per platform and the second level is for planar planes. IMHO that makes the code much more readable. Requested-by: Matt Roper Signed-off-by: Paulo Zanoni --- drivers/gpu

[Intel-gfx] [PATCH 07/11] drm/i915: move ddb_blocks to be a watermark parameter

. The ddb_blocks parameter is one that is used by both the the plane watermarks and the transition watermarks. Move ddb_blocks to the parameter struct so we can simplify the code. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 44

[Intel-gfx] [PATCH 03/11] drm/i915: fix handling of invisible planes in watermarks code

: igt/kms_cursor_legacy/nonblocking-modeset-vs-cursor-atomic Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 15 ++- 2 files changed, 7 insertions(+), 9 deletions(-) The error message mentioned above isd the one added by patch 06 o

[Intel-gfx] [PATCH 10/11] drm/i915: add pipe_htotal to struct skl_wm_params

chosen names for its parameters. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 20 2 files changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index

[Intel-gfx] [PATCH 09/11] drm/i915: make skl_needs_memory_bw_wa() take dev_priv instead of state

ation functions. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_pm.c | 14 -- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 1290efc64869..d101c542f10d 100644 --- a/drivers/gpu/drm

[Intel-gfx] [PATCH 08/11] drm/i915: reorganize the error message for invalid watermarks

ndom intel state structs. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_pm.c | 27 --- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 4053f4a68657..1290efc64869 100644 ---

[Intel-gfx] [PATCH 04/11] drm/i915: remove useless memset() for watermarks parameters

mset "just to be safe", then we should also zero initialize it when we use it for plane 0. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_pm.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9043ff

[Intel-gfx] [PATCH 00/11] More watermarks improvements

Except for maybe patch 1, I don't believe this series will allow us to close any real bugs, but at least it should make the code more readable. Please notice that we removed more lines than we added :). Thanks, Paulo Paulo Zanoni (11): drm/i915: don't apply Display WAs 1125 and 1126

Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for More watermarks improvements

Em Ter, 2018-10-16 às 22:21 +, Patchwork escreveu: > == Series Details == > > Series: More watermarks improvements > URL : https://patchwork.freedesktop.org/series/51086/ > State : warning > > == Summary == > > $ dim checkpatch origin/drm-tip > 6a8c3f3d3663 drm/i915: don't apply Display WA

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for More watermarks improvements

Em Ter, 2018-10-16 às 22:39 +, Patchwork escreveu: > == Series Details == > > Series: More watermarks improvements > URL : https://patchwork.freedesktop.org/series/51086/ > State : failure > > == Summary == > > = CI Bug Log - changes from CI_DRM_4990 -> Patchwork_10481 = > > == Summary -

Re: [Intel-gfx] [PATCH] drm/i915/cnp+: update to the new RAWCLK_FREQ recommendations

Em Sex, 2018-10-12 às 15:42 +0300, Ville Syrjälä escreveu: > On Thu, Oct 11, 2018 at 05:40:45PM -0700, Paulo Zanoni wrote: > > These are the new recommended values provided by our spec (18 -> 19 > > and 23 -> 24). It seems this should help fixing GMBUS issues. Since > >

Re: [Intel-gfx] [PATCH 08/11] drm/i915: reorganize the error message for invalid watermarks

Em Qui, 2018-10-18 às 16:55 +0300, Ville Syrjälä escreveu: > On Tue, Oct 16, 2018 at 03:01:30PM -0700, Paulo Zanoni wrote: > > Print a more generic "failed to compute watermark levels" whenever > > any > > of skl_compute_wm_levels() fail, and print only the spe

Re: [Intel-gfx] [PATCH 07/11] drm/i915: move ddb_blocks to be a watermark parameter

Em Qui, 2018-10-18 às 16:41 +0300, Ville Syrjälä escreveu: > On Tue, Oct 16, 2018 at 03:01:29PM -0700, Paulo Zanoni wrote: > > The goal of struct skl_wm_params is to cache every watermark > > parameter so the other functions can just use them without worrying > > about the

Re: [Intel-gfx] [PATCH 01/11] drm/i915: don't apply Display WAs 1125 and 1126 to GLK/CNL+

Em Qui, 2018-10-18 às 16:14 +0300, Ville Syrjälä escreveu: > On Tue, Oct 16, 2018 at 03:01:23PM -0700, Paulo Zanoni wrote: > > BSpec does not show these WAs as applicable to GLK, and for CNL it > > only shows them applicable for a super early pre-production > > stepping >

Re: [Intel-gfx] [PATCH] drm/i915: Simplify has_sagv

Em Seg, 2018-10-22 às 09:57 -0700, Rodrigo Vivi escreveu: > Let's add a platform has_sagv instead of having a full > function that handle platform by platform. > > The specially case for SKL for not controlled sagv > is already taken care inside intel_enable_sagv, so there's > no need to duplicate

Re: [Intel-gfx] [PATCH 01/11] drm/i915: don't apply Display WAs 1125 and 1126 to GLK/CNL+

Em Seg, 2018-10-22 às 16:55 -0700, Rodrigo Vivi escreveu: > On Mon, Oct 22, 2018 at 04:32:00PM -0700, Paulo Zanoni wrote: > > Em Qui, 2018-10-18 às 16:14 +0300, Ville Syrjälä escreveu: > > > On Tue, Oct 16, 2018 at 03:01:23PM -0700, Paulo Zanoni wrote: > > > > BS

Re: [Intel-gfx] [PATCH] drm/i915: Simplify has_sagv

Em Seg, 2018-10-22 às 17:06 -0700, Rodrigo Vivi escreveu: > On Mon, Oct 22, 2018 at 04:48:50PM -0700, Paulo Zanoni wrote: > > Em Seg, 2018-10-22 às 09:57 -0700, Rodrigo Vivi escreveu: > > > Let's add a platform has_sagv instead of having a full > > > function

Re: [Intel-gfx] [PATCH] drm/i915/icl: Add power well support

r well 3 dependency > > v4: > - Rebase > > v5: > - Detach AUX power wells from the INIT power domain. These power > wells > can only be enabled in a TC/TBT connected state and otherwise not > needed during driver initialization. > > Cc: Animesh Manna > Cc: Rak

Re: [Intel-gfx] [PATCH] drm/i915/icp: Add Interrupt Support

mments. Confirm in the commit message that > icp_irq_postinstall() need not go to > ibx_irq_pre_postinstall() and ibx_irq_postinstall() > as in earlier platforms. (Paulo) > > Cc: Lucas De Marchi > Cc: Paulo Zanoni > Cc: Dhinakaran Pandiyan > Cc: Ville Syrjala > Si

Re: [Intel-gfx] [PATCH] drm/i915: encourage BIT() macro usage in register definitions

> > There's already some BIT() usage here and there, embrace it. > > > > > > > > Cc: Paulo Zanoni Since I'm CC'd I guess my opinion counts here :) > > > > Signed-off-by: Jani Nikula > > > > --- > > > > drivers/gpu/

Re: [Intel-gfx] [PATCH] usb/icl: Work around ACPI boottime crash

Em Seg, 2018-07-02 às 16:57 +0300, Imre Deak escreveu: > Work around the following boot time crash: I worked around a very similar boot time crash by disabling CONFIG_SLAB_FREELIST_HARDENED. Can you please verify if this helps? Reference is LCK-5401. > > [ 10.456056] CPU: 1 PID: 220 Comm: sys

Re: [Intel-gfx] [PATCH 2/2] drm/i915: use the ICL stolen memory

Em Sex, 2018-07-06 às 19:09 -0700, Lucas De Marchi escreveu: > On Fri, May 4, 2018 at 1:33 PM Paulo Zanoni > wrote: > > > > Now that our stolen memory is already reserved by the x86 subsystem > > (since commit "x86/gpu: reserve ICL's graphics stolen memory"

Re: [Intel-gfx] [PATCH 20/24] drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP

Em Qui, 2018-06-21 às 15:04 -0700, Srivatsa, Anusha escreveu: > > -Original Message- > > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On > > Behalf Of > > Paulo Zanoni > > Sent: Monday, May 21, 2018 5:26 PM > > To: intel-gfx@lists.fre

[Intel-gfx] [PATCH 1/8] drm/i915/icl: compute the TBT PLL registers

Use the hardcoded tables provided by our spec. v2: - SSC stays disabled. - Use intel_port_is_tc(). Cc: Anusha Srivatsa Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_dpll_mgr.c | 22 +- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers

[Intel-gfx] [PATCH 4/8] drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP

flows described by the "Gen11 TypeC Programming" page in our spec. Cc: Animesh Manna Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 6 + drivers/gpu/drm/i915/intel_dp.c | 57 - 2 files changed, 62 insertions(+), 1 deletion

[Intel-gfx] [PATCH 7/8] drm/i915/icl: program MG_DP_MODE

Programming this register is part of the Enable Sequence for DisplayPort on ICL. Do as the spec says. Cc: Animesh Manna Reviewed-by: Maarten Lankhorst Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 15 + drivers/gpu/drm/i915/intel_ddi.c | 2 ++ drivers/gpu/drm

[Intel-gfx] [PATCH 2/8] drm/i915/icl: implement icl_digital_port_connected()

Do like the other functions and check for the ISR bits. We have plans to add a few more checks in this code in the next patches, that's why it's a little more verbose than it could be. v2: Rebase. Cc: Animesh Manna Reviewed-by: Lucas De Marchi (v1) Signed-off-by: Paulo Zanoni Sig

[Intel-gfx] [PATCH 3/8] drm/i915/icl: store the port type for TC ports

The type is detected based on the interrupt ISR bit. Once detected, it's not supposed to be changed, so we have some sanity checks for that. Cc: Animesh Manna Signed-off-by: Paulo Zanoni Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_display.h | 7 +++ drivers/gpu/drm

[Intel-gfx] [PATCH 0/8] Remaining ICL display patches

These are the remaining patches from the series called "[PATCH 00/24] More ICL display patches". Patches 1, 3 and 4 still need reviews. Animesh Manna (1): drm/i915/icl: Update FIA supported lane count for hpd. Paulo Zanoni (7): drm/i915/icl: compute the TBT PLL registers dr

[Intel-gfx] [PATCH 5/8] drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI

Just like DP, HDMI needs to implement these flows. The side effect is that HDMI is now going to rely on the ISR bits, just like DP. Reviewed-by: Mika Kahola Signed-off-by: Paulo Zanoni [Rodrigo: non-trivial rebase.] Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_hdmi.c | 11

[Intel-gfx] [PATCH 6/8] drm/i915/icl: Update FIA supported lane count for hpd.

-by: Animesh Manna [Paulo: significant rewrite of the patch.] Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 5 + drivers/gpu/drm/i915/intel_dp.c | 33 - 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 8/8] drm/i915/icl: toggle PHY clock gating around link training

-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 21 + drivers/gpu/drm/i915/intel_ddi.c | 3 ++ drivers/gpu/drm/i915/intel_dp.c | 66 drivers/gpu/drm/i915/intel_drv.h | 2 ++ 4 files changed, 92 insertions(+) diff --git a/drivers/gpu

Re: [Intel-gfx] [PATCH] drm/i915: inline skl_copy_ddb_for_pipe() to its only caller

Em Sex, 2018-06-08 às 00:49 +0100, Chris Wilson escreveu: > Quoting Paulo Zanoni (2018-06-08 00:07:00) > > static void > > skl_print_wm_changes(const struct drm_atomic_state *state) > > { > > @@ -5381,7 +5370,10 @@ static void skl_initial_wm(struct > > intel_at

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI

t; v2: > * Change the MG_TX_DRVCTL registers names to match the spec (Anusha) > > Signed-off-by: Manasi Navare > Cc: Paulo Zanoni > Cc: James Ausmus > --- > drivers/gpu/drm/i915/i915_reg.h | 246 +++--- > -- > 1 file changed, 145 insert

Re: [Intel-gfx] [PATCH 1/8] drm/i915/icl: compute the TBT PLL registers

Em Qui, 2018-07-12 às 17:16 -0700, Rodrigo Vivi escreveu: > On Wed, Jul 11, 2018 at 02:59:02PM -0700, Paulo Zanoni wrote: > > Use the hardcoded tables provided by our spec. > > > > v2: > > - SSC stays disabled. > > - Use intel_port_is_tc(). > > >

Re: [Intel-gfx] [PATCH 1/8] drm/i915/icl: compute the TBT PLL registers

Em Sex, 2018-07-13 às 11:04 -0700, Rodrigo Vivi escreveu: > On Fri, Jul 13, 2018 at 10:20:27AM -0700, Paulo Zanoni wrote: > > Em Qui, 2018-07-12 às 17:16 -0700, Rodrigo Vivi escreveu: > > > On Wed, Jul 11, 2018 at 02:59:02PM -0700, Paulo Zanoni wrote: > > > > Use th

Re: [Intel-gfx] [PATCH 1/8] drm/i915/icl: compute the TBT PLL registers

Em Sex, 2018-07-13 às 14:08 -0700, Rodrigo Vivi escreveu: > On Wed, Jul 11, 2018 at 02:59:02PM -0700, Paulo Zanoni wrote: > > Use the hardcoded tables provided by our spec. > > > > v2: > > - SSC stays disabled. > > - Use intel_port_is_tc(). > > >

Re: [Intel-gfx] [PATCH v3] drm/i915/icl: Add remaining registers and bitfields for MG PHY DDI

> * Fix register names, add spaces for MASK defines, correct the order > of #defines (Paulo) > > v2: > * Change the MG_TX_DRVCTL registers names to match the spec (Anusha) > > Signed-off-by: Manasi Navare > Cc: Paulo Zanoni > Cc: James Ausmus > --- > drivers/gpu/drm

Re: [Intel-gfx] [PATCH 3/8] drm/i915/icl: store the port type for TC ports

Em Qui, 2018-07-12 às 23:14 -0700, Rodrigo Vivi escreveu: > On Wed, Jul 11, 2018 at 02:59:04PM -0700, Paulo Zanoni wrote: > > The type is detected based on the interrupt ISR bit. Once detected, > > it's not supposed to be changed, so we have some sanity checks for > >

Re: [Intel-gfx] [PATCH 1/8] drm/i915/icl: compute the TBT PLL registers

Em Seg, 2018-07-16 às 15:47 -0700, Rodrigo Vivi escreveu: > On Fri, Jul 13, 2018 at 03:57:45PM -0700, Paulo Zanoni wrote: > > Em Sex, 2018-07-13 às 14:08 -0700, Rodrigo Vivi escreveu: > > > On Wed, Jul 11, 2018 at 02:59:02PM -0700, Paulo Zanoni wrote: > > > > Use th

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/icl: Implement voltage swing programming sequence for MG PHY DDI

gt; for MG PHY DDI which is ports C-F. And our spec is still incomplete... Reviewed-by: Paulo Zanoni > > v6 (From Manasi): > * Add programming for MG_CLKHUB and MG_TX_DCC as per the > spec updates > > v5 (from Paulo): > * Checkpatch. > v4 (from Paulo): > * Fix bogus e

[Intel-gfx] [PATCH] drm/i915/icl: implement icl_digital_port_connected()

ladder (Rodrigo). - Don't use the ISR for TC/TBT CPU bits. Cc: Animesh Manna Cc: Rodrigo Vivi Reviewed-by: Lucas De Marchi (v1) Signed-off-by: Rodrigo Vivi Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 8 + drivers/gpu/drm/i915/intel_dp.c | 55

[Intel-gfx] [PATCH 5/5] drm/i915/icl: toggle PHY clock gating around link training

Lankhorst (v1) Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 20 ++ drivers/gpu/drm/i915/intel_ddi.c | 3 ++ drivers/gpu/drm/i915/intel_dp.c | 66 drivers/gpu/drm/i915/intel_drv.h | 2 + 4 files changed, 91 insertions(+) diff --git a

[Intel-gfx] [PATCH 3/5] drm/i915/icl: Update FIA supported lane count for hpd.

. Reviewed-by: Anusha Srivatsa (v1). Signed-off-by: Animesh Manna [Paulo: significant rewrite of the patch.] Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_dp.c | 33 - 2 files changed, 35 insertions(+), 1 deletion

[Intel-gfx] [PATCH 0/5] Remaining ICL display patches, v2

Vivi Thanks, Paulo Animesh Manna (1): drm/i915/icl: Update FIA supported lane count for hpd. Paulo Zanoni (4): drm/i915/icl: implement icl_digital_port_connected() drm/i915/icl: store the port type for TC ports drm/i915/icl: program MG_DP_MODE drm/i915/icl: toggle PHY clock gating around

[Intel-gfx] [PATCH 4/5] drm/i915/icl: program MG_DP_MODE

Programming this register is part of the Enable Sequence for DisplayPort on ICL. Do as the spec says. v2: Simple rebase. Cc: Animesh Manna Reviewed-by: Maarten Lankhorst (v1) Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 15 drivers/gpu/drm/i915/intel_ddi.c | 2

[Intel-gfx] [PATCH 2/5] drm/i915/icl: store the port type for TC ports

The type is detected based on the live status bits. Once detected, it's not supposed to be changed, so we have some sanity checks for that. v2: Rebase. Cc: Animesh Manna Signed-off-by: Rodrigo Vivi Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.h | 7 + driver

[Intel-gfx] [PATCH] drm/i915/icl: implement icl_digital_port_connected()

ladder (Rodrigo). - Don't use the ISR for TC/TBT CPU bits. Cc: Animesh Manna Cc: Rodrigo Vivi Signed-off-by: Rodrigo Vivi Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 8 + drivers/gpu/drm/i915/intel_dp.c | 55 - 2 files changed,

Re: [Intel-gfx] [PATCH] drm/i915/icl: implement icl_digital_port_connected()

Em Ter, 2018-07-24 às 18:19 -0700, Lucas De Marchi escreveu: > On Tue, Jul 24, 2018 at 05:28:09PM -0700, Paulo Zanoni wrote: > > Do like the other functions and check for the status bits. The "Hot > > Plug Detection" page from our documentation says we can't just u

Re: [Intel-gfx] [PATCH 3/5] drm/i915/icl: Update FIA supported lane count for hpd.

Em Qua, 2018-07-25 às 09:52 -0700, Rodrigo Vivi escreveu: > On Tue, Jul 24, 2018 at 05:28:11PM -0700, Paulo Zanoni wrote: > > From: Animesh Manna > > > > In ICL, Flexible IO Adapter (FIA) muxes data and clocks of USB 3.1, > > tbt and display controller. In DP

Re: [Intel-gfx] [PATCH] drm/i915/icl: implement icl_digital_port_connected()

Em Ter, 2018-07-24 às 18:19 -0700, Lucas De Marchi escreveu: > On Tue, Jul 24, 2018 at 05:28:09PM -0700, Paulo Zanoni wrote: > > Do like the other functions and check for the status bits. The "Hot > > Plug Detection" page from our documentation says we can't just u

Re: [Intel-gfx] [PATCH] drm/i915/icl: implement icl_digital_port_connected()

Em Qua, 2018-07-25 às 10:27 -0700, Paulo Zanoni escreveu: > Em Ter, 2018-07-24 às 18:19 -0700, Lucas De Marchi escreveu: > > On Tue, Jul 24, 2018 at 05:28:09PM -0700, Paulo Zanoni wrote: > > > Do like the other functions and check for the status bits. The > > > "Hot

[Intel-gfx] [PATCH v4 1/5] drm/i915/icl: implement icl_digital_port_connected()

off-by: Rodrigo Vivi Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 8 ++ drivers/gpu/drm/i915/intel_dp.c | 55 - 2 files changed, 62 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i

Re: [Intel-gfx] sad output names

Em Qua, 2018-07-25 às 09:20 -0700, Rodrigo Vivi escreveu: > On Wed, Jul 25, 2018 at 03:37:52AM -0400, Felix Miata wrote: > > Asus B250 LGA 1151 (Kaby Lake) Motherboard (4 total physical video > > outputs): > > https://www.asus.com/us/Motherboards/PRIME-B250M-C-CSM/ > > > > G4600 HD Graphics 630 CP

Re: [Intel-gfx] [PATCH 1/2] drm/i915/icl: Add TBT checks for PLL calculations

Em Qua, 2018-07-25 às 14:28 -0700, Anusha Srivatsa escreveu: > Add missing TBT check in the Pll calculation. > > v2: do not use a auxiliary function to check if status is > TBT or not. (Paulo) > > Cc: Paulo Zanoni > Cc: Lucas De Marchi > Signed-off-by: Anusha Srivatsa

Re: [Intel-gfx] [PATCH 2/2] drm/i915/icl: Set TBT IO in Aux transaction

Em Qua, 2018-07-25 às 14:28 -0700, Anusha Srivatsa escreveu: > For a TBT sequence, we need to set the IO type to TBT > in DDI_AUX_CTL. > > Cc: Paulo Zanoni > Signed-off-by: Anusha Srivatsa > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/

[Intel-gfx] [PATCH] drm/i915/icl: don't set CNL_DDI_CLOCk_REG_ACCESS_ON anymore

ng the bit doesn't seem realistic according to the HW team. Let's follow their recommendation. BSpec: 20233 References: commit c8af5274c3cb ("drm/i915: enable the pipe/transcoder/planes later on HSW+") Cc: José Roberto de Souza Signed-off-by: Paulo Zanoni --- drivers/gpu/d

[Intel-gfx] [PATCH 1/2] drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider value defines

these defines instead of magic register values. The new defines are going to be used in the next patch. v2 (from Paulo): * Rebase. * Make it look a little more like the rest of our code. Cc: James Ausmus Suggested-by: James Ausmus Signed-off-by: Manasi Navare Signed-off-by: Paulo Zanoni

[Intel-gfx] [PATCH 2/2] drm/i915/icl: Get DDI clock for ICL for MG PLL and TBT PLL

. v2 (from Paulo): * Make the algorithm look more like what's in the spec, also document where we differ form the spec and why. * Make the code a little more consistent with our coding style. Cc: James Ausmus Signed-off-by: Manasi Navare Signed-off-by: Paulo Zanoni --- drivers/gpu/drm

Re: [Intel-gfx] [PATCH 1/2] drm/i915/icl: Add TBT checks for PLL calculations

Em Qui, 2018-07-26 às 16:35 -0700, Anusha Srivatsa escreveu: > Add missing TBT check in the Pll calculation. > > v2: do not use a auxiliary function to check if status is > TBT or not. (Paulo) > > v3: Code style changes. (Paulo) > > Cc: Paulo Zanoni > Cc: Lucas De

Re: [Intel-gfx] [PATCH 2/2] drm/i915/icl: Set TBT IO in Aux transaction

Em Qui, 2018-07-26 às 16:35 -0700, Anusha Srivatsa escreveu: > For a TBT sequence, we need to set the IO type to TBT > in DDI_AUX_CTL. > > v2: Avoid duplications.(Paulo) > > Cc: Paulo Zanoni > Signed-off-by: Anusha Srivatsa Reviewed-by: Paulo Zanoni > --- > driv

Re: [Intel-gfx] [PATCH] drm/i915/icl: don't set CNL_DDI_CLOCk_REG_ACCESS_ON anymore

Em Qui, 2018-07-26 às 14:02 -0700, Souza, Jose escreveu: > On Wed, 2018-07-25 at 17:12 -0700, Paulo Zanoni wrote: > > The new recommendation from the spec is to simply not set this bit > > anymore. Not setting the bit would prevent some hangs that our > > driver > > ma

[Intel-gfx] [PATCH] drm/i915/icl: implement the tc/legacy HPD {dis, }connect flows

ff-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 6 +++ drivers/gpu/drm/i915/intel_dp.c | 110 +- drivers/gpu/drm/i915/intel_hdmi.c | 11 ++-- 3 files changed, 123 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/dr

[Intel-gfx] [PATCH] drm/i915/icl: avoid unclaimed PLANE_NV12_BUF_CFG register

t 234059da0f33 ("drm/i915/icl: NV12 y-plane ddb is not in same plane") Cc: Mahesh Kumar Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_pm.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915

Re: [Intel-gfx] [PATCH] drm/i915/icl: implement the tc/legacy HPD {dis, }connect flows

Em Qua, 2018-08-01 às 09:22 +0100, Chris Wilson escreveu: > Quoting Paulo Zanoni (2018-08-01 00:45:04) > > +static bool icl_tc_phy_connect(struct drm_i915_private *dev_priv, > > + struct intel_digital_port *dig_port) > > +{ > > +

[Intel-gfx] [PATCH v3] drm/i915/icl: implement the tc/legacy HPD {dis, }connect flows

can't act on in case it does (Chris). BSpec: 21750, 4250. Cc: Animesh Manna Cc: Rodrigo Vivi Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 6 +++ drivers/gpu/drm/i915/intel_dp.c | 110 +- drivers/gpu/drm/i915/intel_hdmi.

Re: [Intel-gfx] [PATCH 01/10] drm/i915/icl: Fix power well anonymous union initializers

ris Wilson > Cc: Ville Syrjala > Cc: Paulo Zanoni With the checkpatch issues fixed: Reviewed-by: Paulo Zanoni > Cc: Jani Nikula > Signed-off-by: Imre Deak > --- > drivers/gpu/drm/i915/intel_runtime_pm.c | 22 +++--- > 1 file changed, 15 insertions(+), 7

Re: [Intel-gfx] [PATCH 02/10] drm/i915: Rename intel_power_domains_fini() to intel_power_domains_fini_hw()

eaner way. > > No functional change. > > Cc: Ville Syrjala > Cc: Paulo Zanoni With the checkpatch issues fixed: Reviewed-by: Paulo Zanoni > Cc: Jani Nikula > Signed-off-by: Imre Deak > --- > drivers/gpu/drm/i915/i915_drv.c | 4 +- > drivers/gpu/drm/i915/in

Re: [Intel-gfx] [PATCH 03/10] drm/i915/vlv: Remove redundant power well ID asserts

rpose. > (A follow-up patch removes power well IDs not needed for direct power > well access). > > Cc: Ville Syrjala > Cc: Paulo Zanoni Reviewed-by: Paulo Zanoni > Cc: Jani Nikula > Signed-off-by: Imre Deak > --- > drivers/gpu/drm/i915/intel_runtime_pm.c | 12

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