On Thu, 2019-04-04 at 14:20 -0700, Rodrigo Vivi wrote:
> On Thu, Apr 04, 2019 at 12:40:34PM -0700, Souza, Jose wrote:
> > On Wed, 2019-04-03 at 17:31 -0700, Rodrigo Vivi wrote:
> > > On Wed, Apr 03, 2019 at 04:35:38PM -0700, José Roberto de Souza
> > > wrote:
> > > > PSR is only supported in eDP tr
On Wed, 2019-04-17 at 15:37 -0700, José Roberto de Souza wrote:
> A new macro that is going to be added in a further patch will need to
> adjust the offset returned by _MMIO_TRANS2(), so here adding
> _TRANS2() and moving most of the implementation of _MMIO_TRANS2() to
> it and while at it taking t
On Wed, 2016-08-03 at 15:53 +0200, Takashi Iwai wrote:
> On Wed, 03 Aug 2016 04:14:30 +0200,
> Dhinakaran Pandiyan wrote:
> >
> > DP MST provides the capability to send multiple video and audio streams via
> > one single port. This requires the API's between i915 and audio drivers to
> > distingui
On Wed, 2016-08-03 at 22:08 +0300, Ville Syrjälä wrote:
> On Tue, Aug 02, 2016 at 07:14:30PM -0700, Dhinakaran Pandiyan wrote:
> > DP MST provides the capability to send multiple video and audio streams via
> > one single port. This requires the API's between i915 and audio drivers to
> > distingui
On Wed, 2016-08-03 at 23:28 +0300, Ville Syrjälä wrote:
> On Wed, Aug 03, 2016 at 07:43:06PM +0000, Pandiyan, Dhinakaran wrote:
> > On Wed, 2016-08-03 at 22:08 +0300, Ville Syrjälä wrote:
> > > On Tue, Aug 02, 2016 at 07:14:30PM -0700, Dhinakaran Pandiyan wrote:
> >
On Thu, 2016-08-04 at 15:49 +0300, Ville Syrjälä wrote:
> On Wed, Aug 03, 2016 at 09:42:53PM +0000, Pandiyan, Dhinakaran wrote:
> > On Wed, 2016-08-03 at 23:28 +0300, Ville Syrjälä wrote:
> > > On Wed, Aug 03, 2016 at 07:43:06PM +, Pandiyan, Dhinakaran wrote:
> > >
On Thu, 2016-08-04 at 10:46 +0300, Jani Nikula wrote:
> On Thu, 04 Aug 2016, Dhinakaran Pandiyan
> wrote:
> > A full dump of link status can be handy in debugging link training
> > failures. Let's add that to the debug messages when link training fails.
> >
> > Signed-off-by: Dhinakaran Pandiyan
On Thu, 2016-08-04 at 04:12 +0100, Chris Wilson wrote:
> On Wed, Aug 03, 2016 at 08:07:40PM -0700, Dhinakaran Pandiyan wrote:
> > The causes of clock recovery and channel equalization failures are not
> > explicitly printed in debug messages. Help debugging link training
> > failures by printing wh
On Thu, 2016-08-04 at 04:07 +0100, Chris Wilson wrote:
> On Wed, Aug 03, 2016 at 08:07:38PM -0700, Dhinakaran Pandiyan wrote:
> > @@ -2588,7 +2592,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
> > *DP |= DP_LINK_TRAIN_PAT_2_CPT;
> > break;
> >
ists.freedesktop.org
> > Cc: alsa-de...@alsa-project.org; ti...@suse.de; libin.y...@linux.intel.com;
> > Pandiyan, Dhinakaran
> > Subject: [Intel-gfx] [PATCH] drm/i915/dp: DP audio API changes for MST
> >
> > DP MST provides the capability to send multiple video
On Fri, 2016-08-05 at 06:21 +, Yang, Libin wrote:
> > -Original Message-
> > From: Pandiyan, Dhinakaran
> > Sent: Friday, August 5, 2016 1:57 PM
> > To: Yang, Libin
> > Cc: intel-gfx@lists.freedesktop.org; ti...@suse.de; alsa-devel@alsa-
> > pro
Cc: libin.y...@linux.intel.com; intel-gfx@lists.freedesktop.org; alsa-
> > de...@alsa-project.org; Pandiyan, Dhinakaran
> >
> > Subject: Re: [Intel-gfx] [PATCH] drm/i915/dp: DP audio API changes for MST
> >
> > On Thu, Aug 04, 2016 at 07:55:09PM +0200, Takashi I
On Tue, 2019-02-05 at 16:23 -0800, Souza, Jose wrote:
> On Tue, 2019-02-05 at 15:50 -0800, Dhinakaran Pandiyan wrote:
> > On Thu, 2019-01-31 at 17:59 -0800, José Roberto de Souza wrote:
> > > Changing the i915_edp_psr_debug was enabling, disabling or
> > > switching
> > > PSR version by directly ca
On Thu, 2019-02-14 at 15:19 -0800, Souza, Jose wrote:
> On Thu, 2019-02-14 at 11:00 -0800, Dhinakaran Pandiyan wrote:
> > On Wed, 2019-02-13 at 18:02 -0800, José Roberto de Souza wrote:
> > > As stated in CRC_CTL spec, after PSR entry state CRC will not be
> > > calculated anymore what is not a pro
On Fri, 2019-02-15 at 23:34 +0200, Ville Syrjälä wrote:
> On Fri, Feb 15, 2019 at 01:06:32PM -0800, Dhinakaran Pandiyan wrote:
> > On Fri, 2019-02-15 at 14:47 +0200, Ville Syrjälä wrote:
> > > On Thu, Feb 14, 2019 at 06:26:29PM -0800, Dhinakaran Pandiyan
> > > wrote:
> > > > On Thu, 2019-02-14 at 2
On Wed, 2019-02-13 at 18:02 -0800, José Roberto de Souza wrote:
> Forcing a specific CRTC to the eDP connector was causing the
> intel_psr_fastset_force() to mark mode_chaged in the wrong and
> disabled CRTC causing no update in the PSR state.
>
> Looks like our internal state track do not clear o
On Thu, 2019-02-28 at 17:14 -0800, Souza, Jose wrote:
> On Thu, 2019-02-28 at 17:06 -0800, Dhinakaran Pandiyan wrote:
> > On Thu, 2019-02-28 at 15:26 -0800, Souza, Jose wrote:
> > > On Thu, 2019-02-28 at 18:56 +0200, Ville Syrjälä wrote:
> > > > On Wed, Feb 27, 2019 at 05:32:57PM -0800, José Robert
On Mon, 2018-12-03 at 14:45 -0800, Souza, Jose wrote:
> On Mon, 2018-12-03 at 12:59 -0800, Dhinakaran Pandiyan wrote:
> > On Thu, 2018-11-29 at 18:25 -0800, José Roberto de Souza wrote:
> > > According to eDP spec, sink can required specific selective
> > > update
> > > granularity that source must
On Thu, 2019-03-07 at 14:53 -0800, Souza, Jose wrote:
> On Thu, 2019-03-07 at 12:26 -0800, Dhinakaran Pandiyan wrote:
> > On Tue, 2019-03-05 at 22:47 -0800, José Roberto de Souza wrote:
> > > If has_psr is set it means that CRTC has a EDP panel attached so
> > > it
> > > can be dropped, also has_ps
On Tue, 2019-03-12 at 14:28 -0700, Souza, Jose wrote:
> On Tue, 2019-03-12 at 14:14 -0700, Dhinakaran Pandiyan wrote:
> > On Tue, 2019-03-12 at 13:53 -0700, Rodrigo Vivi wrote:
> > > On Tue, Mar 12, 2019 at 01:42:17PM -0700, José Roberto de Souza
> > > wrote:
> > > > For some reason if the PSR1 EDP
Thanks for checking, appreciate it.
-DK
> -Original Message-
> From: Runyan, Arthur J
> Sent: Wednesday, March 20, 2019 11:58 AM
> To: Souza, Jose ; Vivi, Rodrigo
> ; Pandiyan, Dhinakaran
>
> Cc: Aigal, Pavana A ; 'intel-
> g...@lists.freedesktop.org'
On Mon, 2019-09-23 at 03:29 -0700, Dhinakaran Pandiyan wrote:
> Gen-12 display can decompress surfaces compressed by the media engine, add
> a new modifier as the driver needs to know the surface was compressed by
> the media or render engine.
>
> Cc: Nanley G Chery
> Cc: Matt Roper
> Cc: Ville
On Wed, 2019-10-02 at 15:29 -0700, Matt Roper wrote:
> On Mon, Sep 23, 2019 at 03:29:29AM -0700, Dhinakaran Pandiyan wrote:
> > Easier to read if all the alignment changes are in one place and contained
> > within a function.
> >
> > Cc: Ville Syrjälä
> > Cc: Matt Roper
> > Signed-off-by: Dhinak
On Tue, 2019-07-16 at 15:03 -0700, Dhinakaran Pandiyan wrote:
> A single 32-bit PSR2 training pattern field follows the sixteen element
> array of PSR table entries in the VBT spec. But, we incorrectly define
> this PSR2 field for each of the PSR table entries. As a result, the PSR1
> training patt
On Wed, 2019-07-17 at 14:35 +0300, Ville Syrjälä wrote:
> On Tue, Jul 16, 2019 at 03:03:21PM -0700, Dhinakaran Pandiyan wrote:
> > A single 32-bit PSR2 training pattern field follows the sixteen element
> > array of PSR table entries in the VBT spec. But, we incorrectly define
> > this PSR2 field f
> -Original Message-
> From: Greg KH [mailto:gre...@linuxfoundation.org]
> Sent: Tuesday, July 30, 2019 10:09 AM
> To: Vivi, Rodrigo
> Cc: Nikula, Jani ; Joonas Lahtinen
> ; Souza, Jose ;
> sas...@kernel.org; intel-gfx@lists.freedesktop.org; sta...@vger.k
On Wed, 2017-12-06 at 23:16 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/5] drm/vblank: Do not update vblank counts if
> vblanks are already disabled.
> URL : https://patchwork.freedesktop.org/series/34996/
> State : failure
>
> == Summary ==
>
> Serie
On Wed, 2017-12-06 at 23:16 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/5] drm/vblank: Do not update vblank counts if
> vblanks are already disabled.
> URL : https://patchwork.freedesktop.org/series/34996/
> State : failure
>
> == Summary ==
>
> Serie
On Wed, 2017-12-06 at 23:16 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/5] drm/vblank: Do not update vblank counts if
> vblanks are already disabled.
> URL : https://patchwork.freedesktop.org/series/34996/
> State : failure
>
> == Summary ==
>
> Serie
On Wed, 2017-12-06 at 15:54 -0800, Rodrigo Vivi wrote:
> On Wed, Dec 06, 2017 at 10:47:40PM +, Dhinakaran Pandiyan wrote:
> > When DC states are enabled and PSR is active, the hardware enters DC5/DC6
> > states resulting in frame counter resets. The frame counter resets mess
> > up the vblan
On Fri, 2017-12-08 at 23:37 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Prevent the DMC from destroying GMBUS transfers on GLK. GMBUS
> lives in PG1 so DC off is all we need.
>
Just so that I understand this correctly. DMC is expected to take care
of managing power for GMBUS transfers
On Mon, 2017-12-11 at 09:06 +, Chris Wilson wrote:
> Fixes: ba86514759c6 ("kms_vblank: Switch from using crtc0 statically to
> explicitly setting mode.")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104208
Reviewed-by: Dhinakaran Pandiyan
What do you think of verifying the driv
On Fri, 2017-12-08 at 23:37 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Gen9+ need to disable GMBUS clock gating when doing multi part
> transfers. Otherwise clock gating will kick in when GMBUS is in
> the WAIT state and presumably that will corrupt the transfer.
> This is documented a
and 2 are
Reviewed-by: Dhinakaran Pandiyan
> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Monday, 11 December, 2017 11:03 AM
> To: Pandiyan, Dhinakaran
> Cc: intel-gfx@lists.freedesktop.org; sta...@vger.kernel.org; Runyan, Arthur J
>
On Tue, 2017-12-12 at 09:10 +0200, Ville Syrjälä wrote:
> On Mon, Dec 11, 2017 at 06:06:57PM -0800, Dhinakaran Pandiyan wrote:
> > PSR allows DMC to put the system to low power states when active, but
> > this can reset the frame counter on some platforms. The frame counter reset
> > leads to a neg
On Thu, 2017-12-14 at 17:06 +0200, Ville Syrjälä wrote:
> On Tue, Dec 12, 2017 at 04:59:34PM -0800, Dhinakaran Pandiyan wrote:
> > Since commit 4d90f2d507ab ("drm/i915: Start tracking PSR state in crtc
> > state"), we check whether PSR can be enabled or not in
> > psr_compute_config(). Given that
On Wed, 2017-12-13 at 18:28 +, Chris Wilson wrote:
> Just printk the string, or at least do not double up on the newlines!
>
Reviewed-by: Dhinakaran Pandiyan
> Fixes: eef57324d926 ("drm/i915: setup bridge for HDMI LPE audio driver")
> Signed-off-by: Chris Wilson
> Cc: Pierre-Louis Bossart
On Thu, 2017-12-14 at 21:30 +0100, Daniel Vetter wrote:
> DK put some nice docs into the commit introducing driver private
> state, but in the git history alone it'll be lost.
>
> Also, since Ville remove the void* usage it's a good opportunity to
> give the driver private stuff some tlc on the d
On Tue, 2017-12-19 at 13:29 -0800, Rodrigo Vivi wrote:
> On Tue, Dec 19, 2017 at 05:26:54AM +, Dhinakaran Pandiyan wrote:
> > DPCD read for the eDP is complete by the time intel_psr_init() is
> > called, which means we can avoid initializing PSR structures and state
> > if there is no sink s
On Tue, 2017-12-19 at 13:54 -0800, Rodrigo Vivi wrote:
> On Wed, Dec 13, 2017 at 07:23:45PM +, Dhinakaran Pandiyan wrote:
> > PSR allows DMC to put the system to low power states when active, but
> > this can reset the frame counter on some platforms. The frame counter reset
> > leads to a n
On Tue, 2017-12-19 at 13:41 -0800, Rodrigo Vivi wrote:
> On Tue, Dec 19, 2017 at 05:26:58AM +, Dhinakaran Pandiyan wrote:
> > When DC states are enabled and PSR is active, the hardware enters DC5/DC6
> > states resulting in frame counter resets. The frame counter resets mess
> > up the vblan
On Tue, 2017-12-19 at 14:01 -0800, Rodrigo Vivi wrote:
> On Tue, Dec 12, 2017 at 09:52:09PM +, Dhinakaran Pandiyan wrote:
> > The POWER_DOMAIN_INIT bit is already set in _POWERWELL_2_POWER_DOMAINS,
> > which is included in _DC_OFF_POWER_DOMAINS. So, avoid setting that again
> > in _DC_OFF_PO
On Wed, 2017-12-20 at 09:24 +, Chris Wilson wrote:
> Quoting Dhinakaran Pandiyan (2017-12-20 04:35:20)
> > Commit 77affa31722b ("drm/i915/psr: Fix compiler warnings for
> > hsw_psr_disable()") swapped status and control registers while fixing
> > indentation. The _ctl at the end of the statu
On Thu, 2017-12-21 at 08:53 +0200, Jani Nikula wrote:
> On Wed, 20 Dec 2017, Dhinakaran Pandiyan
> wrote:
> > Occasionally there are LINK_ADDRESS sideband messages timing out with the
> > Lenovo MST dock + Dell MST monitor(w/ in-built branch) setup I have. These
> > failures lead to the display n
On Thu, 2017-12-21 at 10:52 -0800, Manasi Navare wrote:
> On Wed, Dec 20, 2017 at 10:36:24PM -0800, Dhinakaran Pandiyan wrote:
> > Occasionally there are LINK_ADDRESS sideband messages timing out with the
> > Lenovo MST dock + Dell MST monitor(w/ in-built branch) setup I have. These
> > failures le
On Thu, 2017-12-21 at 13:37 +0100, Maarten Lankhorst wrote:
> Hey,
>
> Op 19-12-17 om 06:26 schreef Dhinakaran Pandiyan:
> > Convert the power_domains->domain_use_count array that tracks per-domain
> > use count to atomic_t type. This is needed to be able to read/write the use
> > counts outside
On Fri, 2017-12-22 at 00:48 +, Pandiyan, Dhinakaran wrote:
> On Thu, 2017-12-21 at 08:53 +0200, Jani Nikula wrote:
> > On Wed, 20 Dec 2017, Dhinakaran Pandiyan
> > wrote:
> > > Occasionally there are LINK_ADDRESS sideband messages timing out with the
> >
On Fri, 2017-12-22 at 15:18 -0800, Rodrigo Vivi wrote:
> Some Cannonlake SKUs will come with a full split between
> port A and port E. This will be called port F although it
> is not a 6th port, but only a split.
I am not sure if this is said in this spec.
From to what I can read and understand
On Fri, 2017-12-22 at 15:18 -0800, Rodrigo Vivi wrote:
> This was wrong since its introduction on commit '04416108ccea
> ("drm/i915/cnl: Add registers related to voltage swing sequences.")'
>
> But since no Port F was needed so far we don't need to
> propagate fixes back there.
>
Checked agains
On Fri, 2017-12-22 at 15:18 -0800, Rodrigo Vivi wrote:
> SKUs that lacks on the full port F split will just time out
> when touching this power well bits, causing a noisy warn.
Shouldn't be this be squashed with [PATCH 09/11] in that case? Why
introduce a WARN and then fix it.
>
> This macr
On Fri, 2017-12-22 at 15:18 -0800, Rodrigo Vivi wrote:
> On some Cannonlake SKUs we have a dedicated Aux for port F,
> that is only the full split between port A and port E.
>
> There is still no Aux E for Port E, as in previous platforms,
> because port_E still means shared lanes with port A.
On Fri, 2017-12-22 at 15:18 -0800, Rodrigo Vivi wrote:
> Since when it got introduced with commit '555e38d27317
> ("drm/i915/cnl: DDI - PLL mapping")' the support for Port F
> was wrong, because Port F bits are far from bits used
> for A to E.
>
> Since Port F is not used so far we don't need t
On Tue, 2017-12-19 at 13:16 +0100, Maarten Lankhorst wrote:
> This should get rid of unclaimed register debug warnings, if
> it still happens we should put this in a intel_crtc->active check..
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104172
The bugzilla indicates this is a reg
On Tue, 2018-01-02 at 18:33 +, Pandiyan, Dhinakaran wrote:
> On Tue, 2017-12-19 at 13:16 +0100, Maarten Lankhorst wrote:
> > This should get rid of unclaimed register debug warnings, if
> > it still happens we should put this in a intel_crtc->active check..
> &
On Thu, 2018-01-04 at 00:48 +0530, Gaurav K Singh wrote:
> From: Gaurav Singh
>
> On Apollolake, with stress test warm reboot, audio card
> was not getting enumerated after reboot. This was a
The problem looks similar to
https://lists.freedesktop.org/archives/intel-gfx/2017-October/144495.html
On Wed, 2018-01-03 at 13:59 -0800, Rodrigo Vivi wrote:
> first of all sorry for not getting back sooner on this...
>
> On Tue, Dec 19, 2017 at 09:40:01PM +, Pandiyan, Dhinakaran wrote:
> >
> >
> >
> > On Tue, 2017-12-19 at 13:29 -0800, Rodrigo Vivi wro
On Wed, 2018-01-03 at 20:57 +, Chris Wilson wrote:
> Quoting Dhinakaran Pandiyan (2018-01-03 20:39:59)
> > Since we want to allow for a non-blocking power domain for vblanks,
> > the power domain use count and power well use count will not be updated
> > atomically inside the power domain mut
On Thu, 2018-01-04 at 12:35 +0100, Maarten Lankhorst wrote:
> Wouldn't it be better to make intel_power_domains_verify_state work
> correctly with the vblank irq?
I tried to :) Since I changed the domain_use_count to atomic_t and moved
it outside of the locks, verify_state became racy. Let me tak
+Art
On Thu, 2018-01-04 at 22:13 +0530, Singh, Gaurav K wrote:
>
> On 1/4/2018 2:48 AM, Rodrigo Vivi wrote:
> > On Wed, Jan 03, 2018 at 08:31:10PM +0000, Pandiyan, Dhinakaran wrote:
> >> On Thu, 2018-01-04 at 00:48 +0530, Gaurav K Singh wrote:
> >>> From: Gaurav
On Thu, 2018-01-04 at 06:36 +, Mustaffa, Mustamin B wrote:
> Hi all,
>
>
>
> Please help to review a patch
> https://patchwork.freedesktop.org/patch/160274/
>
>
That patch is several months old now, please resubmit the patch to the
mailing list. I see that there were comments from Jan
Including a line about the atomic update failure in the commit message
would be nice.
Reviewed-by: Dhinakaran Pandiyan
On Thu, 2018-01-04 at 16:07 +0200, Marta Lofstedt wrote:
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104260
>
> Signed-off-by: Marta Lofstedt
> ---
> tests/kms_
On Thu, 2018-01-04 at 18:21 -0500, Lyude Paul wrote:
> Sorry for the late reply, I've been having very similar issues on my own MST
> hub
> and I wanted to make sure that they were the same issue, although it seems
> like
> they aren't.
>
> So; I've been doing a lot of MST debugging this week a
On Thu, 2018-01-04 at 23:46 +, Pandiyan, Dhinakaran wrote:
> On Thu, 2018-01-04 at 18:21 -0500, Lyude Paul wrote:
> > Sorry for the late reply, I've been having very similar issues on my own
> > MST hub
> > and I wanted to make sure that they were the sam
On Fri, 2018-01-05 at 10:09 -0800, Rodrigo Vivi wrote:
> On Fri, Jan 05, 2018 at 11:23:54AM +, Maarten Lankhorst wrote:
> > Op 04-01-18 om 22:51 schreef Pandiyan, Dhinakaran:
> > > On Thu, 2018-01-04 at 12:35 +0100, Maarten Lankhorst wrote:
> > >>
On Mon, 2018-01-08 at 15:43 +0100, Maarten Lankhorst wrote:
> Op 06-01-18 om 10:51 schreef Dhinakaran Pandiyan:
> > On Thursday, January 4, 2018 12:35:48 PM PST Maarten Lankhorst wrote:
> >> Op 03-01-18 om 21:39 schreef Dhinakaran Pandiyan:
> >>> Since we want to allow for a non-blocking power doma
On Thu, 2018-01-04 at 18:08 -0800, Rodrigo Vivi wrote:
> On Wed, Jan 03, 2018 at 08:40:00PM +, Dhinakaran Pandiyan wrote:
> > When DC states are enabled and PSR is active, the hardware enters DC5/DC6
> > states resulting in the frame counter resetting. The frame counter reset
> > mess up the v
On Mon, 2018-04-30 at 23:39 +, Souza, Jose wrote:
> On Thu, 2018-04-26 at 15:51 -0700, Dhinakaran Pandiyan wrote:
> >
> >
> >
> > On Wed, 2018-04-18 at 15:43 -0700, José Roberto de Souza wrote:
> > >
> > > This reduces the spaghetti that intel_dp_aux_xfer().
> > >
> > > Moved doing less ch
On Fri, 2016-08-05 at 10:35 +0100, Chris Wilson wrote:
> On Thu, Aug 04, 2016 at 01:48:36PM -0700, Dhinakaran Pandiyan wrote:
> > A full dump of link status can be handy in debugging link training
> > failures. Let's add that to the debug messages when link training fails.
> >
> > v2: Removing unr
Thanks Lyude. I realized that after sending the patches, will fix that.
On Thu, 2016-08-04 at 19:42 -0400, Lyude wrote:
> This should be added after patch #3, since that's the one that fixes
> enc_to_mst(). Otherwise:
>
> Reviewed-by: Lyude
>
> On Tue, 2016-08-02 at 18:46 -0700, Dhinakaran Pand
On Thu, 2016-08-04 at 19:51 -0400, Lyude wrote:
> There was some discussion that happened on the original version of this
> patch:
>
> https://patchwork.kernel.org/patch/8960831/
>
> The general consensus was while this fixed the issue, it probably isn't
> the way we want to fix it. It would be a
On Fri, 2016-08-05 at 18:49 +0100, Chris Wilson wrote:
> On Fri, Aug 05, 2016 at 08:41:34PM +0300, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > intel_enable_pipe() looks rather confusing when one side doesn't have
> > the curly braces, and the other one does. And what's ev
On Wed, 2016-08-03 at 14:44 +, Vivi, Rodrigo wrote:
> On Wed, 2016-08-03 at 10:31 +0300, Ville Syrjälä wrote:
> > On Tue, Aug 02, 2016 at 09:42:07PM -0700, Rodrigo Vivi wrote:
> > >
> > > A read(fd, buf, len) function should return the number
> > > of bytes read. In our case we need to return
On Tue, 2016-08-09 at 23:08 +0100, Chris Wilson wrote:
> On Tue, Aug 09, 2016 at 03:06:10PM -0700, Dhinakaran Pandiyan wrote:
> > No functional change, just adding braces to all branches of conditional
> > statement because one of them already had.
> > ---
> > drivers/gpu/drm/i915/intel_audio.c |
On Wed, 2016-08-10 at 17:21 +0300, Ville Syrjälä wrote:
> On Tue, Aug 09, 2016 at 01:58:33PM -0700, Dhinakaran Pandiyan wrote:
> > DP MST provides the capability to send multiple video and audio streams
> > through a single port. This requires the API's between i915 and audio
> > drivers to disting
On Thu, 2016-08-11 at 09:26 +0300, Ville Syrjälä wrote:
> On Wed, Aug 10, 2016 at 12:41:57PM -0700, Dhinakaran Pandiyan wrote:
> > DP MST provides the capability to send multiple video and audio streams
> > through a single port. This requires the API's between i915 and audio
> > drivers to disting
On Thu, 2016-08-11 at 08:09 +0100, Chris Wilson wrote:
> On Wed, Aug 10, 2016 at 11:41:13PM -0700, Dhinakaran Pandiyan wrote:
> > No functional change, just clean up.
> >
> > Signed-off-by: Dhinakaran Pandiyan
> Reviewed-by: Chris Wilson
>
> A quick conversion to kernel types would also be appr
On Thu, 2016-08-11 at 10:52 +0300, Jani Nikula wrote:
> On Thu, 11 Aug 2016, Dhinakaran Pandiyan
> wrote:
> > No functional change, just clean up. Debug messages now print out clock
> > units. Additionally, the configuration bits, which are 1:1 mapped to the
> > clock frequency and don't convey m
On Thu, 2016-08-11 at 15:23 -0700, Manasi Navare wrote:
> Intel_dp_link_is_valid() function reads the Link status registers
> and returns a boolean to indicate link is valid or not.
> If the link has lost lock and is not valid any more, link
> training is performed outside the function else previou
On Thu, 2016-08-11 at 16:41 -0700, Anusha Srivatsa wrote:
> drm/dp/mst
>
> Signed-off-by: Anusha Srivatsa
>
> Add a function that returns the available link bandwidth for
> MST port so that we can accurately determine whether a new
> mode is valid for the link or not.
>
The Signed-off line sho
On Thu, 2016-08-11 at 16:41 -0700, Anusha Srivatsa wrote:
> drm/dp/mst/i915
>
> Signed-off-by: Anusha Srivatsa
>
> Validate the modes against available link bandwidth rather than
> maximum link bandwidth so that we have a better idea as to whether
> a proposed mode can truly run beside existing
On Thu, 2016-08-11 at 10:39 +0300, Ville Syrjälä wrote:
> On Thu, Aug 11, 2016 at 07:10:39AM +0000, Pandiyan, Dhinakaran wrote:
> > On Thu, 2016-08-11 at 09:26 +0300, Ville Syrjälä wrote:
> > > On Wed, Aug 10, 2016 at 12:41:57PM -0700, Dhinakaran Pandiyan wrote:
> >
On Fri, 2016-08-12 at 10:56 -0700, Manasi Navare wrote:
> On Thu, Aug 11, 2016 at 08:18:54PM -0700, Pandiyan, Dhinakaran wrote:
> > On Thu, 2016-08-11 at 15:23 -0700, Manasi Navare wrote:
> > > Intel_dp_link_is_valid() function reads the Link status registers
> > &g
On Fri, 2016-06-10 at 22:18 -0300, Paulo Zanoni wrote:
> Ever since I started working on FBC I was already aware that FBC can
> really amplify the FIFO underrun symptoms. On systems where FIFO
> underruns were harmless error messages, enabling FBC would cause the
> underruns to give black screens.
On Fri, 2016-08-12 at 08:18 +0300, Ville Syrjälä wrote:
> On Fri, Aug 12, 2016 at 04:28:09AM +0000, Pandiyan, Dhinakaran wrote:
> > On Thu, 2016-08-11 at 10:39 +0300, Ville Syrjälä wrote:
> > > On Thu, Aug 11, 2016 at 07:10:39AM +, Pandiyan, Dhinakaran wrote:
> > >
On Sat, 2016-08-13 at 00:16 +, Pandiyan, Dhinakaran wrote:
> On Fri, 2016-08-12 at 08:18 +0300, Ville Syrjälä wrote:
> > On Fri, Aug 12, 2016 at 04:28:09AM +, Pandiyan, Dhinakaran wrote:
> > > On Thu, 2016-08-11 at 10:39 +0300, Ville Syrjälä wrote:
> > > >
Please ignore this, I am resubmitting this as an independent patch.
-DK
On Thu, 2016-08-11 at 13:49 -0700, Dhinakaran Pandiyan wrote:
> Since a DRM function that reads link DP link status is available, let's
> use that instead of the i915 clone.
>
> drm_dp_dpcd_read_link_status() returns a negati
On Thu, 2016-08-18 at 21:39 -0700, Rodrigo Vivi wrote:
> On Mon, Aug 15, 2016 at 05:00:53PM -0700, Dhinakaran Pandiyan wrote:
> > There are places in the driver where we just need the 'port' associated
> > with an encoder and not 'struct intel_digital_port' that contains it.
> > This basically is a
On Fri, 2016-08-19 at 10:02 +0200, Daniel Vetter wrote:
> On Mon, Aug 15, 2016 at 05:00:53PM -0700, Dhinakaran Pandiyan wrote:
> > There are places in the driver where we just need the 'port' associated
> > with an encoder and not 'struct intel_digital_port' that contains it.
> > This basically is
On Wed, 2016-08-24 at 08:08 +0200, Daniel Vetter wrote:
> On Tue, Aug 23, 2016 at 01:49:17PM -0700, Dhinakaran Pandiyan wrote:
> > Storing the port enum in intel_encoder makes it convenient to know the
> > port attached to an encoder. Moving the port information up from
> > intel_digital_port to in
IRC acked-by: Daniel Vetter
On Wed, 2016-08-24 at 00:22 -0700, Dhinakaran Pandiyan wrote:
> Storing the port enum in intel_encoder makes it convenient to know the
> port attached to an encoder. Moving the port information up from
> intel_digital_port to intel_encoder avoids unecessary intel_digit
Confirmed on IRC, Lyude is fine with carrying over R-B from previous
version.
On Wed, 2016-08-24 at 00:22 -0700, Dhinakaran Pandiyan wrote:
> With DP MST, a digital_port can carry more than one audio stream. Hence,
> more than one audio_connector needs to be attached to intel_digital_port in
> su
Just realized this patch needs s/attached_port/port, will send out
another version.
On Mon, 2016-08-29 at 17:23 -0400, Lyude Paul wrote:
> Looks like a much better solution then the previous one.
>
> Reviewed-by: Lyude
>
> On Wed, 2016-08-24 at 00:22 -0700, Dhinakaran Pandiyan wrote:
> > Now t
The changes in this version are primarily in i915. I have carried over
Takashi's R-B from the previous version and removed Ville's.
____
From: Pandiyan, Dhinakaran
Sent: Thursday, September 01, 2016 12:50 AM
To: intel-gfx@lists.freedesktop.org
C
On Mon, 2016-08-15 at 19:36 -0300, Paulo Zanoni wrote:
> Ever since I started working on FBC I was already aware that FBC can
> really amplify the FIFO underrun symptoms. On systems where FIFO
> underruns were harmless error messages, enabling FBC would cause the
> underruns to give black screens.
On Fri, 2016-09-02 at 12:16 +0300, Mika Kahola wrote:
> On Thu, 2016-09-01 at 15:08 -0700, Manasi Navare wrote:
> > From: Dhinakaran Pandiyan
> >
> > This function cleans up clock recovery loop in link training
> > compliant
> > tp Dp Spec 1.2. It tries the clock recovery 5 times for the same
> >
On Fri, 2016-09-02 at 14:20 +0300, Mika Kahola wrote:
> On Thu, 2016-09-01 at 15:08 -0700, Manasi Navare wrote:
> > Fix the number of tries in channel euqalization link training
> > sequence
> > according to DP 1.2 Spec. It returns a boolean depending on channel
> > equalization pass or failure.
>
On Thu, 2016-09-01 at 15:08 -0700, Manasi Navare wrote:
> According to the DisplayPort Spec, in case of Clock Recovery failure
> the link training sequence should fall back to the lower link rate
> followed by lower lane count until CR succeeds.
> On CR success, the sequence proceeds with Channel E
On Thu, 2016-09-01 at 15:08 -0700, Manasi Navare wrote:
> From: Jim Bride
>
> Add the PLL selection code for HSW/BDW/BXT/SKL into a stand-alone function
> in order to allow for the implementation of a platform neutral upfront
> link training function.
>
> v3:
> * Add Hooks for all DDI platforms
On Thu, 2016-09-01 at 15:08 -0700, Manasi Navare wrote:
> While configuring the pipe during modeset, it should loop
> starting from max clock and max lane count reducing the
> lane count and clock in each iteration until the requested mode
> rate is less than or equal to available link BW.
>
> Sig
> -Original Message-
> From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> Sent: Friday, October 26, 2018 7:46 AM
> To: Pandiyan, Dhinakaran
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 2/2] drm/i915: Reuse plane format modifier checks
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