Different GENs have a different ACK register. Use the correct
one for each case.
Suggested-by: Paulo Zanoni
Signed-off-by: Oscar Mateo
Cc: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_debugfs.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu
This register does not contain it. Instead, we have to look into
FAULT_TLB_DATA0 & 1
(where, by the way, we can also get the address space).
Fixes: b03ec3d67ab8 ("drm/i915: There is only one fault register from GEN8
onwards")
Signed-off-by: Oscar Mateo
Cc: Michel Thierry
Cc
ting, this time for real
Fixes: b03ec3d67ab8 ("drm/i915: There is only one fault register from GEN8
onwards")
Signed-off-by: Oscar Mateo
Cc: Michel Thierry
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 15 +--
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 fil
c: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
drivers/gpu/drm/i915/intel_workarounds.c | 7 +++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cfb9b0d..fca1
Revert to the legacy implementation to avoid a system hang.
v2: Correct the address for GAMW_ECO_DEV_RW_IA_REG
v3: Renamed to Wa_220166154
v4: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu
The default GAPZ arbitrer priority value at power-on has been found
to be incorrect.
v2: Now renamed to Wa_1405543622
v3: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
drivers/gpu/drm/i915
Required for Bindless samplers.
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
v2: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm
Redirects the state cache to the CS Command buffer section for
performance reasons.
v2: Rebased
v3: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_workarounds.c | 4
2 files
Disable blend embellishment in RCC.
v2: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 18 +++---
drivers/gpu/drm/i915/intel_workarounds.c | 5 +
2 files changed, 16 insertions(+), 7 deletions
This workarounds an issue with insufficient storage for the
CL2 and SF units.
v2: Renamed to Wa_1405766107
v3: Wrapped the commit message
v4: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu
Disable GWL clock gating to prevent two different issues that
might cause hangs.
Please notice that one of the issues is pre-production only.
v2: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
1 file
Kamble
Cc: Praveen Paneri
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 4
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index
Revert to an L3 non-hash model, for performance reasons.
v2:
- Place the WA name above the actual change
- Improve the register naming
v3:
- Rebased
- Renamed to Wa_1604223664
v4: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm
Avoids an undefined LLC behavior.
BSpec: 9613
v2: Renamed to Wa_1405733216
v3: Spaces around '<<' and fix surrounding code
v4: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
driv
icelake_init_clock_gating()
from Paulo Zanoni
- Squashed with this patch:
drm/i915/icl: WaForceEnableNonCoherent
from Oscar Mateo
- WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
applies to B0 as well.
- WaPipeControlBefore3DStateSamplePattern WABB was being
Enables blend optimization for floating point RTs
v2: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a
WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 8
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index
a Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_workarounds.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 9e50fba..970a763 100644
--- a/drivers/gpu/drm/i915/intel_workaroun
Adjust default GAM TLB partitioning for performance reasons.
v2: Only touch the bits that we really need
v3: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_workarounds.c | 5
Disable CGPSF unit clock gating to prevent an issue.
v2: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 13 -
drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
2 files changed, 14 insertions
of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_workarounds.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 43dbeed..8a76bc4 100644
--- a/drive
Disable I2M Write for performance reasons.
v2: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
drivers/gpu/drm/i915/intel_workarounds.c | 5 +
2 files changed, 8 insertions(+), 1 deletion(-)
diff
Disable MSC clock gating to prevent data corruption.
BSpec: 19257
v2: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
2 files changed, 7 insertions
Avoids a hang during soft reset.
v2: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_workarounds.c | 8
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm
of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_workarounds.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 970a763..43dbeed 100644
--- a/drive
that list against
the hw.
v2: Filter out pre-gen8 as they do not have RING_NONPRIV.
Signed-off-by: Chris Wilson
Cc: Oscar Mateo
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/i915_debugfs.c | 14 +-
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gp
On 4/13/2018 9:54 AM, Chris Wilson wrote:
Quoting Oscar Mateo (2018-04-13 17:46:42)
On 4/12/2018 8:21 AM, Chris Wilson wrote:
Add a selftest to ensure that we restore the whitelisted registers after
rewrite the registers everytime they might be scrubbed, e.g. module
load, reset and resume
quot;)
Signed-off-by: Oscar Mateo
Cc: Chris Wilson
---
drivers/gpu/drm/i915/selftests/intel_workarounds.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/intel_workarounds.c
b/drivers/gpu/drm/i915/selftests/intel_workarounds.c
index fe7deca..5455b26 1006
:
- use fls() instead of find_last_bit() (Chris)
- added INTEL_SSEU to extract sseu from device info. (Chris)
v3:
- rebase on latest tip
v5:
- Added references (Mika)
- Change the ordered of passing arguments and etc. (Ursulin)
v7:
- Rebased.
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Joonas
more local variables for clearer
logic (Ursulin)
v7:
- Rebased.
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Signed-off-by: Yunwei Zhang
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915
instead of calculate on the run. (Oscar)
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Signed-off-by: Yunwei Zhang
Reviewed-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_device_info.c | 33
more local variables for clearer
logic (Ursulin)
v7:
- Rebased.
v8:
- Reviewed by Oscar.
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Signed-off-by: Yunwei Zhang
Reviewed-by: Oscar Mateo
---
drivers/gpu/drm/i915
On 4/17/2018 2:34 PM, Oscar Mateo wrote:
On 4/17/2018 2:05 PM, Yunwei Zhang wrote:
WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any
MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice
instead of calculate on the run. (Oscar)
v9:
- Changed naming and label fixes. (Oscar)
- Store only the selector instead of whole MCR. (Oscar)
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Signed-off-by: Yunwei Zhang
more local variables for clearer
logic (Ursulin)
v7:
- Rebased.
v8:
- Reviewed by Oscar.
v9:
- Fixed label location. (Oscar)
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Signed-off-by: Yunwei Zhang
Reviewed-by: Oscar
On 4/18/2018 9:38 AM, Chris Wilson wrote:
Quoting Oscar Mateo (2018-04-18 17:30:41)
On 4/17/2018 3:58 PM, Yunwei Zhang wrote:
+ /*
+ * HW expects MCR to be programed to a enabled slice/subslice pair
+ * before any MMIO read into slice/subslice register
+ */
The comment
On 4/18/2018 9:45 AM, Oscar Mateo wrote:
On 4/18/2018 9:38 AM, Chris Wilson wrote:
Quoting Oscar Mateo (2018-04-18 17:30:41)
On 4/17/2018 3:58 PM, Yunwei Zhang wrote:
+ /*
+ * HW expects MCR to be programed to a enabled slice/subslice
pair
+ * before any MMIO read into
On 4/18/2018 9:40 AM, Oscar Mateo wrote:
On 4/17/2018 3:59 PM, Yunwei Zhang wrote:
L3Bank could be fused off in hardware for debug purpose, and it
is possible that subslice is enabled while its corresponding L3Bank
pairs
are disabled. In such case, if MCR packet control register(0xFDC) is
instead of calculate on the run. (Oscar)
v9:
- Changed naming and label fixes. (Oscar)
- Store only the selector instead of whole MCR. (Oscar)
v10:
- Improved comments, naming and line breaknig. (Oscar)
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Mika
more local variables for clearer
logic (Ursulin)
v7:
- Rebased.
v8:
- Reviewed by Oscar.
v9:
- Fixed label location. (Oscar)
v10:
- Improved comments and replaced magical number. (Oscar)
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Joonas Lahtinen
Cc: Chris Wilson
Cc: Mika Kuoppala
Cc
instead of calculate on the run. (Oscar)
v9:
- Changed naming and label fixes. (Oscar)
- Store only the selector instead of whole MCR. (Oscar)
v10:
- Improved comments, naming and line breaknig. (Oscar)
v11:
- Moved the comment to most relavent block. (Oscar)
Cc: Oscar Mateo
Cc: Michel
Disable blend embellishment in RCC.
v2: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 18 +++---
drivers/gpu/drm/i915/intel_workarounds.c | 5 +
2 files changed, 16 insertions(+), 7 deletions
Redirects the state cache to the CS Command buffer section for
performance reasons.
v2: Rebased
v3: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_workarounds.c | 4
2 files
Avoids a hang during soft reset.
v2: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_workarounds.c | 8
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm
Avoids an undefined LLC behavior.
BSpec: 9613
v2: Renamed to Wa_1405733216
v3: Spaces around '<<' and fix surrounding code
v4: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
driv
Disable CGPSF unit clock gating to prevent an issue.
v2: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 13 -
drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
2 files changed, 14 insertions
WA refactoring
v4: Rebased on top of whitelist reg refactoring (Michel)
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 4
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915
Adjust default GAM TLB partitioning for performance reasons.
v2: Only touch the bits that we really need
v3: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_workarounds.c | 5
List of GT workarounds for Icelake that we have been carrying in internal.
Can we get eyes on these please?
Oscar Mateo (22):
drm/i915/icl: Introduce initial Icelake Workarounds
drm/i915/icl: Enable Sampler DFR
drm/i915/icl: WaGAPZPriorityScheme
drm/i915/icl: WaL3BankAddressHashing
drm
Disable GWL clock gating to prevent two different issues that
might cause hangs.
Please notice that one of the issues is pre-production only.
v2: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
1 file
icelake_init_clock_gating()
from Paulo Zanoni
- Squashed with this patch:
drm/i915/icl: WaForceEnableNonCoherent
from Oscar Mateo
- WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
applies to B0 as well.
- WaPipeControlBefore3DStateSamplePattern WABB was being
Required for Bindless samplers.
Do Linux UMDs make use of this? This change has been security
reviewed and the whitelisting approved. Virtualization of other
OSes could certainly use it.
v2: Rebased on top of the WA refactoring (Michel)
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
on top of the WA whitelist reg refactoring (Michel)
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_workarounds.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 5abd53
Enables blend optimization for floating point RTs
v2: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a
The default GAPZ arbitrer priority value at power-on has been found
to be incorrect.
v2: Now renamed to Wa_1405543622
v3: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
drivers/gpu/drm/i915
This workarounds an issue with insufficient storage for the
CL2 and SF units.
v2: Renamed to Wa_1405766107
v3: Wrapped the commit message
v4: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu
Paneri
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
Reviewed-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_workarounds.c | 4
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915
of the WA refactoring
v4: Rebased on top of whitelist reg refactoring (Michel)
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gp
c: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
drivers/gpu/drm/i915/intel_workarounds.c | 7 +++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cfb9b0d..fca1
Revert to an L3 non-hash model, for performance reasons.
v2:
- Place the WA name above the actual change
- Improve the register naming
v3:
- Rebased
- Renamed to Wa_1604223664
v4: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm
Revert to the legacy implementation to avoid a system hang.
v2: Correct the address for GAMW_ECO_DEV_RW_IA_REG
v3: Renamed to Wa_220166154
v4: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu
Disable I2M Write for performance reasons.
v2: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
drivers/gpu/drm/i915/intel_workarounds.c | 5 +
2 files changed, 8 insertions(+), 1 deletion(-)
diff
of the WA refactoring
v4: Rebased on top of the whitelist reg refactoring (Michel)
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gp
Disable MSC clock gating to prevent data corruption.
BSpec: 19257
v2: Rebased on top of the WA refactoring
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_workarounds.c | 6 ++
2 files changed, 7 insertions
On 04/20/2018 01:46 PM, Rodrigo Vivi wrote:
On Fri, Apr 20, 2018 at 01:33:54PM -0700, Oscar Mateo wrote:
Disable GWL clock gating to prevent two different issues that
might cause hangs.
Please notice that one of the issues is pre-production only.
v2: Rebased on top of the WA refactoring
Cc
On 04/20/2018 01:48 PM, Rodrigo Vivi wrote:
On Fri, Apr 20, 2018 at 01:33:46PM -0700, Oscar Mateo wrote:
Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
power by dynamically changing its clock frequency in low-throughput
conditions. This patches enables it by default on
On 04/20/2018 02:26 PM, Rodrigo Vivi wrote:
On Fri, Apr 20, 2018 at 01:52:24PM -0700, Oscar Mateo wrote:
On 04/20/2018 01:48 PM, Rodrigo Vivi wrote:
On Fri, Apr 20, 2018 at 01:33:46PM -0700, Oscar Mateo wrote:
Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler
power by
On 04/20/2018 01:53 PM, Rodrigo Vivi wrote:
On Fri, Apr 20, 2018 at 01:49:45PM -0700, Oscar Mateo wrote:
On 04/20/2018 01:46 PM, Rodrigo Vivi wrote:
On Fri, Apr 20, 2018 at 01:33:54PM -0700, Oscar Mateo wrote:
Disable GWL clock gating to prevent two different issues that
might cause hangs
: Michel Thierry
Signed-off-by: Rodrigo Vivi
Signed-off-by: Michel Thierry
Signed-off-by: Oscar Mateo
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_irq.c | 6 ++--
drivers/gpu/drm/i915/intel_drv.h | 3 ++
drivers/gpu/drm/i915/intel_lrc.c
Only enough to achieve HuC authentication. No GuC submission
or any other feature for the time being.
Signed-off-by: Oscar Mateo
Cc: Joonas Lahtinen
Cc: Michal Wajdeczko
Cc: John Spotswood
Cc: Tony Ye
---
drivers/gpu/drm/i915/intel_guc.c | 10 --
drivers/gpu/drm/i915
Sanitize the enable_guc option so that we can enable HuC authentication,
but nothing else. The firmware interface has changed quite dramatically
in Gen11, so it will take a while before we can submit workloads to the
GuC with guarantees.
Signed-off-by: Oscar Mateo
Cc: Joonas Lahtinen
Cc: Michal
0)
v6: Use the latest firmware (v26.171)
v7: Rebased (remove guc-core-family)
v8: Use the latest firmware (v27.182)
Cc: Michal Wajdeczko
Cc: John Spotswood
Cc: Tony Ye
Cc: Joonas Lahtinen
Cc: Daniele Ceraolo Spurio
Signed-off-by: Michel Thierry
Signed-off-by: Oscar Mateo
---
drivers/gp
The register to check for correct HuC authentication by the GuC
has changed in Icelake. Look into the right register & bit.
v2: rebased.
v3: rebased.
v4: Fix I915_PARAM_HUC_STATUS as well (Tony)
BSpec: 19686
Signed-off-by: Oscar Mateo
Cc: Tony Ye
Cc: Vinay Belgaumkar
Cc: Michel Thierry
This patch adds the support to load HuC on ICL.
Version 8.02.2678
v2 (James): Rebase
Signed-off-by: Oscar Mateo
Cc: Tony Ye
Cc: Vinay Belgaumkar
Cc: Michel Thierry
Cc: Joonas Lahtinen
Cc: Michal Wajdeczko
Cc: John Spotswood
---
drivers/gpu/drm/i915/intel_huc_fw.c | 11 +++
1 file
Bare minimum number of patches to get the GuC to authenticate the
HuC correctly (i915.enable_guc=2).
Oscar Mateo (5):
drm/i915/icl/guc: Do not allow GuC submission on Icelake for now
drm/i915/icl/guc: Pass the bare minimum GuC init parameters for
Icelake
drm/i915/icl/guc: Define the GuC
On 04/26/2018 08:27 AM, Mika Kuoppala wrote:
Oscar Mateo writes:
The default GAPZ arbitrer priority value at power-on has been found
to be incorrect.
v2: Now renamed to Wa_1405543622
v3: Rebased on top of the WA refactoring
I have suggested that when implementing workarounds,
authors
On 04/26/2018 08:01 AM, Mika Kuoppala wrote:
Oscar Mateo writes:
Inherit workarounds from previous platforms that are still valid for
Icelake.
v2: GEN7_ROW_CHICKEN2 is masked
v3:
- Since it has been fixed already in upstream, removed the TODO
comment about WA_SET_BIT for
On 04/30/2018 04:29 PM, John Spotswood wrote:
On Fri, 2018-04-27 at 14:31 -0700, Oscar Mateo wrote:
Only enough to achieve HuC authentication. No GuC submission
or any other feature for the time being.
Signed-off-by: Oscar Mateo
Cc: Joonas Lahtinen
Cc: Michal Wajdeczko
Cc: John Spotswood
On 04/30/2018 04:34 PM, John Spotswood wrote:
On Fri, 2018-04-27 at 14:31 -0700, Oscar Mateo wrote:
A GuC firmware for Icelake is now available. Let's use it.
v2: Split out the Cannonlake stuff in a separate patch (Michal)
v3: Rebased
v4:
- Rebased
- Split out MODULE_FIRMWARE
This patch adds the support to load HuC on ICL.
Version 8.02.2678
v2 (James): Rebase
Signed-off-by: Oscar Mateo
Cc: Tony Ye
Cc: Vinay Belgaumkar
Cc: Michel Thierry
Cc: Joonas Lahtinen
Cc: Michal Wajdeczko
Cc: John Spotswood
Cc: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_huc_fw.c
Bare minimum number of patches to get the GuC to authenticate the
HuC correctly (i915.enable_guc=2).
Oscar Mateo (5):
drm/i915/icl/guc: Do not allow GuC submission on Icelake for now
drm/i915/icl/guc: Pass the bare minimum GuC init parameters for
Icelake
drm/i915/icl/guc: Define the GuC
Only enough to achieve HuC authentication. No GuC submission
or any other feature for the time being.
v2: Fix extra space
Signed-off-by: Oscar Mateo
Cc: Joonas Lahtinen
Cc: Michal Wajdeczko
Cc: John Spotswood
Cc: Tony Ye
Cc: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_guc.c | 10
The register to check for correct HuC authentication by the GuC
has changed in Icelake. Look into the right register & bit.
v2: rebased.
v3: rebased.
v4: Fix I915_PARAM_HUC_STATUS as well (Tony)
v5: Fix duplicate Cc
BSpec: 19686
Signed-off-by: Oscar Mateo
Cc: Tony Ye
Cc: Vinay Belgaumkar
Sanitize the enable_guc option so that we can enable HuC authentication,
but nothing else. The firmware interface has changed quite dramatically
in Gen11, so it will take a while before we can submit workloads to the
GuC with guarantees.
Signed-off-by: Oscar Mateo
Cc: Joonas Lahtinen
Cc: Michal
0)
v6: Use the latest firmware (v26.171)
v7: Rebased (remove guc-core-family)
v8: Use the latest firmware (v27.182)
v9: Use the latest firmware (v27.185)
Signed-off-by: Michel Thierry
Signed-off-by: Oscar Mateo
Cc: Michal Wajdeczko
Cc: John Spotswood
Cc: Tony Ye
Cc: Joonas Lahtinen
Cc: Danie
Adjust default GAM TLB partitioning for performance reasons.
v2: Only touch the bits that we really need
v3: Rebased on top of the WA refactoring
v4:
- Added References (Mika)
- Rebased
References: HSDES#220260670
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915
icelake_init_clock_gating()
from Paulo Zanoni
- Squashed with this patch:
drm/i915/icl: WaForceEnableNonCoherent
from Oscar Mateo
- WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and
applies to B0 as well.
- WaPipeControlBefore3DStateSamplePattern WABB was being
List of GT workarounds for Icelake that we have been carrying in internal.
Oscar Mateo (22):
drm/i915/icl: Introduce initial Icelake Workarounds
drm/i915/icl: Enable Sampler DFR
drm/i915/icl: WaGAPZPriorityScheme
drm/i915/icl: WaL3BankAddressHashing
drm/i915/icl
Revert to the legacy implementation to avoid a system hang.
v2: Correct the address for GAMW_ECO_DEV_RW_IA_REG
v3: Renamed to Wa_220166154
v4: Rebased on top of the WA refactoring
v5: Added References (Mika)
References: HSDES#220166154
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers
Added References (Mika)
References: HSDES#2006611047
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
drivers/gpu/drm/i915/intel_workarounds.c | 7 +++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg
Disable MSC clock gating to prevent data corruption.
BSpec: 19257
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
References: HSDES#1405779004
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915
)
- Do not apply together with another WA for the same
register (not worth the hassle)
References: HSDES#1604223664
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_workarounds.c | 10 ++
2 files changed
Disable blend embellishment in RCC.
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
References: HSDES#2006665173
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 18 +++---
drivers/gpu/drm/i915/intel_workarounds.c
Disable CGPSF unit clock gating to prevent an issue.
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
References: HSDES#1406838659
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 13 -
drivers/gpu/drm/i915
Cc: Rodrigo Vivi
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_workarounds.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
b/drivers/gpu/drm/i915/intel_workarounds.c
index 38e3776..ffb0e30 100644
--- a/drivers/gpu
icl_init_clock_gating, since it's not a WA (Rodrigo)
Cc: Rodrigo Vivi
Cc: Praveen Paneri
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
Reviewed-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 9 -
2 files changed, 11 insertions(
on top of the WA whitelist reg refactoring (Michel)
v5: Added References (Mika)
References: HSDES#1405764967
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_workarounds.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c
Disable I2M Write for performance reasons.
v2: Rebased on top of the WA refactoring
v3: Added References (Mika)
References: HSDES#1604302699
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
drivers/gpu/drm/i915/intel_workarounds.c | 5
Avoids an undefined LLC behavior.
BSpec: 9613
v2: Renamed to Wa_1405733216
v3: Spaces around '<<' and fix surrounding code
v4: Rebased on top of the WA refactoring
v5: Added References (Mika)
References: HSDES#1405733216
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
driv
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_workarounds.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a9866df..d36cf61 100644
--- a
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