From: Clint Taylor
Initialize c10 combo phy ports. TODO Type-C ports.
Cc: Radhakrishna Sripada
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b
Add DP rates for Meteorlake.
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_dp.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display
programming (Khaled)
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/Makefile |1 +
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 1120 +
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 43
Create a separate file to store registers for PICA chips
C10 and C20.
v2: Rename file (Jani)
v3: Use _PICK_EVEN_2RANGES() macro (Lucas)
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 139 ++
1 file changed
64603
Cc: Matt Atwood
Cc: Matt Roper
Cc: Lucas De Marchi
Cc: Gustavo Sousa
Signed-off-by: José Roberto de Souza
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_bw.c | 4 +-
drivers/gpu/drm/i915/display/intel_bw.h | 2 +
d
o times of level 1 preemphasis 0.
Fix this in the driver code as well.
v3: VSwing update (Clint)
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Clint Taylor
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 140 -
Sripada
Signed-off-by: Clint Taylor
Signed-off-by: Mika Kahola
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 576 +-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 1 +
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 2 +
drivers/gpu/drm/i915/
based on changes in BSpec consolidated table
v3: Rename intel_c20_read() to intel_c20_sram_read() (Gustavo)
Use context and correct MPLLA reg bit to select if MPLLA is in
use or not (Gustavo)
Signed-off-by: Mika Kahola
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display
pll programming (Gustavo)
Clear calibration banks for both lanes (Gustavo)
Signed-off-by: José Roberto de Souza
Signed-off-by: Mika Kahola
Signed-off-by: Bhanuprakash Modem
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 266 +++---
.../gpu/drm/i915
As we already do with C10 chip, let's dump the pll
hw state for C20 as well.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
3
Calculate port clock with C20 phy.
v2: Initialize parameters
v3: Revised formula for port clock check
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 70 ++-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
.../gpu/drm/i915/display
DP1.4 and DP20 voltage swing sequence for C20 phy.
Bspec: 65449, 67636, 67610
v2: DP2.0 Tx Eq tables has been updated in BSpec.
Update also the driver code as per BSpec 65449
Signed-off-by: Mika Kahola
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Clint Taylor
---
.../gpu/drm/i915
provides a dedicated HPD
control register for each supported port, so we loop over ports
ourselves instead of using intel_hpd_hotplug_enables() or
intel_get_hpd_pins().
BSpec: 49305, 55726, 65107, 65300
Signed-off-by: Mika Kahola
Signed-off-by: Madhumitha Tolakanahalli Pradeep
Signed-off-by
From: Gustavo Sousa
Xe_LPD+ defines interrupt bits for only DDI ports in the DE Port
Interrupt registers. The bits for Type-C ports are defined in the PICA
interrupt registers.
BSpec: 50064
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/i915_irq.c | 5 -
1 file changed, 4 insertions
Add C20 HDMI state calculations and put HDMI table definitions
in use.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display
Readout hw state for Thunderbolt.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++-
3 files changed, 32 insertions(+), 2 deletions
Enabling and disabling sequence for Thunderbolt PLL.
v2: Use __intel_de_wait_for_register() instead of
__intel_wait_for_register() (Jani)
Use '0' instead of ~XELPDP_TBT_CLOCK_ACK (Gustavo)
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_p
Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display
Finally, we can enable TC ports for Meteorlake.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_display.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index
From: Imre Deak
The HPD live status for MTL has to be read from different set of
registers. MTL deserves a new function for this purpose
and cannot reuse the existing HPD live status detection
Signed-off-by: Anusha Srivatsa
Signed-off-by: Imre Deak
Signed-off-by: Mika Kahola
---
drivers
From: Anusha Srivatsa
Unlike previous platforms that used PORT_TX_DFLEXDPSP
for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1
from which the max_lanes has to be calculated.
Bspec: 50235, 65380
Cc: Mika Kahola
Cc: Imre Deak
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Signed-off-by
tcss power request with correct parameter.
v3: Use de variant for register wait (Jani)
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_tc.c | 117 ++-
2 files changed, 114 insertions(+), 5 deletions
Phy programming support for C10 PICA chips. This is the first part of
the series that adds support for PICA chips. Later the support for
C20 chips are added.
Signed-off-by: Mika Kahola
Clint Taylor (1):
drm/i915/mtl: Initial DDI port setup
Mika Kahola (3):
drm/i915/mtl: Add DP rates
drm
From: Clint Taylor
Initialization sequences and C10 phy are in place to be able to enable
the first 2 ports of MTL. The other ports use C20 phy that still need
to be properly added. Enable the first ports for now, keeping a TODO
comment about the others.
Cc: Radhakrishna Sripada
Reviewed-by: Lu
Add DP rates for Meteorlake.
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_dp.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display
programming (Khaled)
Cc: Mika Kahola
Cc: Imre Deak
Cc: Uma Shankar
Cc: Gustavo Sousa
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/Makefile |1 +
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 1120 +
drivers/gpu/drm/i915
Create a separate file to store registers for PICA chips
C10 and C20.
v2: Rename file (Jani)
v3: Use _PICK_EVEN_2RANGES() macro (Lucas)
Coding style fixed (Lucas)
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 131
lace
this patch with something more general purpose.
Bspec: 64568
v2: Rebasing with Clint's HDMI C10 PLL tables (Mika)
v3: Add missing use_hdmi checks from Clint's HDMI implementation changes (Ankit)
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Cli
Display14 introduces a new way to instruct the PUnit with
power and bandwidth requirements of DE. Add the functionality
to program the registers and handle waits using interrupts.
The current wait time for timeouts is programmed for 10 msecs to
factor in the worst case scenarios. Changes made to us
o times of level 1 preemphasis 0.
Fix this in the driver code as well.
v3: VSwing update (Clint)
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Clint Taylor
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 140 -
er
Cc: Lucas De Marchi
Cc: Gustavo Sousa
Signed-off-by: José Roberto de Souza
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_bw.c | 4 +-
drivers/gpu/drm/i915/display/intel_bw.h | 2 +
drivers/gpu/drm/i915/display/intel_dis
PHY programming support for PICA C10 and C20 Type-C chips.
v2: Move intel_cx0_reg_defs.h to intel_cx0_phy_regs.h (Jani)
Move pmdemand as part of intel_display structure
PLL table updates
Signed-off-by: Mika Kahola
Anusha Srivatsa (1):
drm/i915/mtl: Pin assignment for TypeC
Clint
From: Clint Taylor
Initialize c10 combo phy ports. TODO Type-C ports.
Cc: Radhakrishna Sripada
Signed-off-by: Clint Taylor
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-2-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
1 file ch
Add DP rates for Meteorlake.
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-3-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_dp.c | 15 ++-
1 file changed, 14 insertions(+), 1
Create a separate file to store registers for PICA chips
C10 and C20.
v2: Rename file (Jani)
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 136 ++
1 file changed, 136 insertions(+)
create mode 100644 drivers
() with port instead of phy (Lucas)
v3: Move clear request flag into try-loop
Cc: Mika Kahola
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-5-mika.kah...@intel.com
lace
this patch with something more general purpose.
Bspec: 64568
v2: Rebasing with Clint's HDMI C10 PLL tables (Mika)
v3: Add missing use_hdmi checks from Clint's HDMI implementation changes (Ankit)
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Cli
o times of level 1 preemphasis 0.
Fix this in the driver code as well.
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Clint Taylor
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-7-mika.kah...
Signed-off-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-8-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_bw.c | 4 +-
drivers/gpu/drm/i915/display/intel_bw.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 14 +
.
C20 phy PLL programming sequence for DP, DP2.0, HDMI2.x non-FRL and
HDMI2.x FRL. This enables C20 MPLLA and MPLLB programming sequence. add
4 lane support for c20.
Signed-off-by: José Roberto de Souza
Signed-off-by: Mika Kahola
Signed-off-by: Bhanuprakash Modem
Signed-off-by: Imre Deak
Link
Calculate port clock with C20 phy.
Signed-off-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-11-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 32 ++--
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2
based on changes in BSpec consolidated table
Signed-off-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-10-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 495 ++-
drivers/gpu/drm/i915/display/intel_cx0_phy.h
Add C20 HDMI state calculations and put HDMI table definitions
in use.
Signed-off-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-12-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 ++
1 file changed, 10 insertions
Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled.
Signed-off-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-14-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions
Enabling and disabling sequence for Thunderbolt PLL.
Signed-off-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-15-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 137 ++-
drivers/gpu/drm/i915/display
DP1.4 and DP20 voltage swing sequence for C20 phy.
Bspec: 65449, 67636, 67610
v2: DP2.0 Tx Eq tables has been updated in BSpec.
Update also the driver code as per BSpec 65449
Signed-off-by: Mika Kahola
Signed-off-by: Radhakrishna Sripada
Link:
https://patchwork.freedesktop.org/patch
Readout hw state for Thunderbolt.
Signed-off-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-16-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2
Finally, we can enable TC ports for Meteorlake.
Signed-off-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-17-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_display.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a
provides a dedicated HPD
control register for each supported port, so we loop over ports
ourselves instead of using intel_hpd_hotplug_enables() or
intel_get_hpd_pins().
BSpec: 49305, 55726, 65107, 65300
Signed-off-by: Mika Kahola
Signed-off-by: Madhumitha Tolakanahalli Pradeep
Signed-off-by
From: Gustavo Sousa
Xe_LPD+ defines interrupt bits for only DDI ports in the DE Port
Interrupt registers. The bits for Type-C ports are defined in the PICA
interrupt registers.
BSpec: 50064
Signed-off-by: Gustavo Sousa
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-1
tcss power request with correct parameter.
Signed-off-by: Mika Kahola
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-20-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_tc.c | 117
From: Anusha Srivatsa
Unlike previous platforms that used PORT_TX_DFLEXDPSP
for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1
from which the max_lanes has to be calculated.
Bspec: 50235, 65380
Cc: Mika Kahola
Cc: Imre Deak
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Signed-off-by
From: Imre Deak
The HPD live status for MTL has to be read from different set of
registers. MTL deserves a new function for this purpose
and cannot reuse the existing HPD live status detection
Signed-off-by: Anusha Srivatsa
Signed-off-by: Imre Deak
Signed-off-by: Mika Kahola
---
drivers
From: Imre Deak
For MTL+ platforms we use PICA chips for Type-C support and
hence mg programming is not needed.
Fixes issue with drm warn of TC port not being in legacy mode.
Signed-off-by: Mika Kahola
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +++
1 file
alues
by the driver.
Signed-off-by: Mika Kahola
Mika Kahola (2):
Revert "drm/i915/display: Skip C10 state verification in case of
fastset"
drm/i915/display: Force full modeset for eDP
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 3 ---
drivers/gpu/drm/i915/display/intel
This reverts commit a1d91c6e989d0e66b89aa911f2cd459d7bdebbe5.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index
true and hence we would need to program PLL values by the
driver. The patch suggests a workaround as enabling full
modeset when booting up. This way we force the driver to
write the PLL values to the hw.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_dp.c | 13 +
1
.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 8e3b13884bb8..89a195917179 100644
--- a/drivers/gpu/drm
As a preparation to remove .clock member from pll state
structure, let's move the port clock calculation on better
location
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 176 ++-
1 file changed, 91 insertions(+), 85 deletions(-)
diff --
.clock is not necessarily required to have in pll state
structure as it can always recalculated with the *_calc_port_clock()
function. Hence, let's remove this struct member complitely.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c
,
we would need to disable fastset and use full modeset instead.
However, first we need to revert the patch that disables fastset
for C10.
Signed-off-by: Mika Kahola
Mika Kahola (2):
drm/i915/display: Revert "drm/i915/display: Skip C10 state
verification in case of fastset"
,
we would need to disable fastset and use full modeset instead.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 74 +++
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 39 ++
drivers/gpu
This reverts commit a1d91c6e989d0e66b89aa911f2cd459d7bdebbe5.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index
intel_cx0pll_dump_hw_state() to dump
pll information (Jani)
Signed-off-by: Mika Kahola
Mika Kahola (2):
drm/i915/display: Revert "drm/i915/display: Skip C10 state
verification in case of fastset"
drm/i915/display: Add compare config for MTL+ platforms
drivers/gpu/drm/i915/display/intel_cx0_p
This reverts commit a1d91c6e989d0e66b89aa911f2cd459d7bdebbe5.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index
,
we would need to disable fastset and use full modeset instead.
v2: Fix C10 error on PLL comparison (BAT)
Use memcmp instead of fixed loops for pll config
comparison (Jani)
Clean up and use intel_cx0pll_dump_hw_state() to dump
pll information (Jani)
Signed-off-by: Mika Kahola
training parameters are set
to zero and training is restarted.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_dp.c | 75 +++-
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 67 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915
Generalization to cover DP case
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9497eb6..abf8c7d 100644
--- a/drivers/gpu/drm/i915
This patch adds fast link training support if BDB version
is equal or higher than 182 and the feature is supported
in VBT.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_bios.c | 4
drivers/gpu/drm/i915/intel_bios.h | 1 +
drivers/gpu
et_global_pipes()'
--
Mika Kahola, Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Fill out the lower three digits for gen2 and gen3 cdclk frqeuncy. It's
not clear if these are accurate frquencies or just in the ballpark, but
without docs this is the best we can do.
Signed-off-by: Ville Syrjälä
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_display.c
Ville Syrjälä
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/i915_reg.h | 11 ---
drivers/gpu/drm/i915/intel_display.c | 15 ---
2 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b5
is machine.
Signed-off-by: Ville Syrjälä
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/i915_reg.h | 3 +
drivers/gpu/drm/i915/intel_display.c | 186 ++-
2 files changed, 185 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/d
so I couldn't verify what the BIOS used, so this notion is
purely based on our current code,
Signed-off-by: Ville Syrjälä
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_display.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/d
We don't currently have cdclk extraction code for 965g,snb,ivb.
Let's assume 400 MHz until we know better. That seems to match hints
in various vague documents. Whether that's good enough is not
entirely clear.
Signed-off-by: Ville Syrjälä
Signed-off-by: Mika Kahola
---
drive
Unify the HSW/BDW/SKL cdclk extraction code to conform to the same
.get_display_clock_speed() mold that all the other platforms
use.
v2: Update due to SKL code getting added
Signed-off-by: Ville Syrjälä
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_audio.c | 3 +-
drivers/gpu
Now that we are "extracting" the cdclk frequency on ILK-IVB we
can also simplify ilk_get_aux_clock_divider() to calculate the
divider based on cdclk instead of hardcoding the values.
Signed-off-by: Ville Syrjälä
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_dp.c | 6 ++--
Rather than reading out the current cdclk value use the cached value we
have tucked away in dev_priv.
Signed-off-by: Ville Syrjälä
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_display.c | 3 +--
drivers/gpu/drm/i915/intel_dp.c | 5 +++--
drivers/gpu/drm/i915/intel_pm.c
ilk_get_aux_clock_divider() is now a subset of
hsw_get_aux_clock_divider() so unify them.
Signed-off-by: Ville Syrjälä
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_dp.c | 23 +++
1 file changed, 3 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm
Rather that extracting the current cdclk freuqncy every time someone
wants to know it, cache the current value and use that. VLV/CHV already
stored a cached value there so just expand that to cover all platforms.
Signed-off-by: Ville Syrjälä
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_display.c | 20 +++-
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 38279f6..39b6042
st the max cdclk insted of the current cdclk
Tested-by: Timo Aaltonen
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83497
Signed-off-by: Ville Syrjälä
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_display.c | 31 +--
drivers/gpu/drm/i915/intel_drv.
Limit CHV maximum cdclk to 320MHz.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 736df3e..5ed40df 100644
--- a/drivers/gpu
.global_resources() reordering for Haswell
Signed-off-by: Ville Syrjälä
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/i915_reg.h | 3 +
drivers/gpu/drm/i915/intel_display.c | 161 ++-
2 files changed, 161 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm
pixel rate.
v2: Grab rps.hw_lock around sandybridge_pcode_write()
v3: Rebase due to power well vs. .global_resources() reordering
v4: Rebase due to .global_resources() reordering for BDW
Signed-off-by: Ville Syrjälä
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
driver
Combined Valleyview, Haswell and Broadwell '*_modeset_global_pipes()'
into one function 'intel_modeset_global_pipes()'
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_display.c | 89 +---
1 file changed, 41 insertions(+), 48 deleti
We need to tell BDW ULT and ULX apart.
Signed-off-by: Ville Syrjälä
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 39b6042..c7f7808 100644
--- a
On Tue, Mar 31, 2015 at 05:45:56PM +0300, Ville Syrjälä wrote:
> On Tue, Mar 31, 2015 at 02:14:23PM +0300, Mika Kahola wrote:
> > Combined Valleyview, Haswell and Broadwell '*_modeset_global_pipes()'
> > into one function 'intel_modeset_global_pipes()'
ction 'intel_calc_cdclk()' that combines
routines from 'valleyview_calc_cdclk()' and 'haswell_calc_cdclk()'
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_display.c | 191 ---
1 file changed, 88 insertions(+), 103 deletions(-)
Definitely a good idea to check the audio part as well if there is
a doubt that by changing CD clock the audio would fail. I can check
this and I'll get back once I have the results.
Cheers,
Mika
On Tue, Apr 07, 2015 at 02:06:50PM +0530, Sivakumar Thulasimani wrote:
> where can i check this (au
ction 'intel_calc_cdclk()' that combines
routines from 'valleyview_calc_cdclk()' and 'haswell_calc_cdclk()'
v3:
- Let's take a step back and not remove the routines 'valleyview_calc_cdclk()'
and 'haswell_calc_cdclk()' from newly introduced routine
at 15:52 +0200, Daniel Vetter wrote:
> On Tue, Apr 07, 2015 at 12:29:25PM +0300, Mika Kahola wrote:
> > Definitely a good idea to check the audio part as well if there is
> > a doubt that by changing CD clock the audio would fail. I can check
> > this and I'll get back o
On Thu, 2015-04-09 at 11:32 +0200, Daniel Vetter wrote:
> On Thu, Apr 09, 2015 at 10:24:24AM +0300, Mika Kahola wrote:
> > I did some testing on audio part with HDMI-HDMI and DP-HDMI cables
> > connected to my Haswell box. Before applying the patch I tested as a
> > refe
On Fri, 2015-04-10 at 16:10 +0200, Takashi Iwai wrote:
> At Fri, 10 Apr 2015 16:27:39 +0300,
> Mika Kahola wrote:
> >
> > On Thu, 2015-04-09 at 17:17 +0200, Takashi Iwai wrote:
> > > At Thu, 9 Apr 2015 15:51:27 +0200,
> > > Daniel Vetter wrote:
> > >
I tested this patch with the audio in place. With this setup in my HSW
machine I can hear the pink noise played back with DP-HDMI cable
attatched.
speaker-test -c 2 -r 48000 -F S16_LE -t pink --device=plughw:0,7
Cheers,
Mika
On Tue, 2015-04-07 at 14:06 +0530, Sivakumar Thulasimani wrote:
> where
for the update Mika. The issue will be that audio plays faster or
> slower than normal. i.e it will be < 1x or > 1x. can you confirm if
> audible sound plays after CD Clock change at 1x speed ?
>
> regards,
> Sivakumar
> On 4/14/2015 12:06 PM, Mika Kahola wrote:
> >
This series is revised based on Jani's good comments.
In this series the patch which read out DP link training
parameters from VBT is discarded as based on the comments
that I received.
Files changed:
drivers/gpu/drm/i915/intel_dp.c
drivers/gpu/drm/i915/intel_drv.h
__
training parameters are set
to zero and training is restarted.
V2:
- flag that indicates if DP link is trained and valid
renamed from 'link_trained' to 'train_set_valid'
- removed routine 'intel_dp_reuse_link_train'
Signed-off-by: Mika Kahola
---
drivers
This patch adds DP link training optimization by reusing the
previously trained values.
v2:
- rebase
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915
Limit CHV maximum cdclk to 320MHz.
v2: Rebase to the latest
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index c38c297
701 - 800 of 995 matches
Mail list logo
