On Thu, 2017-01-12 at 11:00 +0100, Maarten Lankhorst wrote:
> Op 30-12-16 om 13:47 schreef Mika Kahola:
> >
> > Testcase for plane visibility after atomic modesets. The idea of
> > the test
> > is the following:
> >
> > - draw a blue screen with high
In CI system, the default 64 iterations of this test may cause CRC overflow
warnings in dmesg when debugfs is enabled in kernel config. To keep dmesg
warning noise in minimum, let's run this test only once by default.
Signed-off-by: Mika Kahola
---
tests/kms_plane_multiple.c | 2 +-
1
This is definitely needed to pass igt test on bxt
'gem_exec_suspend --run-subtest basic-S3'
Tested-by: Mika Kahola
On Mon, 2017-01-09 at 14:46 +0530, Vidya Srinivas wrote:
> From: Uma Shankar
>
> Enable MIPI IO WA for BXT DSI as per bspec.
>
> Signed-off-by: Uma
Fixes for issues seen on CI tests. The patches provide relaxed timing
requirement for atomic commit as well as general cleanup to favor library
functions.
Mika Kahola (2):
tests/kms_plane_multiple: Relax atomic commit time requirement
tests/kms_plane_multiple: Cleanup in favor of library
Relax required time to atomic commits from 1 vblank to 2 vblanks.
Reference: Issues seen on BYT CI tests
Cc: Maarten Lankhorst
Signed-off-by: Mika Kahola
---
tests/kms_plane_multiple.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/tests/kms_plane_multiple.c b
Cleaunup by replacing get_vblank() function with library function
kmstest_get_vblank().
Cc: Maarten Lankhorst
Signed-off-by: Mika Kahola
---
tests/kms_plane_multiple.c | 27 +++
1 file changed, 3 insertions(+), 24 deletions(-)
diff --git a/tests/kms_plane_multiple.c b
On Mon, 2017-01-16 at 14:26 +0100, Maarten Lankhorst wrote:
> Op 16-01-17 om 14:09 schreef Mika Kahola:
> >
> > Relax required time to atomic commits from 1 vblank to 2 vblanks.
> >
> > Reference: Issues seen on BYT CI tests
> >
> > Cc: Maarten Lankhor
Relax required time to atomic commits from 1 vblank to 2 vblanks.
v2: Increase MAX_CRCS to 2 (Maarten)
Reference: Issues seen on BYT CI tests
Cc: Maarten Lankhorst
Signed-off-by: Mika Kahola
---
tests/kms_plane_multiple.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions
Cleaunup by replacing get_vblank() function with library function
kmstest_get_vblank().
Cc: Maarten Lankhorst
Reviewed-by: Maarten Lankhorst
Signed-off-by: Mika Kahola
---
tests/kms_plane_multiple.c | 27 +++
1 file changed, 3 insertions(+), 24 deletions(-)
diff
Fixes for issues seen on CI tests. The patches provide relaxed timing
requirement for atomic commit as well as general cleanup to favor library
functions.
v2: fix MAX_CRCS definition
Mika Kahola (2):
tests/kms_plane_multiple: Relax atomic commit time requirement
tests/kms_plane_multiple
intel_dsi_clear_device_ready(encoder);
>
> + val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
> + I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
> + val & ~MIPIO_RST_CTRL);
> +
> intel_disable_dsi_pll(encoder);
>
> + /* Power down DSI regulator to save power */
> + I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
> + I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, HS_IO_CTRL_SELECT);
> +
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> u32 val;
>
--
Mika Kahola - Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Reviewed-by: Mika Kahola
On Fri, 2017-01-20 at 12:45 -0500, Robert Foss wrote:
> Add an index property which helps accessing the corresponding
> igt_plane_t structure through the igt_*_get_plane() functions.
>
> Signed-off-by: Robert Foss
> ---
> lib/igt_kms
Reviewed-by: Mika Kahola
On Fri, 2017-01-20 at 12:45 -0500, Robert Foss wrote:
> Rework kmstest_crtc and kmstest_plane structs and their usage
> to not depend on a static plane count.
>
> Signed-off-by: Robert Foss
> ---
>
Reviewed-by: Mika Kahola
On Fri, 2017-01-20 at 12:45 -0500, Robert Foss wrote:
> Rename these properties to have them use the same naming convention
> as the igt_*_t structs.
>
> Signed-off-by: Robert Foss
> ---
> lib/igt_kms.c| 16 +---
> lib/igt_
t; i915_drm.h */
> -enum igt_plane {
> - IGT_PLANE_1 = 0,
> - IGT_PLANE_PRIMARY = IGT_PLANE_1,
> - IGT_PLANE_2,
> - IGT_PLANE_3,
> - IGT_PLANE_4,
> - IGT_PLANE_5,
> - IGT_PLANE_6,
> - IGT_PLANE_7,
> - IGT_PLANE_8,
> - IGT_PLANE_9,
On Thu, 2017-01-12 at 12:37 +0100, Maarten Lankhorst wrote:
> Hey,
>
> Op 12-01-17 om 11:28 schreef Mika Kahola:
> >
> > On Thu, 2017-01-12 at 11:11 +0100, Maarten Lankhorst wrote:
> > >
> > > Op 30-12-16 om 13:00 schreef Mika Kahola:
> > > >
Reviewed-by: Mika Kahola
On Tue, 2017-01-24 at 18:33 -0500, Robert Foss wrote:
> Add an index property which helps accessing the corresponding
> igt_plane_t structure through the igt_*_get_plane() functions.
>
> Signed-off-by: Robert Foss
> ---
> lib/igt_kms
Reviewed-by: Mika Kahola
On Tue, 2017-01-24 at 18:33 -0500, Robert Foss wrote:
> Rework kmstest_crtc and kmstest_plane structs and their usage
> to not depend on a static plane count.
>
> Signed-off-by: Robert Foss
> ---
>
Reviewed-by: Mika Kahola
On Tue, 2017-01-24 at 18:33 -0500, Robert Foss wrote:
> Rename these properties to have them use the same naming convention
> as the igt_*_t structs.
>
> Signed-off-by: Robert Foss
> ---
> lib/igt_kms.c| 16 +---
> lib/igt_
for (j = 0; j < plane_resources->count_planes; j++)
> {
> + drmModePlane *drm_plane;
> +
> + drm_plane = drmModeGetPlane(display->drm_fd,
> + plane_resources-
> >planes[j]);
> +
Reviewed-by: Mika Kahola
On Tue, 2017-01-24 at 18:33 -0500, Robert Foss wrote:
> Add changes reflecting the new support for dynamic number of planes
> per pipe.
>
> Signed-off-by: Robert Foss
> ---
> tests/kms_atomic_transition.c | 27 +--
>
Reviewed-by: Mika Kahola
On Tue, 2017-01-24 at 18:33 -0500, Robert Foss wrote:
> Add changes reflecting the new support for dynamic number of planes
> per pipe.
>
> Signed-off-by: Robert Foss
> ---
> tests/kms_busy.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion
Reviewed-by: Mika Kahola
On Tue, 2017-01-24 at 18:33 -0500, Robert Foss wrote:
> Add changes reflecting the new support for dynamic number of planes
> per pipe.
>
> Signed-off-by: Robert Foss
> ---
> tests/kms_crtc_background_color.c | 2 +-
> 1 file changed, 1 ins
Reviewed-by: Mika Kahola
On Tue, 2017-01-24 at 18:33 -0500, Robert Foss wrote:
> Add changes reflecting the new support for dynamic number of planes
> per pipe.
>
> Signed-off-by: Robert Foss
> ---
> tests/kms_cursor_crc.c | 12 ++--
> 1 file changed, 6 inser
Reviewed-by: Mika Kahola
On Tue, 2017-01-24 at 18:33 -0500, Robert Foss wrote:
> Add changes reflecting the new support for dynamic number of planes
> per pipe.
>
> Signed-off-by: Robert Foss
> ---
> tests/kms_chv_cursor_fail.c | 6 +++---
> 1 file changed, 3 inser
d. For consistency, should we
rename this as pipe_id too? I'll leave this up to you. Either way, this
is
Reviewed-by: Mika Kahola
>
> - for_each_pipe(display, pipe) {
> - igt_plane_t *plane = &display-
> >pipes[pipe].planes[IGT_PLANE_PRIM
Reviewed-by: Mika Kahola
On Tue, 2017-01-24 at 18:33 -0500, Robert Foss wrote:
> Add changes reflecting the new support for dynamic number of planes
> per pipe.
>
> Signed-off-by: Robert Foss
> ---
> tests/kms_flip_event_leak.c | 2 +-
> 1 file changed, 1 insertion(+), 1
Reviewed-by: Mika Kahola
On Tue, 2017-01-24 at 18:33 -0500, Robert Foss wrote:
> Add changes reflecting the new support for dynamic number of planes
> per pipe.
>
> Signed-off-by: Robert Foss
> ---
> tests/kms_fence_pin_leak.c | 2 +-
> 1 file changed, 1 insertion(+), 1
Reviewed-by: Mika Kahola
On Tue, 2017-01-24 at 18:33 -0500, Robert Foss wrote:
> Add changes reflecting the new support for dynamic number of planes
> per pipe.
>
> Signed-off-by: Robert Foss
> ---
> tests/kms_legacy_colorkey.c | 4 +++-
> 1 file changed, 3 inse
Reviewed-by: Mika Kahola
On Tue, 2017-01-24 at 18:33 -0500, Robert Foss wrote:
> Add changes reflecting the new support for dynamic number of planes
> per pipe.
>
> Signed-off-by: Robert Foss
> ---
> tests/kms_mmap_write_crc.c | 2 +-
> 1 file changed, 1 insertion(+), 1
Reviewed-by: Mika Kahola
On Tue, 2017-01-24 at 18:33 -0500, Robert Foss wrote:
> Add changes reflecting the new support for dynamic number of planes
> per pipe.
>
> Signed-off-by: Robert Foss
> ---
> tests/kms_mmio_vs_cs_flip.c | 6 +++---
> 1 file changed, 3 inser
Reviewed-by: Mika Kahola
On Tue, 2017-01-24 at 18:33 -0500, Robert Foss wrote:
> Add changes reflecting the new support for dynamic number of planes
> per pipe.
>
> Signed-off-by: Robert Foss
> ---
> tests/kms_panel_fitting.c | 16
> 1 file change
Reviewed-by: Mika Kahola
On Tue, 2017-01-24 at 18:33 -0500, Robert Foss wrote:
> Add changes reflecting the new support for dynamic number of planes
> per pipe.
>
> Signed-off-by: Robert Foss
> ---
> tests/kms_pipe_color.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 d
}
>
> static void
> -test_plane_panning(data_t *data, enum pipe pipe, enum igt_plane
> plane,
> +test_plane_panning(data_t *data, enum pipe pipe, int plane,
> unsigned int flags)
misaligned parameter. With that fixed, this is
Reviewed-by: Mika Kahola
>
_I915_FORMAT_MOD_Y_TILED);
> + }
> +
> + igt_subtest_f("atomic-pipe-%s-tiling-y-planes",
> + kmstest_pipe_name(pipe)) {
> + int n_planes = data->display.pipes[pipe].n_planes;
> + for (int planes = 0; planes < n_planes; planes++
Reviewed-by: Mika Kahola
On Tue, 2017-01-24 at 18:33 -0500, Robert Foss wrote:
> Add changes reflecting the new support for dynamic number of planes
> per pipe.
>
> Signed-off-by: Robert Foss
> ---
> tests/kms_plane_scaling.c | 14 +++---
> 1 file changed, 7 inser
Reviewed-by: Mika Kahola
On Tue, 2017-01-24 at 18:33 -0500, Robert Foss wrote:
> Add changes reflecting the new support for dynamic number of planes
> per pipe.
>
> Signed-off-by: Robert Foss
> ---
> tests/kms_properties.c | 6 +++---
> 1 file changed, 3 inser
Reviewed-by: Mika Kahola
On Tue, 2017-01-24 at 18:33 -0500, Robert Foss wrote:
> Add changes reflecting the new support for dynamic number of planes
> per pipe.
>
> Signed-off-by: Robert Foss
> ---
> tests/kms_psr_sink_crc.c | 52 +-
>
Reviewed-by: Mika Kahola
On Tue, 2017-01-24 at 18:33 -0500, Robert Foss wrote:
> Add changes reflecting the new support for dynamic number of planes
> per pipe.
>
> Signed-off-by: Robert Foss
> ---
> tests/kms_rmfb.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion
Reviewed-by: Mika Kahola
On Tue, 2017-01-24 at 18:33 -0500, Robert Foss wrote:
> Add changes reflecting the new support for dynamic number of planes
> per pipe.
>
> Signed-off-by: Robert Foss
> ---
> tests/kms_pwrite_crc.c | 2 +-
> 1 file changed, 1 insertion(+), 1
Reviewed-by: Mika Kahola
On Tue, 2017-01-24 at 18:33 -0500, Robert Foss wrote:
> Add changes reflecting the new support for dynamic number of planes
> per pipe.
>
> Signed-off-by: Robert Foss
> ---
> tests/kms_rotation_crc.c | 63
> -
Reviewed-by: Mika Kahola
On Tue, 2017-01-24 at 18:33 -0500, Robert Foss wrote:
> Add changes reflecting the new support for dynamic number of planes
> per pipe.
>
> Signed-off-by: Robert Foss
> ---
> tests/kms_sink_crc_basic.c | 2 +-
> 1 file changed, 1 insertion(+), 1
Reviewed-by: Mika Kahola
On Tue, 2017-01-24 at 18:33 -0500, Robert Foss wrote:
> Add changes reflecting the new support for dynamic number of planes
> per pipe.
>
> Signed-off-by: Robert Foss
> ---
> tests/kms_universal_plane.c | 18 +-
> 1 file change
From: Clint Taylor
Initialization sequences and C10 phy are in place to be able to enable
the first 2 ports of MTL. The other ports use C20 phy that still need
to be properly added. Enable the first ports for now, keeping a TODO
comment about the others.
Cc: Radhakrishna Sripada
Reviewed-by: Lu
)
General cleanups and macro definitions (Imre)
Signed-off-by: Mika Kahola
Ankit Nautiyal (1):
drm/i915/display/mtl: Fill port width in
DDI_BUF_/TRANS_DDI_FUNC_/PORT_BUF_CTL for HDMI
Clint Taylor (1):
drm/i915/mtl: Initial DDI port setup
José Roberto de Souza (1):
drm/i915/mtl
0.
Fix this in the driver code as well.
v3: VSwing update (Clint)
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Clint Taylor
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 61 +--
drivers/gpu/drm/i9
programming (Khaled)
v4: Add tx and cmn on c10mpllb_state (Imre)
Add missing waits for pending transactions between two message bus
writes (Imre)
General cleanups and simplifications (Imre)
Cc: Mika Kahola
Cc: Imre Deak
Cc: Uma Shankar
Cc: Gustavo Sousa
Signed-off-by: Radhakrishna Sripada
Add DP rates for Meteorlake.
Reviewed-by: Vinod Govindapillai
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_dp.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
Create a separate file to store registers for PICA chips
C10 and C20.
v2: Rename file (Jani)
v3: Use _PICK_EVEN_2RANGES() macro (Lucas)
Coding style fixed (Lucas)
v4: Redefine macros (Imre)
Reviewed-by: Vinod Govindapillai (v3)
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
: Imre Deak
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/i915_irq.c | 249 +++-
drivers/gpu/drm/i915/i915_reg.h | 31 +++-
2 files changed, 273 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index
ommit message.
v3:
- Use TRANS_DDI_PORT_WIDTH() instead of DDI_PORT_WIDTH() for the value
of TRANS_DDI_FUNC_CTL_*. (Gustavo)
Signed-off-by: Ankit Nautiyal
Signed-off-by: Taylor, Clinton A
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_ddi.c | 48 +---
dr
5505
Acked-by: Matt Roper
Signed-off-by: Satyeshwar Singh
Signed-off-by: Clint Taylor
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Ankit Nautiyal
Signed-off-by: José Roberto de Souza
Signed-off-by: Mika Kahola
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 8 +
drivers/gpu/drm
Add support for C20 phy for Type-C connections. C20 phy differs from
C10 and hence we need to separately handle this case.
Signed-off-by: Mika Kahola
Anusha Srivatsa (1):
drm/i915/mtl: Pin assignment for TypeC
Gustavo Sousa (1):
drm/i915/mtl: Define mask for DDI AUX interrupts
Imre Deak
C20 phy PLL programming sequence for DP, DP2.0, HDMI2.x non-FRL and
HDMI2.x FRL. This enables C20 MPLLA and MPLLB programming sequence. add
4 lane support for c20.
Signed-off-by: José Roberto de Souza
Signed-off-by: Mika Kahola
Signed-off-by: Bhanuprakash Modem
Signed-off-by: Imre Deak
Signed
Create a table for C20 DP1.4, DP2.0 and HDMI2.1 rates.
The PLL settings are based on table, not for algorithmic alternative.
For DP 1.4 only MPLLB is in use.
Once register settings are done, we read back C20 HW state.
BSpec: 64568
Signed-off-by: Mika Kahola
Signed-off-by: Arun R Murthy
Signed
Calculate port clock with C20 phy.
BSpec: 64568
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 45 +++
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++
drivers/gpu/drm/i915/display
From: Imre Deak
The HPD live status for MTL has to be read from different set of
registers. MTL deserves a new function for this purpose
and cannot reuse the existing HPD live status detection
Signed-off-by: Anusha Srivatsa
Signed-off-by: Imre Deak
Signed-off-by: Mika Kahola
---
drivers
As we already do with C10 chip, let's dump the pll
hw state for C20 as well.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
3
Readout hw state for Thunderbolt.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++-
3 files changed, 32 insertions(+), 2 deletions
From: Gustavo Sousa
Xe_LPD+ defines interrupt bits for only DDI ports in the DE Port
Interrupt registers. The bits for Type-C ports are defined in the PICA
interrupt registers.
BSpec: 50064
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/i915_irq.c | 5 -
1 file changed, 4 insertions
Enabling and disabling sequence for Thunderbolt PLL.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 135 ++-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 7 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
3 files changed, 138
Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display
DP1.4 and DP20 voltage swing sequence for C20 phy.
Bspec: 65449, 67636, 67610
Signed-off-by: Mika Kahola
Signed-off-by: Clint Taylor
Signed-off-by: Radhakrishna Sripada
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++
.../drm/i915/display/intel_ddi_buf_trans.c| 53
-by: Mika Kahola
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 19 ++
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 4 +
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display
From: Anusha Srivatsa
Unlike previous platforms that used PORT_TX_DFLEXDPSP
for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1
from which the max_lanes has to be calculated.
Bspec: 50235, 65380
Signed-off-by: Anusha Srivatsa
Signed-off-by: Jose Roberto de Souza
Signed-off-by: Mika
Finally, we can enable TC ports for Meteorlake.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_display.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index
Add support for C20 phy for Type-C connections. C20 phy differs from
C10 and hence we need to separately handle this case.
v2: Fixes for C20 pll programming and hw readout
Signed-off-by: Mika Kahola
Anusha Srivatsa (1):
drm/i915/mtl: Pin assignment for TypeC
Gustavo Sousa (1):
drm/i915
() instead of msleep() (Andi)
Reviewed-by: Arun R Murthy
Signed-off-by: José Roberto de Souza
Signed-off-by: Mika Kahola
Signed-off-by: Bhanuprakash Modem
Signed-off-by: Imre Deak
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 288 +++---
.../gpu/drm
-off-by: Mika Kahola
Signed-off-by: Arun R Murthy
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 624 +-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 8 +-
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 1 +
drivers/gpu/drm/i915/display
Calculate port clock with C20 phy.
BSpec: 64568
Reviewed-by: Radhakrishna Sripada
Reviewed-by: Arun R Murthy
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 45 +++
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
.../gpu/drm/i915/display
As we already do with C10 chip, let's dump the pll
hw state for C20 as well.
Reviewed-by: Radhakrishna Sripada
Reviewed-by: Arun R Murthy
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20
drivers/gpu/drm/i915/display/intel_cx0_phy.h
Use MPLLA for DP2.0 rates 10G and 20G, when ssc is enabled.
v2: Fix typo in commit message (Animesh)
Reviewed-by: Radhakrishna Sripada
Reviewed-by: Arun R Murthy
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 7 +--
1 file changed, 5 insertions(+), 2
DP1.4 and DP20 voltage swing sequence for C20 phy.
Bspec: 65449, 67636, 67610
Reviewed-by: Arun R Murthy
Signed-off-by: Mika Kahola
Signed-off-by: Clint Taylor
Signed-off-by: Radhakrishna Sripada
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++
.../drm/i915/display
: Matt Atwood
Signed-off-by: Mika Kahola
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 19 ++
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 4 +
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers
Enabling and disabling sequence for Thunderbolt PLL.
Bspec: 64568
v2: Use intel_de_wait_for_register() (RK)
Reviewed-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 135 ++-
drivers/gpu/drm/i915/display/intel_cx0_phy.h
: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_tc.c | 30 -
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index 951b12ac51dc..b192265a3d78 100644
--- a/drivers/gpu/drm/i915
Readout hw state for Thunderbolt.
Reviewed-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++-
3 files
Finally, we can enable TC ports for Meteorlake.
Reviewed-by: Clint Taylor
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_display.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_tc.c | 28 +
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index b192265a3d78..4fca711a58bc 100644
--- a/drivers/gpu/drm
From: Gustavo Sousa
Xe_LPD+ defines interrupt bits for only DDI ports in the DE Port
Interrupt registers. The bits for Type-C ports are defined in the PICA
interrupt registers.
BSpec: 50064
Reviewed-by: Radhakrishna Sripada
Signed-off-by: Gustavo Sousa
Signed-off-by: Mika Kahola
every successful or unsuccessful
read or write operation. However, testing revealed that this
alone is not sufficient method an additiona delay is also
introduces anything from 200us to 300us. This delay is experimental
value and has no specification to back it up.
Signed-off-by: Mika Kahola
Currently we are not using watchdog timers for PSR/PSR2.
The patch disables these timers so they are not in use.
BSpec: 69895
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_psr.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a
7;s move reset to corresponding
timeout error and drop the excess reset function calls from
read/write functions.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915
table updates
PICA hotplug handling updates
Signed-off-by: Mika Kahola
Anusha Srivatsa (1):
drm/i915/mtl: Pin assignment for TypeC
Clint Taylor (1):
drm/i915/mtl: Initial DDI port setup
Gustavo Sousa (1):
drm/i915/mtl: Define mask for DDI AUX interrupts
Imre Deak (1):
drm/i915/mtl
From: Clint Taylor
Initialize c10 combo phy ports. TODO Type-C ports.
Cc: Radhakrishna Sripada
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b
Create a separate file to store registers for PICA chips
C10 and C20.
v2: Rename file (Jani)
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 136 ++
1 file changed, 136 insertions(+)
create mode 100644 drivers
Add DP rates for Meteorlake.
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_dp.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display
Calculate port clock with C20 phy.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 64 +++-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
3 files changed, 65 insertions(+), 5 deletions
programming (Khaled)
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/Makefile |1 +
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 1120 +
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 43
Add C20 HDMI state calculations and put HDMI table definitions
in use.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display
o times of level 1 preemphasis 0.
Fix this in the driver code as well.
v3: VSwing update (Clint)
Cc: Imre Deak
Cc: Uma Shankar
Signed-off-by: Clint Taylor
Signed-off-by: Radhakrishna Sripada
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 140 -
As we already do with C10 chip, let's dump the pll
hw state for C20 as well.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
3
Use MPLLA for DP2.0 rates 20G and 20G, when ssc is enabled.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display
pll programming (Gustavo)
Clear calibration banks for both lanes (Gustavo)
Signed-off-by: José Roberto de Souza
Signed-off-by: Mika Kahola
Signed-off-by: Bhanuprakash Modem
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 266 +++---
.../gpu/drm/i915
based on changes in BSpec consolidated table
v3: Rename intel_c20_read() to intel_c20_sram_read() (Gustavo)
Use context and correct MPLLA reg bit to select if MPLLA is in
use or not (Gustavo)
Signed-off-by: Mika Kahola
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/display
Enabling and disabling sequence for Thunderbolt PLL.
v2: Use __intel_de_wait_for_register() instead of
__intel_wait_for_register() (Jani)
Use '0' instead of ~XELPDP_TBT_CLOCK_ACK (Gustavo)
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_p
Readout hw state for Thunderbolt.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 27
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++-
3 files changed, 32 insertions(+), 2 deletions
From: Anusha Srivatsa
Unlike previous platforms that used PORT_TX_DFLEXDPSP
for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1
from which the max_lanes has to be calculated.
Bspec: 50235, 65380
Cc: Mika Kahola
Cc: Imre Deak
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Signed-off-by
provides a dedicated HPD
control register for each supported port, so we loop over ports
ourselves instead of using intel_hpd_hotplug_enables() or
intel_get_hpd_pins().
BSpec: 49305, 55726, 65107, 65300
Signed-off-by: Mika Kahola
Signed-off-by: Madhumitha Tolakanahalli Pradeep
Signed-off-by
From: Imre Deak
The HPD live status for MTL has to be read from different set of
registers. MTL deserves a new function for this purpose
and cannot reuse the existing HPD live status detection
Signed-off-by: Anusha Srivatsa
Signed-off-by: Imre Deak
Signed-off-by: Mika Kahola
---
drivers
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