ction (Daniel)
v4: remove updating bpc for display info as it may be overridden
when parsing EDID. Instead, check bpc for DP branch device
during compute_config
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_dp.c | 17 -
1 file changed, 16 insertions(+), 1 del
ink training is requested we should perform it always
> */
> if ((intel_dp->compliance_test_type ==
> DP_TEST_LINK_TRAINING) ||
> (!drm_dp_channel_eq_ok(link_status, intel_dp-
> >lane_count))) {
Should we place this check as part drm_dp_helper()'s
drm_dp_channel_eq_ok() routine as th
+1 for this cleanup
Reviewed-by: Mika Kahola
On Thu, 2016-09-01 at 15:08 -0700, Manasi Navare wrote:
> From: Dhinakaran Pandiyan
>
> Wrap the max. vswing check in a separate function.
> This makes the clock recovery phase of DP link training cleaner
>
> Signed-off-by: D
ING_MASK;
>
> /* Update training set as requested by target */
> intel_get_adjust_train(intel_dp, link_status);
> if (!intel_dp_update_link_train(intel_dp)) {
> DRM_ERROR("failed to update link
> tra
; times\n");
> }
>
> intel_dp_set_idle_link_train(intel_dp);
>
> - if (channel_eq)
> - DRM_DEBUG_KMS("Channel EQ done. DP Training
> successful\n");
> + return intel_dp->channel_eq_status;
> +
> }
>
> voi
er
> *encoder,
> struct intel_crtc_state *pipe_config);
> void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool
> state);
> uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
> +bool intel_ddi_link_train(struct i
count;
> + lane_count >>= 1) {
>
> link_clock = common_rates[clock];
> link_avail =
> intel_dp_max_data_rate(link_clock,
--
Mika Kahola - Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Fri, 2016-09-02 at 11:05 +0300, Mika Kahola wrote:
> +1 for this cleanup
>
> Reviewed-by: Mika Kahola
Received couple of compiler warnings to be cleaned up
drivers/gpu/drm/i915/intel_dp_link_training.c: In function
‘intel_dp_link_max_vswing_reached’:
drivers/gpu
On Tue, 2016-09-06 at 17:13 -0700, Manasi Navare wrote:
> From: Dhinakaran Pandiyan
>
> Wrap the max. vswing check in a separate function.
> This makes the clock recovery phase of DP link training cleaner
>
> v2:
> Fixed the Compiler warning (Mika Kahola)
>
> Signed-
intel_get_adjust_train(intel_dp, link_status);
> if (!intel_dp_update_link_train(intel_dp)) {
> DRM_ERROR("failed to update link
> training\n");
> - break;
> + return false;
> }
> +
> + if ((intel_dp->train_set[0] &
> DP_TRAIN_VOLTAGE_SWING_MASK) ==
> + voltage)
> + ++voltage_tries;
> + else
> + voltage_tries = 1;
> +
> + if (intel_dp_link_max_vswing_reached(intel_dp))
> + ++max_vswing_tries;
> +
> }
> }
>
--
Mika Kahola - Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Reviewed-by: Mika Kahola
On Fri, 2016-09-02 at 22:05 +0300, Pandiyan, Dhinakaran wrote:
> On Fri, 2016-09-02 at 14:20 +0300, Mika Kahola wrote:
> >
> > On Thu, 2016-09-01 at 15:08 -0700, Manasi Navare wrote:
> > >
> > > Fix the number of tries in c
make use
> of common_rates array (Mika Kahola)
> * Changed INTEL_INFO to INTEL_GEN (David Weinehall)
>
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 125
> +++---
> drivers/gpu/drm/i915/intel_dp.c |
el_dp *intel_dp, struct
> drm_connector *connector);
> void intel_dp_mst_suspend(struct drm_device *dev);
> void intel_dp_mst_resume(struct drm_device *dev);
> +u8 intel_dp_max_lane_count(struct intel_dp *intel_dp);
> int intel_dp_max_link_rate(struct intel_dp *intel_dp);
> int intel_dp_link_rate_index(struct intel_dp *intel_dp, int
> *common_rates,
> int link_rate);
> @@ -1448,6 +1449,8 @@ intel_dp_pre_emphasis_max(struct intel_dp
> *intel_dp, uint8_t voltage_swing);
> void intel_dp_compute_rate(struct intel_dp *intel_dp, int
> port_clock,
> uint8_t *link_bw, uint8_t *rate_select);
> bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
> +int intel_dp_common_rates(struct intel_dp *intel_dp, int
> *common_rates);
> +bool intel_dp_upfront_link_train(struct intel_dp *intel_dp);
> bool
> intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t
> link_status[DP_LINK_STATUS_SIZE]);
>
--
Mika Kahola - Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
quest.
- Do full modeset
- Enable DRM_MODE_ATOMIC_ALLOW_MODESET and try to do atmic commit.
Kernel should now allow atomic modeset.
For: VIZ-6955
Signed-off-by: Mika Kahola
---
tests/Makefile.sources | 1 +
tests/kms_atomic_allow_modeset.c
On Tue, 2017-04-04 at 14:28 +0200, Maarten Lankhorst wrote:
> Hey,
>
> Op 04-04-17 om 13:59 schreef Mika Kahola:
> >
> > When doing a full atomic modeset, kernel should fail if the flag
> > DRM_MODE_ATOMIC_ALLOW_MODESET is not set. Let's add this test as
> >
Looks ok to me.
On Thu, 2017-04-06 at 12:15 -0700, Rodrigo Vivi wrote:
> Also in a way that reuse bdw+ for all next platforms.
>
> Signed-off-by: Rodrigo Vivi
Reviewed-by: Mika Kahola
> ---
> drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +-
> 1 file changed, 1 insert
On Wed, 2017-03-29 at 11:53 +0200, Maarten Lankhorst wrote:
> Op 15-03-17 om 09:43 schreef Mika Kahola:
> >
> > This test case introduces concurrently running test cases for
> > atomic
> > modesetting.
> >
> > The first test or thread draws blue backroun
ad changes resolution from higher to lower one and back.
For: VIZ-7022
v2: use igt_fork instead of pthreads to create concurrent test runs (Maarten)
v3: use igt_display calls instead of raw drm calls for display updates (Maarten)
Various cleanups on accessing drm connector (Maarten)
Signed-of
Atomic has a few special cases around async commits and event generation
that we need to test. This patch addresses these two tests
- kernel rejects events on a disabled pipe
- events on a pipe that is getting enabled/disabled
For: VIZ-6954
Signed-off-by: Mika Kahola
---
tests
quest.
- Do full modeset/change active property
- Enable DRM_MODE_ATOMIC_ALLOW_MODESET and try to do atmic commit.
Kernel should now allow atomic modeset.
For: VIZ-6955
v2: create own testcase (Maarten)
v3: add test for active property change (Maarten)
Signed-off-by: Mika Kahola
---
ining operation. The revert above was identified
> via a
> bisect as the cause of some of Skylake's PSR woes. This patch,
> largely
> based on
>
> commit 4e96c97742f4201edf1b0f8e1b1b6b2ac6ff33e7
> Author: Mika Kahola
> Date: Wed Apr 29 09:17:39 2015 +0300
> drm/i
ow for sure what is the color range in use.
Reviewed-by: Mika Kahola
>
> v2: Add more details to the commit message.
> v3: Force all tests to use full range.
> Cc: Ville Syrjälä
> Signed-off-by: Ander Conselvan de Oliveira
>
> ---
> lib/igt_kms.c | 7 ++-
> 1
work)
> > {
> > struct drm_i915_private *dev_priv =
> > @@ -552,7 +634,7 @@ static void i915_hpd_poll_init_work(struct
> > work_struct *work)
> > * in the middle of disabling polling
> > */
> > if (!enabled)
> > - drm_helper_hpd_irq_event(dev);
> > + intel_hpd_irq_event(dev);
> > }
> Just wondering, as I saw previously drm_helper_hpd_irq_event function
> was used, which basically does the same thing, except doing memcmp
> for detecting the edid change. Is it only Intel specific change? As
> we
> could just add this modification to existing helper function or add
> another helper function to the drm (drm_probe_helper.c), so that it
> is
> also usable elsewhere..
I second Stanislav's proposal to add this feature as part of drm. This
edid check could be part of existing drm_helper_hpd_irq_event()
function. Other drivers might find this change useful.
>
> >
> >
> > /**
> --
> Best Regards,
>
> Lisovskiy Stanislav
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Mika Kahola - Intel OTC
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
the supported rotations
> v3: Move hardcodings to a single function(Ville)
>
> [1]: https://patchwork.freedesktop.org/patch/209647/
>
> Cc: Radhakrishna Sripada
> Cc: Ville Syrjälä
> Cc: Daniel Vetter
> Cc: Rodrigo Vivi
> Cc: Maarten Lankhorst
> Cc: Mika Kahola
&
r bit that maps directly to the link clock.
> So this patch creates a separate function in intel_dpll_mgr.c
> to obtain the write array PLL Params and compares the set
> pll_params with the table to get the corresponding link
> clock.
>
> Cc: Rodrigo Vivi
> Cc: Mika Kahola
Patch look ok to me.
Reviewed-by: Mika Kahola
On Wed, 2018-05-23 at 15:44 -0700, Paulo Zanoni wrote:
> From: Manasi Navare
>
> PLLs are the source clocks for the DDIs so in order
> to determine the ddi clock we need to check the PLL
> configuration.
>
> This gets a
pipe select bits can still be set in the register. Thus
> we have to ignore those bits. OTOH i965 still allows the cursors
> to move between pipes thus we have to trust the bits there.
>
Reviewed-by: Mika Kahola
> Signed-off-by: Ville Syrjälä
> ---
> d
e care of gvt uses as well
>
Reviewed-by: Mika Kahola
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/gvt/fb_decoder.c | 12 ++--
> drivers/gpu/drm/i915/i915_reg.h | 22 +++---
> drivers/gpu/drm/i915/intel_display.c | 16 ---
On Tue, 2018-01-30 at 22:38 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We disable trickle feed whenever possible, except for the cursors
> on SNB/IVB. Let's try disabling it there too if for no other reason
> than consistency.
>
Reviewed-by: Mika Kahola
On Tue, 2018-01-30 at 22:38 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Call the enum i9xx_plane_id variable i9xx_plane like we do elsewhere.
>
> Cc: Hans de Goede
Reviewed-by: Mika Kahola
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/intel
the patch looks fine to me.
On Mon, 2018-05-21 at 17:25 -0700, Paulo Zanoni wrote:
> Just like DP, HDMI needs to implement these flows. The side effect is
> that HDMI is now going to rely on the ISR bits, just like DP.
>
Reviewed-by: Mika Kahola
> Signed-off-by: Paulo Zanoni
>
Reviewed-by: Mika Kahola
On Tue, 2016-05-31 at 12:08 +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> The VBT has these mysterious H/V image sizes as part of the display
> timings. Looking at some dumps those appear to be the physical
> dimensions in mm. Wh
o drm (Daniel)
v4: Use of drm_dp_helper routines to collect data (Ville)
Mika Kahola (11):
drm: Add missing DP downstream port types
drm: Read DP downstream port capabilities
drm: Helper to read DP branch device type
drm: Helper to read max clock rate
drm: Helper to read max bits per component
Add missing DisplayPort downstream port types. The introduced
new port types are DP++ and Wireless.
Signed-off-by: Mika Kahola
---
include/drm/drm_dp_helper.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 5a848e7..e384c7f
SW revision is mandatory field for DisplayPort branch
devices. This is defined in DPCD register field 0x50A.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/drm_dp_helper.c | 22 ++
include/drm/drm_dp_helper.h | 4 +++-
2 files changed, 25 insertions(+), 1 deletion
DisplayPort branch device may define max supported bits per
component. Update display info based on this value if bpc
is defined.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_dp.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b
Helper routine to read out maximum supported pixel rate
for DisplayPort legay VGA converter or TMDS clock rate
for other digital legacy converters. The helper returns
clock rate in kHz.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/drm_dp_helper.c | 28
include/drm
Helper routine to read out maximum supported bits per
component for DisplayPort legay converters.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/drm_dp_helper.c | 31 +++
include/drm/drm_dp_helper.h | 2 ++
2 files changed, 33 insertions(+)
diff --git a/drivers
Read DisplayPort branch device id string.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/drm_dp_helper.c | 12
include/drm/drm_dp_helper.h | 2 ++
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index bac0ccc
: Mika Kahola
---
drivers/gpu/drm/drm_dp_helper.c | 14 ++
include/drm/drm_dp_helper.h | 1 +
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index c4149fd..7d3b245 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b
computation moved to drm (Ville, Daniel)
v3: Sink pixel rate computation moved to drm_dp_max_sink_dotclock()
function (Daniel)
v4: Use of drm_dp_helper.c routines to compute max pixel clock (Ville)
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_dp.c | 17 +
1 file
Read DisplayPort branch device info from through debugfs
interface.
v2: use drm_dp_helper routines to collect data
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/i915_debugfs.c | 66 +
1 file changed, 66 insertions(+)
diff --git a/drivers/gpu/drm/i915
Read DisplayPort downstream port capabilities. Depending on
the DP port the capabilities are defined in length of 1 byte
or 4 bytes depending if the detailed capability information is
available.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/drm_dp_helper.c | 27
HW revision is mandatory field for DisplayPort branch
devices. This is defined in DPCD register field 0x509.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/drm_dp_helper.c | 21 +
include/drm/drm_dp_helper.h | 7 +++
2 files changed, 28 insertions(+)
diff --git a
On Thu, 2016-06-09 at 11:02 +0300, Ville Syrjälä wrote:
> On Mon, Jun 06, 2016 at 04:29:07PM +0300, Mika Kahola wrote:
> > Helper routine to read out maximum supported bits per
> > component for DisplayPort legay converters.
> >
> > Signed-off-by: Mika Kahola
&
o drm (Daniel)
v4: Use of drm_dp_helper routines to collect data (Ville)
v5: Remove duplicate code and unnecessary functions from drm_dp_helper (Ville)
Mika Kahola (10):
drm: Add missing DP downstream port types
drm: Drop VGA from bpc definitions
drm: Helper to read max clock rate
drm: Helper to
Drop "VGA" from bits per component definitions as these
are also used by other standards such as DVI, HDMI,
DP++.
Signed-off-by: Mika Kahola
---
include/drm/drm_dp_helper.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/drm/drm_dp_helper.h b/i
HW revision is mandatory field for DisplayPort branch
devices. This is defined in DPCD register field 0x509.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/drm_dp_helper.c | 21 +
include/drm/drm_dp_helper.h | 7 +++
2 files changed, 28 insertions(+)
diff --git a
Helper routine to read out maximum supported bits per
component for DisplayPort legay converters.
v2: Return early if detailed port cap info is not available.
Replace if-else ladder with switch-case (Ville)
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/drm_dp_helper.c | 42
DisplayPort branch device may define max supported bits per
component. Update display info based on this value if bpc
is defined.
v2: cleanup to match the drm_dp_helper.c patches introduced
earlier in this series
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_dp.c | 9
Read DisplayPort branch device info from through debugfs
interface.
v2: use drm_dp_helper routines to collect data
v3: cleanup to match the drm_dp_helper.c patches introduced
earlier in this series
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/i915_debugfs.c | 72
lle)
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_dp.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f97cd53..3b09230 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/
)
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/drm_dp_helper.c | 33 +
include/drm/drm_dp_helper.h | 2 ++
2 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index eeaf5a7..1199a02 100644
--- a
Add missing DisplayPort downstream port types. The introduced
new port types are DP++ and Wireless.
Signed-off-by: Mika Kahola
---
include/drm/drm_dp_helper.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 5a848e7..e384c7f
Read DisplayPort branch device id string.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/drm_dp_helper.c | 12
include/drm/drm_dp_helper.h | 2 ++
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 3dab8a4
SW revision is mandatory field for DisplayPort branch
devices. This is defined in DPCD register field 0x50A.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/drm_dp_helper.c | 21 +
include/drm/drm_dp_helper.h | 2 ++
2 files changed, 23 insertions(+)
diff --git a
It has been turned out that in some HW combination the DisplayPort
fast link training feature caused screen flickering. Let's revert
this feature for now until we can ensure that the feature works for
all platforms.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393
Signed-off-by:
p.org/show_bug.cgi?id=91393
Reviewed-by: Jani Nikula
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_dp.c | 3 ---
drivers/gpu/drm/i915/intel_dp_link_training.c | 26 ++
drivers/gpu/drm/i915/intel_drv.h | 2 --
3 files changed, 2 inserti
more conservative
approach this feature is disabled by default.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_params.c| 4
drivers/gpu/drm/i915/intel_dp_link_training.c | 11 ++-
3 files changed, 15
training is started with zero values.
The patch is fix for reported screen flickering issue in
https://bugs.freedesktop.org/show_bug.cgi?id=91393
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_dp.c | 6 ++
drivers/gpu/drm/i915/intel_dp_link_training.c | 27
isabled when
> enabling the fdi rx/tx and pch transcoder&port. But somehow this is
> only needed when enabling, not also when disabling.
>
> Cc: Ville Syrjälä
> Signed-off-by: Daniel Vetter
Tested-by: Mika Kahola
> ---
> drivers/gpu/drm/i915/intel_display.c | 12 +++
isabled when
> enabling the fdi rx/tx and pch transcoder&port. But somehow this is
> only needed when enabling, not also when disabling.
>
> Cc: Ville Syrjälä
> Signed-off-by: Daniel Vetter
Reviewed-by: Mika Kahola
> ---
> drivers/gpu/drm/i915/intel_display.c | 12 +++
training is started with zero values.
v2:
Readout DPCD register to check if no aux handshaking is
required in link training (Ander)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_dp.c | 8 +-
drivers/gpu/drm
cted the retry loop(Jani), rebase
>
> Cc: Jani Nikula
Tested-by: Mika Kahola
> Signed-off-by: vkorjani
> Signed-off-by: Deepak M
> ---
> drivers/gpu/drm/i915/intel_bios.c | 6 +++
> drivers/gpu/drm/i915/intel_bios.h | 1 +
>
On Tue, 2015-12-01 at 04:17 +0530, Deepak M wrote:
> v3: rebase
>
> Cc: Jani Nikula
Tested-by: Mika Kahola
> Signed-off-by: Deepak M
> ---
> drivers/gpu/drm/i915/intel_opregion.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gp
t; Cc: Jani Nikula
Tested-by: Mika Kahola
> Signed-off-by: Deepak M
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_opregion.c | 9 +
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i
On Tue, 2015-12-01 at 04:17 +0530, Deepak M wrote:
> Calling the validate_vbt before assiging the opregion vbt blob.
> Size of the VBT blob cant be more than 6KB when VBT is present
> in mailbox 4.
>
> Cc: Jani Nikula
Tested-by: Mika Kahola
> Signed-off-by: Deepak M
> -
y where we get the complete
> opregion dump and pick the VBT from the dump wrt to
> the VBT offset.
>
> Cc: Jani Nikula
Tested-by: Mika Kahola
> Signed-off-by: Deepak M
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 29 +
> drivers/gpu/drm/i915/
When testing this patch on my BXT-M I received this error message
Hardware name: Intel Corp. Broxton M/RVP, BIOS
BXTM_IFWI_X64_R_2015_49_2_03 11/25/2015
[0.00] [ cut here ]
[0.00] WARNING: CPU: 0 PID: 0 at drivers/iommu/dmar.c:829
warn_invalid_dmar+0x81/0xa
move handling a null crtc_state, with all transitional helpers
> gone this can no longer happen.
>
Reviewed-by: Mika Kahola
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
> + crtc->active = crtc_state->base.active;
> +
> + if (crtc_state->base.active) {
> + dev_priv->active_crtcs |= 1 << crtc->pipe;
> +
> + if (IS_BROADWEL
training is started with zero values.
v3: Remove cached old link parameters. Instead, disable
fast link training feature when link parameters are
set (Ville)
v2: Readout DPCD register to check if no aux handshaking is
required in link training (Ander)
Signed-off-by: Mika Kahola
On Tue, 2015-12-15 at 10:26 +, Chris Wilson wrote:
> On Tue, Dec 15, 2015 at 12:22:40PM +0200, Mika Kahola wrote:
> > On Tue, 2015-11-24 at 11:29 +0100, Maarten Lankhorst wrote:
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/
On Wed, 2015-12-16 at 14:41 +0200, Ville Syrjälä wrote:
> On Wed, Dec 16, 2015 at 02:26:58PM +0200, Mika Kahola wrote:
> > Disable DP fast link training if DP link configuration
> > changes. If one of the DP link parameters i.e. link
> > bandwidth, lane count, rate selecti
#4 otherwise.
>
Tested-by: Mika Kahola
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_opregion.c | 25 +++--
> 2 files changed, 24 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/d
aux handshaking is
required in link training (Ander)
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_dp.c | 8 +++-
drivers/gpu/drm/i915/intel_dp_link_training.c | 17 +
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 25
On Thu, 2015-12-17 at 15:16 +0200, Ville Syrjälä wrote:
> On Thu, Dec 17, 2015 at 02:46:03PM +0200, Mika Kahola wrote:
> > Disable DP fast link training if DP link configuration
> > changes. If one of the DP link parameters i.e. link
> > bandwidth, lane count, rate selecti
parameters. Instead, disable
fast link training feature when link parameters are
set (Ville)
v2: Readout DPCD register to check if no aux handshaking is
required in link training (Ander)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393
Signed-off-by: Mika Kahola
---
drivers/gpu
These two patches are fixes for DP link trainging failures and flickering issues
reported by
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393
Mika Kahola (2):
drm/i915: Disable fast link training if DP config changes
drm/i915: Check DP no aux transaction bit on link training
Check if no AUX transactions are required on DP link training.
If this bit is set, we can reuse the known good drive current
and pre-emphasis level from the last "full" link training.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91393
Signed-off-by: Mika Kahola
---
drive
On Mon, 2016-10-17 at 16:30 +0200, Daniel Vetter wrote:
> On Mon, Oct 17, 2016 at 02:28:37PM +0300, Mika Kahola wrote:
> >
> > + for (int i = 0; i < iterations; i++) {
> > + igt_info("%d/%d: Testing connector %s using pipe
> > %s with %d plan
due to unmet test requirements
Signed-off-by: Mika Kahola
---
tests/Makefile.sources | 1 +
tests/kms_plane_multiple.c | 475 +
2 files changed, 476 insertions(+)
create mode 100644 tests/kms_plane_multiple.c
diff --git a/tests/Makefile.sourc
On Mon, 2016-10-24 at 10:28 +0200, Daniel Vetter wrote:
> On Thu, Oct 20, 2016 at 12:27:23PM +0300, Mika Kahola wrote:
> >
> > This is a testcase with multiple planes. The idea here is the
> > following
> >
> > - draw a uniform frame with blue color
> &g
On Tue, 2016-11-01 at 09:25 +0100, Maarten Lankhorst wrote:
> Op 20-10-16 om 11:27 schreef Mika Kahola:
> >
> > This is a testcase with multiple planes. The idea here is the
> > following
> >
> > - draw a uniform frame with blue color
> > - grab crc for
Rename nplanes variable to max_planes
To optimize test execution, run iterations after the modeset
v2: Keep a logfile on random number seeds per subtest that are not skipped
due to unmet test requirements
Signed-off-by: Mika Kahola
---
tests/Makefile.sources | 1 +
tests/kms_plane_
Thanks for the review.
On Mon, 2016-11-07 at 14:04 +0100, Maarten Lankhorst wrote:
> Op 02-11-16 om 10:32 schreef Mika Kahola:
> >
> > This is a testcase with multiple planes. The idea here is the
> > following
> >
> > - draw a uniform frame with blue co
ions after the modeset
v2: Keep a logfile on random number seeds per subtest that are not skipped
due to unmet test requirements
Signed-off-by: Mika Kahola
---
tests/Makefile.sources | 1 +
tests/kms_plane_multiple.c | 501 +
2 files ch
On Tue, 2016-11-08 at 14:14 +0100, Maarten Lankhorst wrote:
> Op 08-11-16 om 12:54 schreef Mika Kahola:
> >
> > This is a testcase with multiple planes. The idea here is the
> > following
> >
> > - draw a uniform frame with blue color
> > - grab crc for
me nplanes variable to max_planes
To optimize test execution, run iterations after the modeset
v2: Keep a logfile on random number seeds per subtest that are not skipped
due to unmet test requirements
Signed-off-by: Mika Kahola
---
tests/Makefile.sources | 1 +
tests/kms_plane_multip
Tested-by: Mika Kahola
On Tue, 2016-04-26 at 13:27 +0300, Jani Nikula wrote:
> Request the GPIO by index through the consumer API. For now, use a
> quick
> hack to store the already requested ones, simply because I have no
> idea
> whether this actually works or not, and I have no
'i915_display_info' that the plane is invisible
- switch back to higher resolution mode
- check from debugfs 'i915_display_info' that the plane is visible again
- repeat number of iterations, default 64
Signed-off-by: Mika Kahola
---
tests/Makefile.sources | 1 +
tests/kms_
This change is needed to enable DSI/MIPI display on BXT
Reviewed-by: Mika Kahola
On Tue, 2016-02-02 at 23:21 +0530, Ramalingam C wrote:
> We need to enable DSI PLL before configuring the DSI registers.
>
> Signed-off-by: Ramalingam C
> ---
> drivers/gpu/drm/i915/intel_dsi.c
On Wed, 2016-02-03 at 11:27 +0200, Jani Nikula wrote:
> On Wed, 03 Feb 2016, "Thulasimani, Sivakumar"
> wrote:
> > just realized that intel_dsi_init is not called from setup outputs for
> > BXT. is this expected ?
> > if so when is it expected to be added ?
> >
> > Again, the current code in int
On Wed, 2016-02-03 at 11:28 +0200, Jani Nikula wrote:
> On Tue, 02 Feb 2016, Ramalingam C wrote:
> > We need to enable DSI PLL before configuring the DSI registers.
> >
> > Signed-off-by: Ramalingam C
> > ---
> > drivers/gpu/drm/i915/intel_dsi.c |2 +-
> > 1 file changed, 1 insertion(+), 1 d
Skip DDI PLL selection if display type is DSI/MIPI.
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/intel_display.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d7de2a5
gt; from pipe config to calculate txbyteclkhs. Fix it in this patch.
> >
> > V2: dsi_pixel_format_bpp is used to retrieve the bpp from pixel_format
> > [Review: Jani]
> >
> > Signed-off-by: Deepak M
> > Signed-off-by: Yogesh Mohan Marimuthu
> > Sig
Additional 50 ms delay is needed between DPCD reads on HP Bizlink 1326
DP to VGA adapter. Having said that, I haven't noticed a need for
additional delay between DPCD reads on other DP-VGA dongles.
While at it, let's replace mdelay() with usleep_range() routine.
Signed-off-by: M
On Tue, 2016-03-15 at 14:26 +0100, Daniel Vetter wrote:
> On Tue, Mar 15, 2016 at 01:38:58PM +0200, Mika Kahola wrote:
> > Additional 50 ms delay is needed between DPCD reads on HP Bizlink 1326
> > DP to VGA adapter. Having said that, I haven't noticed a need for
> > add
Test MIPI/DSI display suspend/resume cycle on Apollolake.
Jani Nikula (1):
drm/i915/bxt: add bxt dsi gpio element support
Mika Kahola (2):
drm/i915: Get the i2c bus number from the ACPI
drm/i915: Adding the parsing logic for the i2c element
drivers/gpu/drm/i915/i915_drv.c
Syrjälä
Signed-off-by: Deepak M
Signed-off-by: Mika Kahola
---
drivers/gpu/drm/i915/i915_drv.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 10 +++
drivers/gpu/drm/i915/intel_acpi.c | 59 +++
3 files changed, 71 insertions(+)
diff --git a/drivers/gpu/drm/i915
101 - 200 of 995 matches
Mail list logo
