[Intel-gfx] [PATCH 04/16] drm/i915/gen8: Add dynamic page trace events

2015-05-26 Thread Michel Thierry
The dynamic page allocation patch series added it for GEN6, this patch adds them for GEN8. v2: Consolidate pagetable/page_directory events v3: Multiple rebases. v4: Rebase after s/page_tables/page_table/. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v3+) --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 07/16] drm/i915/gen8: Generalize PTE writing for GEN8 PPGTT

2015-05-26 Thread Michel Thierry
page table level and here is no exception. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.c | 56 ++--- 1 file changed, 39 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gp

[Intel-gfx] [PATCH 06/16] drm/i915/gen8: Add 4 level switching infrastructure and lrc support

2015-05-26 Thread Michel Thierry
register. Cc: Akash Goel Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2+) --- drivers/gpu/drm/i915/i915_gem_gtt.c | 62 ++--- drivers/gpu/drm/i915/i915_gem_gtt.h | 2 ++ drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_lrc.c

[Intel-gfx] [PATCH 01/16] drm/i915: Remove unnecessary gen8_clamp_pd

2015-05-26 Thread Michel Thierry
gen8_clamp_pd clamps to the next page directory boundary, but the macro gen8_for_each_pde already has a check to stop at the page directory boundary. Furthermore, i915_pte_count also restricts to the next page table boundary. Suggested-by: Akash Goel Signed-off-by: Michel Thierry --- drivers

[Intel-gfx] [PATCH 13/16] drm/i915: object size needs to be u64

2015-05-26 Thread Michel Thierry
In a 48b world, users can try to allocate buffers bigger than 4GB; in these cases it is important that size is a 64b variable. Also added a warning for illegal bind with size = 0. Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem.c | 5 +++-- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 05/16] drm/i915/gen8: implement alloc/free for 4lvl

2015-05-26 Thread Michel Thierry
patches cleaner. Cc: Akash Goel Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2+) --- drivers/gpu/drm/i915/i915_gem_gtt.c | 198 ++-- drivers/gpu/drm/i915/i915_gem_gtt.h | 12 ++- 2 files changed, 177 insertions(+), 33 deletions(-) diff --git a

[Intel-gfx] [PATCH 14/16] drm/i915: Check against correct user_size limit in 48b ppgtt mode

2015-05-26 Thread Michel Thierry
v2: Use the default ctx to infer the ppgtt max size (Akash). Cc: Akash Goel Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_userptr.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c b/drivers/g

[Intel-gfx] [PATCH 10/16] drm/i915/gen8: Initialize PDPs

2015-05-26 Thread Michel Thierry
flush. This commit also moves gen8_initialize_pt next to the other initialize page functions. v2: Handle scratch_pdp allocation failure correctly, and keep initialize_px functions together (Akash) Suggested-by: Akash Goel Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.c

[Intel-gfx] [PATCH 12/16] drm/i915/gen8: Add ppgtt info and debug_dump

2015-05-26 Thread Michel Thierry
v2: Clean up patch after rebases. v3: gen8_dump_ppgtt for 32b and 48b PPGTT. v4: Use used_pml4es/pdpes (Akash). Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2+) --- drivers/gpu/drm/i915/i915_debugfs.c | 18 drivers/gpu/drm/i915/i915_gem_gtt.c | 88

[Intel-gfx] [PATCH] tests/gem_ppgtt: Check Wa32bitOffsets workarounds

2015-05-26 Thread Michel Thierry
Test EXEC_OBJECT_NEEDS_32BADDRESS flag to use reserved 32b segment. Driver will try to use lower PDPs of each PPGTT for the objects requiring Wa32bitGeneralStateOffset or Wa32bitInstructionBaseOffset. Signed-off-by: Michel Thierry --- tests/gem_ppgtt.c | 90

[Intel-gfx] [PATCH 11/16] drm/i915: Expand error state's address width to 64b

2015-05-26 Thread Michel Thierry
Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_drv.h | 4 ++-- drivers/gpu/drm/i915/i915_gpu_error.c | 17 + 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 16/16] drm/i915/gen8: Flip the 48b switch

2015-05-26 Thread Michel Thierry
Use 48b addresses if hw supports it and i915.enable_ppgtt=3. Note, aliasing PPGTT remains 32b only. Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.c | 5 + drivers/gpu/drm/i915/i915_params.c | 2 +- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a

Re: [Intel-gfx] [PATCH 09/16] drm/i915/gen8: Add 4 level support in insert_entries and clear_range

2015-05-26 Thread Michel Thierry
On 5/26/2015 3:21 PM, Michel Thierry wrote: When 48b is enabled, gen8_ppgtt_insert_entries needs to read the Page Map Level 4 (PML4), before it selects which Page Directory Pointer (PDP) it will write to. Similarly, gen8_ppgtt_clear_range needs to get the correct PDP/PD range. This patch was

Re: [Intel-gfx] [PATCH 15/16] drm/i915: Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset

2015-05-26 Thread Michel Thierry
On 5/26/2015 4:25 PM, Daniel Vetter wrote: On Tue, May 26, 2015 at 03:21:22PM +0100, Michel Thierry wrote: There are some allocations that must be only referenced by 32bit offsets. To limit the chances of having the first 4GB already full, objects not requiring this workaround don't us

[Intel-gfx] [PATCH] drm/i915: limit PPGTT size to 2GB in 32-bit platforms

2015-05-28 Thread Michel Thierry
We already set this limit for the GGTT. This is a temporary patch until a full replacement of size_t variables (inadequate in 32-bit kernel) is in place. Regression from: commit a4e0bedca678c81eea4cd79a4bd502335639f73a Author: Michel Thierry Date: Wed Apr 8 12:13:35

Re: [Intel-gfx] [PATCH] drm/i915: limit PPGTT size to 2GB in 32-bit platforms

2015-05-28 Thread Michel Thierry
On 5/28/2015 4:39 PM, Chris Wilson wrote: On Thu, May 28, 2015 at 04:24:47PM +0100, Michel Thierry wrote: We already set this limit for the GGTT. This is a temporary patch until a full replacement of size_t variables (inadequate in 32-bit kernel) is in place. Regression from: commit

[Intel-gfx] [PATCH v2] drm/i915: limit PPGTT size to 2GB in 32-bit platforms

2015-05-28 Thread Michel Thierry
: Michel Thierry Date: Wed Apr 8 12:13:35 2015 +0100 drm/i915: Use complete address space in true PPGTT v2: Prettify code and explain why this is needed. (Chris) Suggested-by: Daniel Vetter Cc: Mika Kuoppala Cc: Chris Wilson Signed-off-by: Michel Thierry --- drivers/gpu

Re: [Intel-gfx] [PATCH v2] drm/i915: limit PPGTT size to 2GB in 32-bit platforms

2015-05-29 Thread Michel Thierry
On 5/28/2015 10:14 PM, Chris Wilson wrote: On Thu, May 28, 2015 at 06:09:34PM +0100, Michel Thierry wrote: And prevent overflow warning during compilation. We already set this limit for the GGTT. This is a temporary patch until a full replacement of size_t variables (inadequate in 32-bit

Re: [Intel-gfx] [PATCH 02/21] drm/i915/gtt: Workaround for HW preload not flushing pdps

2015-05-29 Thread Michel Thierry
On 5/22/2015 6:04 PM, Mika Kuoppala wrote: With BDW/SKL and 32bit addressing mode only, the hardware preloads pdps. However the TLB invalidation only has effect on levels below the pdps. This means that if pdps change, hw might access with stale pdp entry. To combat this problem, preallocate the

Re: [Intel-gfx] [PATCH 02/21] drm/i915/gtt: Workaround for HW preload not flushing pdps

2015-05-29 Thread Michel Thierry
On 5/29/2015 12:05 PM, Michel Thierry wrote: On 5/22/2015 6:04 PM, Mika Kuoppala wrote: With BDW/SKL and 32bit addressing mode only, the hardware preloads pdps. However the TLB invalidation only has effect on levels below the pdps. This means that if pdps change, hw might access with stale pdp

[Intel-gfx] [PATCH v3] drm/i915: limit PPGTT size to 2GB in 32-bit platforms

2015-05-29 Thread Michel Thierry
We already set this limit for the GGTT. This is a temporary patch until a full replacement of size_t variables (inadequate in 32-bit kernel) is in place. Regression from: commit a4e0bedca678c81eea4cd79a4bd502335639f73a Author: Michel Thierry Date: Wed Apr 8 12:13:35

Re: [Intel-gfx] [PATCH 01/21] drm/i915/gtt: Mark TLBS dirty for gen8+

2015-06-01 Thread Michel Thierry
On 5/22/2015 6:04 PM, Mika Kuoppala wrote: When we touch gen8+ page maps, mark them dirty like we do with previous gens. Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_gtt.c | 21 +++-- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/gp

Re: [Intel-gfx] [PATCH 06/21] drm/i915/gtt: Remove _single from page table allocator

2015-06-02 Thread Michel Thierry
On 5/22/2015 6:04 PM, Mika Kuoppala wrote: We are always allocating a single page. No need to be verbose so remove the suffix. Signed-off-by: Mika Kuoppala I saw another of your patches will take care of i915_dma_map_single/i915_dma_unmap_single... Reviewed-by: Michel Thierry

Re: [Intel-gfx] [PATCH 07/21] drm/i915/gtt: Introduce i915_page_dir_dma_addr

2015-06-02 Thread Michel Thierry
On 5/22/2015 6:05 PM, Mika Kuoppala wrote: The legacy mode mm switch and the execlist context assignment needs dma address for the page directories. Introduce a function that encapsulates the scratch_pd dma fallback if no pd is found. Signed-off-by: Mika Kuoppala Reviewed-by: Michel Thierry

Re: [Intel-gfx] [PATCH 08/21] drm/i915/gtt: Introduce struct i915_page_dma

2015-06-02 Thread Michel Thierry
On 5/22/2015 6:05 PM, Mika Kuoppala wrote: All our paging structures have struct page and dma address for that page. Add struct for page/dma address pairs and use it to make the setup and teardown for different paging structures identical. Include the page directory offset also in the struct fo

Re: [Intel-gfx] [PATCH 09/21] drm/i915/gtt: Rename unmap_and_free_px to free_px

2015-06-02 Thread Michel Thierry
On 5/22/2015 6:05 PM, Mika Kuoppala wrote: All the paging structures are now similar and mapped for dma. The unmapping is taken care of by common accessors, so don't overload the reader with such details. Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_gtt.c | 32 ++

Re: [Intel-gfx] [PATCH 10/21] drm/i915/gtt: Remove superfluous free_pd with gen6/7

2015-06-02 Thread Michel Thierry
On 5/22/2015 6:05 PM, Mika Kuoppala wrote: This has slipped in somewhere but it was harmless as we check the page pointer before teardown. Signed-off-by: Mika Kuoppala Right, free_pd is only for gen8+. Reviewed-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.c | 1 - 1 file

Re: [Intel-gfx] [PATCH 11/21] drm/i915/gtt: Introduce fill_page_dma()

2015-06-02 Thread Michel Thierry
On 5/22/2015 6:05 PM, Mika Kuoppala wrote: When we setup page directories and tables, we point the entries to a to the next level scratch structure. Make this generic by introducing a fill_page_dma which maps and flushes. We also need 32 bit variant for legacy gens. v2: Fix flushes and handle va

Re: [Intel-gfx] [PATCH 12/21] drm/i915/gtt: Introduce kmap|kunmap for dma page

2015-06-03 Thread Michel Thierry
On 5/22/2015 6:05 PM, Mika Kuoppala wrote: As there is flushing involved when we have done the cpu write, make functions for mapping for cpu space. Make macros to map any type of paging structure. v2: Make it clear tha flushing kunmap is only for ppgtt (Ville) Cc: Ville Syrjälä Signed-off-by:

Re: [Intel-gfx] [PATCH 13/21] drm/i915/gtt: Use macros to access dma mapped pages

2015-06-03 Thread Michel Thierry
ala Since we're ending up with macros for a lot of things, should we add one for ppgtt->base.dev ? Looks like we could use it in ~20 places. Reviewed-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.c | 37 + drivers/gpu/drm/i915/i91

Re: [Intel-gfx] [PATCH 14/21] drm/i915/gtt: Make scratch page i915_page_dma compatible

2015-06-03 Thread Michel Thierry
On 5/22/2015 6:05 PM, Mika Kuoppala wrote: Lay out scratch page structure in similar manner than other paging structures. This allows us to use the same tools for setup and teardown. Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_gtt.c | 89

Re: [Intel-gfx] [PATCH 15/21] drm/i915/gtt: Fill scratch page

2015-06-03 Thread Michel Thierry
On 5/22/2015 6:05 PM, Mika Kuoppala wrote: During review of dynamic page tables series, I was able to hit a lite restore bug with execlists. I assume that due to incorrect pd, the batch run out of legit address space and into the scratch page area. The ACTHD was increasing due to scratch being al

Re: [Intel-gfx] [PATCH 16/21] drm/i915/gtt: Pin vma during virtual address allocation

2015-06-03 Thread Michel Thierry
t cut as a intermediate solution. Testcase: igt/gem_ctx_thrash Signed-off-by: Mika Kuoppala Reviewed-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c

Re: [Intel-gfx] [PATCH 17/21] drm/i915/gtt: Cleanup page directory encoding

2015-06-03 Thread Michel Thierry
On 5/22/2015 6:05 PM, Mika Kuoppala wrote: Write page directory entry without using superfluous indirect function. Also remove unused device parameter from the encode function. Signed-off-by: Mika Kuoppala Reviewed-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.c | 19

Re: [Intel-gfx] [PATCH 18/21] drm/i915/gtt: Move scratch_pd and scratch_pt into vm area

2015-06-03 Thread Michel Thierry
-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.c | 51 + drivers/gpu/drm/i915/i915_gem_gtt.h | 7 +++-- 2 files changed, 27 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c

Re: [Intel-gfx] [PATCH 19/21] drm/i915/gtt: One instance of scratch page table/directory

2015-06-03 Thread Michel Thierry
in ggtt); I'll still keep only 1 instance. + + return 0; +} + Reviewed-by: Michel Thierry ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 20/21] drm/i915/gtt: Use nonatomic bitmap ops

2015-06-03 Thread Michel Thierry
On 5/22/2015 6:05 PM, Mika Kuoppala wrote: There is no need for atomicity here. Convert all bitmap operations to nonatomic variants. Cc: Ville Syrjälä Signed-off-by: Mika Kuoppala Reviewed-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.c | 12 ++-- 1 file changed, 6

Re: [Intel-gfx] [PATCH 21/21] drm/i915/gtt: Reorder page alloc/free/init functions

2015-06-03 Thread Michel Thierry
. _Introduce_ made me think there was something new in this patch. Signed-off-by: Mika Kuoppala Reviewed-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.c | 54 ++--- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 08/24] drm/i915: Complete page table structures

2014-12-18 Thread Michel Thierry
.daddr/ Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2) --- drivers/gpu/drm/i915/i915_debugfs.c | 2 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 85 + drivers/gpu/drm/i915/i915_gem_gtt.h | 14 +++--- drivers/gpu/drm/i915/intel_lrc.c| 16 +++-

[Intel-gfx] [PATCH 11/24] drm/i915: Extract context switch skip logic

2014-12-18 Thread Michel Thierry
From: Ben Widawsky We have some fanciness coming up. This patch just breaks out the logic. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_context.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 13/24] drm/i915: Initialize all contexts

2014-12-18 Thread Michel Thierry
refore, we also must reinitialize. It was tricky to track this down as we don't have much insight into what happens in a context save. This is required for the next patch which enables dynamic page tables. v2: to->ppgtt is only valid in full ppgtt. Signed-off-by: Ben Widawsky Signed-off-by: Miche

[Intel-gfx] [PATCH 18/24] drm/i915/bdw: Update pdp switch and point unused PDPs to scratch page

2014-12-18 Thread Michel Thierry
The latter point only matters with full PPGTT. The former point only effect platforms with less than 4GB memory. v2: Updated commit message to point that we must set unused PDPs to the scratch page. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2) --- drivers/gpu/drm

[Intel-gfx] [PATCH 20/24] drm/i915: Extract PPGTT param from pagedir alloc

2014-12-18 Thread Michel Thierry
drm_device, which is an unavoidable wart throughout the series. (in other words, not extra flagrant). Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915

[Intel-gfx] [PATCH 23/24] drm/i915/bdw: Dynamic page table allocations

2014-12-18 Thread Michel Thierry
ary memory when we've unmapped things. v2: Update aliasing/true ppgtt allocate/teardown/clear functions for gen 6 & 7. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2) --- drivers/gpu/drm/i915/i915_gem_gtt.c | 378 +--- drivers/gpu/drm/i915/i9

[Intel-gfx] [PATCH 21/24] drm/i915/bdw: Split out mappings

2014-12-18 Thread Michel Thierry
init, which should have no functional change. The PDPEs are still a special case for now. We'll need a function for that in the future as well. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.c | 186 ++-- 1 fi

[Intel-gfx] [PATCH 19/24] drm/i915: num_pd_pages/num_pd_entries isn't useful

2014-12-18 Thread Michel Thierry
From: Ben Widawsky These values are never quite useful for dynamic allocations of the page tables. Getting rid of them will help prevent later confusion. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_debugfs.c | 2 -- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 10/24] drm/i915: Track GEN6 page table usage

2014-12-18 Thread Michel Thierry
dp.pagedir/pdp.pagedirs Make a scratch page allocation helper v3: Rebase and expand commit message. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v3) --- drivers/gpu/drm/i915/i915_gem_gtt.c | 300 ++-- drivers/gpu/drm/i915/i915_gem_g

[Intel-gfx] [PATCH 24/24] drm/i915/bdw: Dynamic page table allocations in lrc mode

2014-12-18 Thread Michel Thierry
been allocated. Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/intel_lrc.c | 80 +++- 1 file changed, 70 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 546884b..6abe4bc 100644 --- a

[Intel-gfx] [PATCH 16/24] drm/i915/bdw: pagedirs rework allocation

2014-12-18 Thread Michel Thierry
From: Ben Widawsky Start using gen8_for_each_pdpe macro to allocate the page directories. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.c | 43 ++--- 1 file changed, 31 insertions(+), 12 deletions(-) diff

[Intel-gfx] [PATCH 07/24] drm/i915: page table abstractions

2014-12-18 Thread Michel Thierry
clean-up/rebase. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2) --- drivers/gpu/drm/i915/i915_gem_gtt.c | 177 ++-- drivers/gpu/drm/i915/i915_gem_gtt.h | 23 - 2 files changed, 107 insertions(+), 93 deletions(-) diff --git a/drivers/gpu/drm

[Intel-gfx] [PATCH 01/24] drm/i915: Add some extra guards in evict_vm

2014-12-18 Thread Michel Thierry
From: Ben Widawsky v2: Use WARN_ONs (Daniel) Cc: Daniel Vetter Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_evict.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 09/24] drm/i915: Create page table allocators

2014-12-18 Thread Michel Thierry
ion, which makes playing around with such things trivial. v2: Updated commit message to explain why this patch exists v3: For lrc, s/pdp.pagedir[i].daddr/pdp.pagedir[i]->daddr/ Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v3) --- drivers/gpu/drm/i915/i915_ge

[Intel-gfx] [PATCH 04/24] drm/i915: Setup less PPGTT on failed pagedir

2014-12-18 Thread Michel Thierry
From: Ben Widawsky The current code will both potentially print a WARN, and setup part of the PPGTT structure. Neither of these harm the current code, it is simply for clarity, and to perhaps prevent later bugs, or weird debug messages. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry

[Intel-gfx] [PATCH 03/24] drm/i915: Rename to GEN8_LEGACY_PDPES

2014-12-18 Thread Michel Thierry
/gpu/drm/i915/*.[ch] Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +++--- drivers/gpu/drm/i915/i915_gem_gtt.h | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/dr

[Intel-gfx] [PATCH 00/24] PPGTT dynamic page allocations

2014-12-18 Thread Michel Thierry
x27;t useful drm/i915: Extract PPGTT param from pagedir alloc drm/i915/bdw: Split out mappings drm/i915/bdw: begin bitmap tracking drm/i915/bdw: Dynamic page table allocations Michel Thierry (1): drm/i915/bdw: Dynamic page table allocations in lrc mode drivers/gpu/drm/i915/i915_debu

[Intel-gfx] [PATCH 02/24] drm/i915/trace: Fix offsets for 64b

2014-12-18 Thread Michel Thierry
From: Ben Widawsky Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_trace.h | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h index 6058a01..f004d3d 100644

[Intel-gfx] [PATCH 22/24] drm/i915/bdw: begin bitmap tracking

2014-12-18 Thread Michel Thierry
From: Ben Widawsky Like with gen6/7, we can enable bitmap tracking with all the preallocations to make sure things actually don't blow up. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.c | 121 +--- driver

[Intel-gfx] [PATCH 17/24] drm/i915/bdw: pagetable allocation rework

2014-12-18 Thread Michel Thierry
From: Ben Widawsky Start using gen8_for_each_pde macro to allocate page tables. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.c | 54 - drivers/gpu/drm/i915/i915_gem_gtt.h | 10 +++ 2 files changed, 39

[Intel-gfx] [PATCH 06/24] drm/i915: Range clearing is PPGTT agnostic

2014-12-18 Thread Michel Thierry
From: Ben Widawsky Therefore we can do it from our general init function. Eventually, I hope to have a lot more commonality like this. It won't arrive yet, but this was a nice easy one. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.

[Intel-gfx] [PATCH 05/24] drm/i915/gen8: Un-hardcode number of page directories

2014-12-18 Thread Michel Thierry
From: Ben Widawsky Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 9d998ec..8f76990 100644

[Intel-gfx] [PATCH 14/24] drm/i915: Finish gen6/7 dynamic page table allocation

2014-12-18 Thread Michel Thierry
s get the trace. v3: Updated trace event to spit out a name v4: Aliasing ppgtt is now initialized differently (in setup global gtt) Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v4) --- drivers/gpu/drm/i915/i915_debugfs.c | 3 +- drivers/gpu/drm/i915/i915_drv.h | 7 ++ driver

[Intel-gfx] [PATCH 15/24] drm/i915/bdw: Use dynamic allocation idioms on free

2014-12-18 Thread Michel Thierry
params v3: Multiple rebases. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2, v3) --- drivers/gpu/drm/i915/i915_gem_gtt.c | 54 +++-- drivers/gpu/drm/i915/i915_gem_gtt.h | 46 +++ 2 files changed, 80 insertions(+), 20 deletion

[Intel-gfx] [PATCH 12/24] drm/i915: Track page table reload need

2014-12-18 Thread Michel Thierry
he current context has mappings change, we need a context reload to switch v2: Rebased after ppgtt clean up patches. Split the warning for aliasing and true ppgtt options. And do not break aliasing ppgtt, where to->ppgtt is always null. Signed-off-by: Michel Thierry (v2) --- driver

Re: [Intel-gfx] [PATCH 00/24] PPGTT dynamic page allocations

2014-12-19 Thread Michel Thierry
: On Thu, Dec 18, 2014 at 05:09:57PM +, Michel Thierry wrote: This new version tries to remove as many unnecessary changes as possible from the previous RFC. For GEN8, it has also been extended to work in logical ring submission (lrc) mode, as it will be the preferred mode of operation. I

[Intel-gfx] [PATCH v2 03/24] drm/i915: Rename to GEN8_LEGACY_PDPES

2014-12-23 Thread Michel Thierry
l 4 Entry v2: Expanded information about Page Directory/Table nomenclature. Cc: Daniel Vetter CC: Dave Gordon Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2) --- drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +++--- drivers/gpu/drm/i915/i915_gem_gtt.h | 6 +++--- 2 files changed, 6

[Intel-gfx] [PATCH v2 02/24] drm/i915/trace: Fix offsets for 64b

2014-12-23 Thread Michel Thierry
From: Ben Widawsky Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_trace.h | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h index 6058a01..f004d3d 100644

[Intel-gfx] [PATCH v2 00/24] PPGTT dynamic page allocations

2014-12-23 Thread Michel Thierry
alloc drm/i915/bdw: Split out mappings drm/i915/bdw: begin bitmap tracking drm/i915/bdw: Dynamic page table allocations Michel Thierry (1): drm/i915/bdw: Dynamic page table allocations in lrc mode drivers/gpu/drm/i915/i915_debugfs.c|7 +- drivers/gpu/drm/i915/i915_

[Intel-gfx] [PATCH v2 04/24] drm/i915: Setup less PPGTT on failed pagedir

2014-12-23 Thread Michel Thierry
From: Ben Widawsky The current code will both potentially print a WARN, and setup part of the PPGTT structure. Neither of these harm the current code, it is simply for clarity, and to perhaps prevent later bugs, or weird debug messages. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry

[Intel-gfx] [PATCH v2 07/24] drm/i915: page table abstractions

2014-12-23 Thread Michel Thierry
clean-up/rebase. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2) --- drivers/gpu/drm/i915/i915_gem_gtt.c | 177 ++-- drivers/gpu/drm/i915/i915_gem_gtt.h | 23 - 2 files changed, 107 insertions(+), 93 deletions(-) diff --git a/drivers/gpu/drm

[Intel-gfx] [PATCH v2 06/24] drm/i915: Range clearing is PPGTT agnostic

2014-12-23 Thread Michel Thierry
From: Ben Widawsky Therefore we can do it from our general init function. Eventually, I hope to have a lot more commonality like this. It won't arrive yet, but this was a nice easy one. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.

[Intel-gfx] [PATCH v2 09/24] drm/i915: Create page table allocators

2014-12-23 Thread Michel Thierry
ion, which makes playing around with such things trivial. v2: Updated commit message to explain why this patch exists v3: For lrc, s/pdp.pagedir[i].daddr/pdp.pagedir[i]->daddr/ Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v3) --- drivers/gpu/drm/i915/i915_ge

[Intel-gfx] [PATCH v2 14/24] drm/i915: Finish gen6/7 dynamic page table allocation

2014-12-23 Thread Michel Thierry
onths ago (Daniel). Cc: Daniel Vetter Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v4+) --- drivers/gpu/drm/i915/i915_debugfs.c | 3 +- drivers/gpu/drm/i915/i915_gem.c | 2 + drivers/gpu/drm/i915/i915_gem_gtt.c | 128 drivers/gpu/drm

[Intel-gfx] [PATCH v2 08/24] drm/i915: Complete page table structures

2014-12-23 Thread Michel Thierry
.daddr/ Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2) --- drivers/gpu/drm/i915/i915_debugfs.c | 2 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 85 + drivers/gpu/drm/i915/i915_gem_gtt.h | 14 +++--- drivers/gpu/drm/i915/intel_lrc.c| 16 +++-

[Intel-gfx] [PATCH v2 13/24] drm/i915: Initialize all contexts

2014-12-23 Thread Michel Thierry
refore, we also must reinitialize. It was tricky to track this down as we don't have much insight into what happens in a context save. This is required for the next patch which enables dynamic page tables. v2: to->ppgtt is only valid in full ppgtt. Signed-off-by: Ben Widawsky Signed-off-by: Miche

[Intel-gfx] [PATCH v2 11/24] drm/i915: Extract context switch skip and pd load logic

2014-12-23 Thread Michel Thierry
From: Ben Widawsky We have some fanciness coming up. This patch just breaks out the logic of context switch skip, pd load pre, and pd load post. v2: Use new functions to replace the logic right away (Daniel) Cc: Daniel Vetter Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2

[Intel-gfx] [PATCH v2 21/24] drm/i915/bdw: Split out mappings

2014-12-23 Thread Michel Thierry
init, which should have no functional change. The PDPEs are still a special case for now. We'll need a function for that in the future as well. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.c | 186 ++-- 1 fi

[Intel-gfx] [PATCH v2 22/24] drm/i915/bdw: begin bitmap tracking

2014-12-23 Thread Michel Thierry
From: Ben Widawsky Like with gen6/7, we can enable bitmap tracking with all the preallocations to make sure things actually don't blow up. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.c | 121 +--- driver

[Intel-gfx] [PATCH v2 23/24] drm/i915/bdw: Dynamic page table allocations

2014-12-23 Thread Michel Thierry
ary memory when we've unmapped things. v2: Update aliasing/true ppgtt allocate/teardown/clear functions for gen 6 & 7. v3: Rebase. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2+) --- drivers/gpu/drm/i915/i915_gem_gtt.c | 377 +-

[Intel-gfx] [PATCH v2 16/24] drm/i915/bdw: pagedirs rework allocation

2014-12-23 Thread Michel Thierry
From: Ben Widawsky Start using gen8_for_each_pdpe macro to allocate the page directories. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.c | 43 ++--- 1 file changed, 31 insertions(+), 12 deletions(-) diff

[Intel-gfx] [PATCH v2 18/24] drm/i915/bdw: Update pdp switch and point unused PDPs to scratch page

2014-12-23 Thread Michel Thierry
The latter point only matters with full PPGTT. The former point only effect platforms with less than 4GB memory. v2: Updated commit message to point that we must set unused PDPs to the scratch page. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2) --- drivers/gpu/drm

[Intel-gfx] [PATCH v2 24/24] drm/i915/bdw: Dynamic page table allocations in lrc mode

2014-12-23 Thread Michel Thierry
been allocated. Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/intel_lrc.c | 80 +++- 1 file changed, 70 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 546884b..6abe4bc 100644 --- a

[Intel-gfx] [PATCH v2 19/24] drm/i915: num_pd_pages/num_pd_entries isn't useful

2014-12-23 Thread Michel Thierry
From: Ben Widawsky These values are never quite useful for dynamic allocations of the page tables. Getting rid of them will help prevent later confusion. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_debugfs.c | 2 -- drivers/gpu/drm/i915

[Intel-gfx] [PATCH v2 20/24] drm/i915: Extract PPGTT param from pagedir alloc

2014-12-23 Thread Michel Thierry
drm_device, which is an unavoidable wart throughout the series. (in other words, not extra flagrant). Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915

[Intel-gfx] [PATCH v2 01/24] drm/i915: Add some extra guards in evict_vm

2014-12-23 Thread Michel Thierry
From: Ben Widawsky v2: Use WARN_ONs (Daniel) Cc: Daniel Vetter Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_evict.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH v2 15/24] drm/i915/bdw: Use dynamic allocation idioms on free

2014-12-23 Thread Michel Thierry
params v3: Multiple rebases. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2, v3) --- drivers/gpu/drm/i915/i915_gem_gtt.c | 54 +++-- drivers/gpu/drm/i915/i915_gem_gtt.h | 46 +++ 2 files changed, 80 insertions(+), 20 deletion

[Intel-gfx] [PATCH v2 05/24] drm/i915/gen8: Un-hardcode number of page directories

2014-12-23 Thread Michel Thierry
From: Ben Widawsky Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 9d998ec..8f76990 100644

[Intel-gfx] [PATCH v2 12/24] drm/i915: Track page table reload need

2014-12-23 Thread Michel Thierry
he current context has mappings change, we need a context reload to switch v2: Rebased after ppgtt clean up patches. Split the warning for aliasing and true ppgtt options. And do not break aliasing ppgtt, where to->ppgtt is always null. v3: Invalidate PPGTT TLBs inside alloc_va_range and teardow

[Intel-gfx] [PATCH v2 10/24] drm/i915: Track GEN6 page table usage

2014-12-23 Thread Michel Thierry
dp.pagedir/pdp.pagedirs Make a scratch page allocation helper v3: Rebase and expand commit message. v4: Allocate required pagetables only when it is needed, _bind_to_vm instead of bind_vma (Daniel). Cc: Daniel Vetter Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v3+) --- drivers/gp

[Intel-gfx] [PATCH v2 17/24] drm/i915/bdw: pagetable allocation rework

2014-12-23 Thread Michel Thierry
From: Ben Widawsky Start using gen8_for_each_pde macro to allocate page tables. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.c | 54 - drivers/gpu/drm/i915/i915_gem_gtt.h | 10 +++ 2 files changed, 39

[Intel-gfx] [PATCH v3 09/25] drm/i915: Plumb drm_device through page tables operations

2015-01-13 Thread Michel Thierry
The next patch in the series will require it for alloc_pt_single. Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.c | 29 - 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH v3 12/25] drm/i915: Track page table reload need

2015-01-13 Thread Michel Thierry
_range and teardown_va_range. v4: Rename ppgtt_invalidate_tlbs to mark_tlbs_dirty and move pd_dirty_rings from i915_address_space to i915_hw_ppgtt. Signed-off-by: Michel Thierry (v2+) --- drivers/gpu/drm/i915/i915_gem_context.c| 27 ++- drivers/gpu/drm/i915/i915_gem_execbuffer

[Intel-gfx] [PATCH v3 19/25] drm/i915/bdw: Update pdp switch and point unused PDPs to scratch page

2015-01-13 Thread Michel Thierry
The latter point only matters with full PPGTT. The former point only effect platforms with less than 4GB memory. v2: Updated commit message to point that we must set unused PDPs to the scratch page. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2) --- drivers/gpu/drm

[Intel-gfx] [PATCH v3 17/25] drm/i915/bdw: page directories rework allocation

2015-01-13 Thread Michel Thierry
From: Ben Widawsky Start using gen8_for_each_pdpe macro to allocate the page directories. v2: Rebased after s/free_pt_*/unmap_and_free_pt/ change. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2) --- drivers/gpu/drm/i915/i915_gem_gtt.c | 43

[Intel-gfx] [PATCH v3 01/25] drm/i915/trace: Fix offsets for 64b

2015-01-13 Thread Michel Thierry
From: Ben Widawsky Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_trace.h | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h index 6058a01..f004d3d 100644

[Intel-gfx] [PATCH v3 07/25] drm/i915: Complete page table structures

2015-01-13 Thread Michel Thierry
tory[i].daddr/ v3: Rebase. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2, v3) --- drivers/gpu/drm/i915/i915_debugfs.c | 2 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 85 + drivers/gpu/drm/i915/i915_gem_gtt.h | 14 +++--- drivers/gpu/dr

[Intel-gfx] [PATCH v3 23/25] drm/i915/bdw: begin bitmap tracking

2015-01-13 Thread Michel Thierry
From: Ben Widawsky Like with gen6/7, we can enable bitmap tracking with all the preallocations to make sure things actually don't blow up. v2: Rebased to match changes from previous patches. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2) --- drivers/gpu/drm

[Intel-gfx] [PATCH v3 11/25] drm/i915: Extract context switch skip and pd load logic

2015-01-13 Thread Michel Thierry
From: Ben Widawsky We have some fanciness coming up. This patch just breaks out the logic of context switch skip, pd load pre, and pd load post. v2: Use new functions to replace the logic right away (Daniel) Cc: Daniel Vetter Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2

[Intel-gfx] [PATCH v3 05/25] drm/i915: Range clearing is PPGTT agnostic

2015-01-13 Thread Michel Thierry
From: Ben Widawsky Therefore we can do it from our general init function. Eventually, I hope to have a lot more commonality like this. It won't arrive yet, but this was a nice easy one. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.

[Intel-gfx] [PATCH v3 24/25] drm/i915/bdw: Dynamic page table allocations

2015-01-13 Thread Michel Thierry
. v4: Remove BUG() from ppgtt_unbind_vma, but keep checking that either teardown_va_range or clear_range functions exist (Daniel). Cc: Daniel Vetter Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2+) --- drivers/gpu/drm/i915/i915_gem_gtt.c | 375 +-

[Intel-gfx] [PATCH v3 20/25] drm/i915: num_pd_pages/num_pd_entries isn't useful

2015-01-13 Thread Michel Thierry
From: Ben Widawsky These values are never quite useful for dynamic allocations of the page tables. Getting rid of them will help prevent later confusion. v2: Updated to use unmap_and_free_pd functions. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2) --- drivers/gpu/drm/i915

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