On 7/1/2015 3:26 PM, Daniel Vetter wrote:
On Wed, Jul 01, 2015 at 03:05:44PM +0100, Michel Thierry wrote:
On 6/30/2015 4:16 PM, Mika Kuoppala wrote:
Previously we have pointed the page where the individual ppgtt
scratch structures refer to, to be the instance which GGTT setup have
allocated
LRC submission
mode (execlists) and it can be detected by i915.enable_ppgtt=3.
Also note that this expanded address space is only available for full PPGTT,
aliasing PPGTT and Global GTT remain 32-bit.
Michel Thierry (17):
drm/i915: Remove unnecessary gen8_clamp_pd
drm/i915/gen8: Make pdp allocation
added macros to initialize the pdps.
v4: Rebase after final merged version of Mika's ppgtt/scratch patches.
Suggested-by: Akash Goel
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 41 +++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 1
: Ben Widawsky
Signed-off-by: Michel Thierry (v3+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 9 -
drivers/gpu/drm/i915/i915_trace.h | 16
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_
cleanup / scratch merge patch series.
v6: Rebase after final merged version of Mika's ppgtt/scratch patches.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 136 +++-
1 file changed, 88 insertions
register.
v5: Rebase after Mika's ppgtt cleanup / scratch merge patch series.
PDP update in bb_start is only for legacy 32b mode.
v6: Rebase after final merged version of Mika's ppgtt/scratch patches.
Cc: Akash Goel
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2+)
---
drive
Signed-off-by: Michel Thierry (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index bd31cbc..67d02b9 100644
--- a/drivers/gpu/drm/i915/i915_gem_g
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/i915_gpu_error.c | 17 +
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915
In a 48b world, users can try to allocate buffers bigger than 4GB; in
these cases it is important that size is a 64b variable.
Also added a warning for illegal bind with size = 0.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem.c | 5 +++--
drivers/gpu/drm/i915
v2: Clean up patch after rebases.
v3: gen8_dump_ppgtt for 32b and 48b PPGTT.
v4: Use used_pml4es/pdpes (Akash).
v5: Rebase after Mika's ppgtt cleanup / scratch merge patch series.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2+)
---
drivers/gpu/drm/i915/i915_debugfs.c
eries.
Suggested-by: Akash Goel
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 11 ---
2 files changed, 1 insertion(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_
h).
v3: Just kill the limit, it was only there for early detection of an
error when used for execbuffer (Chris).
Cc: Akash Goel
Cc: Chris Wilson
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_userptr.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/dr
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Michel Thierry
---
configure.ac | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure.ac b/configure.ac
index 001fd3d..12b8465 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,7 +20,7 @@
AC_PREREQ([2.63])
AC_INIT
Cc: John Harrison
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d245c82..c720a18 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/d
Use 48b addresses if hw supports it (i915.enable_ppgtt=3).
Note, aliasing PPGTT remains 32b only.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
drivers/gpu/drm/i915/i915_params.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers
PIN_HIGH; update PIN_OFFSET_MASK
to use last PIN_ defined instead of hard-coded value; use correct limit
check in eb_vma_misplaced. (Chris)
Cc: Chris Wilson
Cc: Ben Widawsky
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h| 4 +++-
drivers/gpu/drm/i915/i915_gem.c
calls to drm_intel_bo_emit_reloc will clear it.
v2: Make set/clear functions nops on pre-gen8 platforms, and use them
internally in emit_reloc functions (Ben)
s/48BADDRESS/48B_ADDRESS/ (Dave)
Cc: Ben Widawsky
Cc: Dave Gordon
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Michel Thierry
page table
level and here is no exception.
v2: Rebase after Mika's ppgtt cleanup / scratch merge patch series.
v3: Rebase after final merged version of Mika's ppgtt/scratch patches.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2)
---
drivers/gpu/drm/i915
ka's ppgtt/scratch patches.
Cc: Akash Goel
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 162 ++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 12 ++-
2 files changed, 146 insertions(+), 28 deletions(-)
diff
mber of pages
parameter in insert_pte_entries.
Cc: Akash Goel
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 51 -
drivers/gpu/drm/i915/i915_gem_gtt.h | 11
2 files changed, 50 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2+)
---
drivers/gpu/drm/i915/i915_drv.h | 7 ++-
drivers/gpu/drm/i915/i915_gem_gtt.c | 116
drivers/gpu/drm/i915/i915_gem_gtt.h | 41 ++---
3 files changed, 128 insertions(+), 36 deleti
: s/48baddress/48b_address/,
Only use in OUT_RELOC64 cases, OUT_RELOC implies a 32-bit address offset
is needed (Ben)
Cc: Ben Widawsky
Cc: mesa-...@lists.freedesktop.org
Signed-off-by: Michel Thierry
---
configure.ac | 2 +-
src/mesa/drivers/dri/i965
On 7/1/2015 4:43 PM, Chris Wilson wrote:
On Wed, Jul 01, 2015 at 04:27:32PM +0100, Michel Thierry wrote:
+ flags |= PIN_ZONE_4G;
+ if (entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS)
+ flags &= ~PIN_ZONE_4G;
+
if (!drm_mm_node_allocated
PIN_HIGH; update PIN_OFFSET_MASK
to use last PIN_ defined instead of hard-coded value; use correct limit
check in eb_vma_misplaced. (Chris)
v5: Don't touch PIN_OFFSET_MASK and update workaround comment (Chris)
Cc: Chris Wilson
Reviewed-by: Chris Wilson (v4)
Signed-off-by: Michel Th
On 7/1/2015 6:06 PM, Emil Velikov wrote:
Hi Michel,
Although I cannot comment on the exact implementation I can give you
general some tips which you might find useful.
Hi Emil,
On 1 July 2015 at 16:28, Michel Thierry wrote:
Gen8+ supports 48-bit virtual addresses, but some objects must
On 7/2/2015 8:21 AM, Chris Wilson wrote:
On Wed, Jul 01, 2015 at 04:28:10PM +0100, Michel Thierry wrote:
Gen8+ supports 48-bit virtual addresses, but some objects must always be
allocated inside the 32-bit address range.
OUT_BATCH(0);
OUT_BATCH(mocs_wb << 16);
/* Surface
On 7/7/2015 9:33 AM, Chris Wilson wrote:
On Sat, Apr 11, 2015 at 09:41:37AM +0100, Chris Wilson wrote:
Bug reports are still coming in for late 4.0-rcX that indicate that
execlists causes GPU hangs following resume.
Fixes regression from
commit d7f621e50704306c348ccb192f17047f1499f9bc
Author: O
On 7/7/2015 1:36 PM, Goel, Akash wrote:
On 7/1/2015 8:57 PM, Michel Thierry wrote:
This transitional patch doesn't do much for the existing code. However,
it should make upcoming patches to use the full 48b address space a bit
easier. The patch also introduces the PML4, ie. the new top
On 7/7/2015 1:48 PM, Goel, Akash wrote:
On 7/1/2015 8:57 PM, Michel Thierry wrote:
@@ -1087,8 +1137,62 @@ static int gen8_alloc_va_range_4lvl(struct
i915_address_space *vm,
uint64_t start,
uint64_t length)
{
-WARN_ON(1); /* to be implemented
On 7/7/2015 1:51 PM, Goel, Akash wrote:
On 7/1/2015 8:57 PM, Michel Thierry wrote:
static void
@@ -781,9 +793,9 @@ gen8_ppgtt_insert_pte_entries(struct
i915_address_space *vm,
struct i915_hw_ppgtt *ppgtt =
container_of(vm, struct i915_hw_ppgtt, base);
gen8_pte_t
On 7/7/2015 1:43 PM, Goel, Akash wrote:
On 7/1/2015 8:57 PM, Michel Thierry wrote:
@@ -795,13 +821,15 @@ static void gen8_ppgtt_cleanup(struct
i915_address_space *vm)
*
* Return: 0 if success; negative error code otherwise.
*/
-static int gen8_ppgtt_alloc_pagetabs(struct
On 7/7/2015 1:53 PM, Goel, Akash wrote:
On 7/1/2015 8:57 PM, Michel Thierry wrote:
@@ -476,13 +477,13 @@ int i915_error_state_to_str(struct
drm_i915_error_state_buf *m,
if ((obj = error->ring[i].ctx)) {
err_printf(m, "%s --- HW Context =
On 7/7/2015 1:56 PM, Goel, Akash wrote:
On 7/1/2015 8:57 PM, Michel Thierry wrote:
v2: Clean up patch after rebases.
v3: gen8_dump_ppgtt for 32b and 48b PPGTT.
v4: Use used_pml4es/pdpes (Akash).
v5: Rebase after Mika's ppgtt cleanup / scratch merge patch series.
Signed-off-by: Ben Wid
cleanup / scratch merge patch series.
v6: Rebase after final merged version of Mika's ppgtt/scratch patches.
v7: Keep pagetable map in-line (and avoid unnecessary for_each_pde
loops), remove redundant ppgtt pointer in _alloc_pagetabs (Akash)
Cc: Akash Goel
Signed-off-by: Ben Widawsky
In a 48b world, users can try to allocate buffers bigger than 4GB; in
these cases it is important that size is a 64b variable.
Also added a warning for illegal bind with size = 0.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem.c | 5 +++--
drivers/gpu/drm/i915
Introduces the Page Map Level 4 (PML4), ie. the new top level structure
of the page tables.
To facilitate testing, 48b mode will be available on Broadwell and
GEN9+, when i915.enable_ppgtt = 3.
Cc: Akash Goel
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 7
Signed-off-by: Michel Thierry (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 7a1d6f8..030f688 100644
--- a/drivers/gpu/drm/i915/i915_gem_g
ka's ppgtt/scratch
patches.
v12: Fix pdpe start value in trace (Akash)
Cc: Akash Goel
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 161 ++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 12 ++-
2 fil
page table
level and here is no exception.
v2: Rebase after Mika's ppgtt cleanup / scratch merge patch series.
v3: Rebase after final merged version of Mika's ppgtt/scratch patches.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2)
---
drivers/gpu/drm/i915
ff-by: Michel Thierry (v2+)
---
drivers/gpu/drm/i915/i915_debugfs.c | 18
drivers/gpu/drm/i915/i915_gem_gtt.c | 83 +
2 files changed, 93 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debu
register.
v5: Rebase after Mika's ppgtt cleanup / scratch merge patch series.
PDP update in bb_start is only for legacy 32b mode.
v6: Rebase after final merged version of Mika's ppgtt/scratch
patches.
Cc: Akash Goel
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2+)
---
drive
v2: For semaphore errors, object is mapped to GGTT and offset will not
be > 4GB, print only lower 32-bits (Akash)
Cc: Akash Goel
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/i915_gpu_error.c |
eries.
Suggested-by: Akash Goel
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 11 ---
2 files changed, 1 insertion(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_
mber of pages
parameter in insert_pte_entries.
v8: Change gen8_ppgtt_clear_pte_range to stop at PDP boundary, instead of
adding and extra clamp function; remove unnecessary pdp_start/pdp_len
variables (Akash).
Cc: Akash Goel
Signed-off-by: Michel Thierry
---
drivers/gpu/dr
ated to v3).
Suggested-by: Akash Goel
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 41 +++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
2 files changed, 40 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/d
eclists) and it can be detected by i915.enable_ppgtt=3.
Also note that this expanded address space is only available for full PPGTT,
aliasing PPGTT and Global GTT remain 32-bit.
Michel Thierry (18):
drm/i915: Remove unnecessary gen8_clamp_pd
drm/i915/gen8: Make pdp allocation more dynamic
Cc: John Harrison
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 91e195a..4a30a73 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/d
h).
v3: Just kill the limit, it was only there for early detection of an
error when used for execbuffer (Chris).
Cc: Akash Goel
Reviewed-by: Chris Wilson
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_userptr.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/g
after gen8_map_pagetable_range removal.
v7: Use generic page name (px) in DECLARE_EVENT_CLASS (Akash)
Cc: Akash Goel
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v3+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 6 ++
drivers/gpu/drm/i915/i915_trace.h
PIN_HIGH; update PIN_OFFSET_MASK
to use last PIN_ defined instead of hard-coded value; use correct limit
check in eb_vma_misplaced. (Chris)
v5: Don't touch PIN_OFFSET_MASK and update workaround comment (Chris)
Cc: Chris Wilson
Reviewed-by: Chris Wilson (v4)
Signed-off-by: Michel Th
Use 48b addresses if hw supports it (i915.enable_ppgtt=3).
Note, aliasing PPGTT remains 32b only.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
drivers/gpu/drm/i915/i915_params.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers
awsky
Signed-off-by: Michel Thierry (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 82 ++---
drivers/gpu/drm/i915/i915_gem_gtt.h | 10 +++--
2 files changed, 74 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/
On 7/7/2015 4:27 PM, Chris Wilson wrote:
On Tue, Jul 07, 2015 at 04:14:59PM +0100, Michel Thierry wrote:
In a 48b world, users can try to allocate buffers bigger than 4GB; in
these cases it is important that size is a 64b variable.
Also added a warning for illegal bind with size = 0.
Signed
On 7/7/2015 9:08 PM, Chris Wilson wrote:
On Tue, Jul 07, 2015 at 04:44:30PM +0100, Michel Thierry wrote:
On 7/7/2015 4:27 PM, Chris Wilson wrote:
On Tue, Jul 07, 2015 at 04:14:59PM +0100, Michel Thierry wrote:
In a 48b world, users can try to allocate buffers bigger than 4GB; in
these cases
On 7/8/2015 4:22 PM, Daniel Vetter wrote:
On Wed, Jul 08, 2015 at 12:22:58PM +0100, Michel Thierry wrote:
On 7/7/2015 9:08 PM, Chris Wilson wrote:
On Tue, Jul 07, 2015 at 04:44:30PM +0100, Michel Thierry wrote:
On 7/7/2015 4:27 PM, Chris Wilson wrote:
On Tue, Jul 07, 2015 at 04:14:59PM +0100
On 8/18/2015 10:56 PM, Mika Kuoppala wrote:
commit e1f123257a1f7d3af36a31a0fb2d4c6f40039fed
Author: Michel Thierry
Date: Wed Jul 29 17:23:56 2015 +0100
drm/i915: Expand error state's address width to 64b
changed the batch buffer address to be 64b. Fix the parsing
of gtt o
: Mika Kuoppala
Cc: Michel Thierry
Signed-off-by: Michał Winiarski
Unless Chris thinks otherwise, I see Michał already addressed his comments.
Reviewed-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 45 +
1 file changed, 16 insertions(+
Signed-off-by: Michel Thierry
---
intel/intel-symbol-check | 1 +
1 file changed, 1 insertion(+)
diff --git a/intel/intel-symbol-check b/intel/intel-symbol-check
index c555e6d..64ec4ed 100755
--- a/intel/intel-symbol-check
+++ b/intel/intel-symbol-check
@@ -39,6 +39,7 @@ drm_intel_bo_subdata
these patches to comply with the i915 merge process.
Once the kernel patch is merged, I'll make a new libdrm release and address
the mesa build dependency.
[1] http://lists.freedesktop.org/archives/dri-devel/2015-August/087837.html
Michel Thierry (2):
intel: 48b ppg
http://lists.freedesktop.org/archives/intel-gfx/2015-July/072612.html
Cc: Ben Widawsky
Cc: Michał Winiarski
Signed-off-by: Michel Thierry
---
include/drm/i915_drm.h| 3 +-
intel/intel_bufmgr.c | 11 ++
intel/intel_bufmgr.h | 1 +
intel/intel_bufmgr_gem.c
Also check for correct revision id in each Gen9 platform (SKL until B0
and BXT until A0).
Cc: Nick Hoath
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_lrc.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu
olo Spurio
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_lrc.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index d8b605f..c3fca4b 100644
--- a/drivers/gpu/drm/i915/i
sure that we're using the right upper limit, select it based on
the ppgtt mode.
Cc: Michel Thierry
Signed-off-by: Daniele Ceraolo Spurio
Yes, we need this, specially when we use top-down allocation.
(you could use %'lld to add thousand separators into these long long
outputs).
R
x27;s true, although I was under the impression that the render state
batch was executed in the ggtt.
Always mark newly created ppgtts dirty to ensure that pdps are
pushed before first bb.
Cc: Michel Thierry
Cc: Arun Siluvery
Cc: Chris Wilson
Cc: Imre Deak
Signed-off-by: Mika Kuoppala
---
drive
: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 352ccd5..3e00f72 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1869,6 +1869,7
On 9/9/2015 11:33 AM, Chris Wilson wrote:
On Wed, Sep 09, 2015 at 11:29:52AM +0100, Michel Thierry wrote:
i915_gem_object_bind_to_vm returns -E2BIG when the user tries to bind an
object larger than the aperture, but i915_gem_fault does not handle this
return code:
[501906.530985] gem_mmap_gtt
On 9/15/2015 2:30 PM, Michał Winiarski wrote:
According to bspec, some parts of HW expect the addresses to be in
a canonical form where bits [63:48] == [47]. Lets satisfy the HW by
converting the address prior to allocating/clearing the entries in page
tables.
Thanks for sending this. A couple
On 9/15/2015 2:30 PM, Michał Winiarski wrote:
It will be initialized just moments later by i915_init_vm. Global and
aliasing tables are going through different path anyways.
Cc: Michel Thierry
Cc: Mika Kuoppala
Signed-off-by: Michał Winiarski
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2
e the read
pointer should be set to 0.
Signed-off-by: Lei Shen
Signed-off-by: Deepak S
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_lrc.c | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gp
On 9/25/2015 4:44 PM, Mika Kuoppala wrote:
Michel Thierry writes:
- ring->next_context_status_buffer = 0;
+
+ /*
+* Instead of resetting the Context Status Buffer (CSB) read pointer to
+* zero, we need to read the write pointer from hardware and use
EN8_CSB_ENTRIES (6) and GEN8_CSB_PTR_MASK
(0x07).
Cc: Mika Kuoppala
Signed-off-by: Lei Shen
Signed-off-by: Deepak S
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_lrc.c | 39 ---
drivers/gpu/drm/i915/intel_lrc.h | 2 ++
2 files changed, 34 i
EN8_CSB_ENTRIES (6) and GEN8_CSB_PTR_MASK
(0x07).
v3: Rebased on top of "Parametrize LRC registers" patch.
Cc: Mika Kuoppala
Signed-off-by: Lei Shen
Signed-off-by: Deepak S
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_lrc.c | 39
EN8_CSB_ENTRIES (6) and GEN8_CSB_PTR_MASK
(0x07).
Cc: Mika Kuoppala
Signed-off-by: Lei Shen
Signed-off-by: Deepak S
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_lrc.c | 39 ---
drivers/gpu/drm/i915/intel_lrc.h | 2 ++
2 files changed, 34 i
Goel
Cc: Chris Wilson
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 7 ++-
drivers/gpu/drm/i915/i915_params.c | 2 +-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index
http://lists.freedesktop.org/archives/intel-gfx/2015-September/075836.html
Michel Thierry (2):
drm/i915: Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset
drm/i915/gen8: Flip the 48b switch
drivers/gpu/drm/i915/i915_drv.h| 2 ++
drivers/gpu/drm/i915/i915_gem.c
ommit message updated to point to libdrm patch.
Cc: Chris Wilson
Cc: Akash Goel
Reviewed-by: Chris Wilson (v4)
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h| 2 ++
drivers/gpu/drm/i915/i915_gem.c| 25 +++--
drivers/gpu/drm
ommit message updated to point to libdrm patch.
v9: vmas are allocated in the correct ozone, so only check flag when the
vma has not been allocated. (Chris)
Cc: Chris Wilson
Reviewed-by: Chris Wilson (v4)
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h| 2 ++
driver
On 10/1/2015 2:16 PM, Daniel Vetter wrote:
On Wed, Sep 30, 2015 at 03:36:19PM +0100, Michel Thierry wrote:
Use 48b addresses if hw supports it (i915.enable_ppgtt=3).
Update the sanitize_enable_ppgtt for 48 bit PPGTT mode.
Note, aliasing PPGTT remains 32b only.
v2: s/full_64b/full_48b/. (Akash
eaking the for
loop immediately.
This has been already verified with "static analysis tools".
[1]http://lists.freedesktop.org/archives/intel-gfx/2015-June/068548.html
Cc: Paulo Zanoni
Cc: Chris Wilson
Cc: Dave Gordon
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gt
On 10/1/2015 5:09 PM, Chris Wilson wrote:
On Thu, Oct 01, 2015 at 04:59:35PM +0100, Michel Thierry wrote:
---
drivers/gpu/drm/i915/i915_gem_gtt.h | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915
On 10/2/2015 1:58 PM, Chris Wilson wrote:
On Fri, Oct 02, 2015 at 01:47:03PM +0100, Michel Thierry wrote:
On 10/1/2015 5:09 PM, Chris Wilson wrote:
On Thu, Oct 01, 2015 at 04:59:35PM +0100, Michel Thierry wrote:
---
drivers/gpu/drm/i915/i915_gem_gtt.h | 14 ++
1 file changed
eaking the for
loop immediately.
This has been already verified with "static analysis tools".
[1]http://lists.freedesktop.org/archives/intel-gfx/2015-June/068548.html
v2: Make it a single statement, while preventing the common subexpression
elimination (Chris)
Cc: Paulo Zanoni
Cc: Chr
so seen in bug 87729 - igt/gem_close_race)
Cc: Daniel Vetter
Cc: Chris Wilson
Cc: Rafael Barbalho
Cc: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gpu/drm/i915/i915_gem.c | 20
drivers/gpu/drm/i915/i915_gem_cont
On 10/5/2015 5:36 PM, Dave Gordon wrote:
On 02/10/15 14:16, Michel Thierry wrote:
We tried to fix this in commit fdc454c1484a ("drm/i915: Prevent out of
range pt in gen6_for_each_pde").
But the static analyzer still complains that, just before we break due
to "iter < I91
igned-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem.c | 3 ++-
drivers/gpu/drm/i915/intel_lrc.c | 35 ++-
2 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3d5a5a8
On 4/15/2015 5:40 PM, Chris Wilson wrote:
On Wed, Apr 15, 2015 at 05:17:13PM +0100, Michel Thierry wrote:
WaIdleLiteRestore is an execlists-only workaround, and requires the driver
to ensure that any context always has HEAD!=TAIL when attempting lite
restore.
Add two extra MI_NOOP instructions
itted and update
comment (Chris).
Cc: Chris Wilson
Signed-off-by: Thomas Daniel
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem.c | 3 ++-
drivers/gpu/drm/i915/intel_lrc.c | 35 ++-
2 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/dr
On 4/22/2015 12:36 AM, Linus Torvalds wrote:
So I just go the appended NULL pointer de-reference when trying to
look at a video from my GoPro.
The code disassembles to
0: 81 fb 00 04 00 00 cmp$0x400,%ebx
6: 41 89 07 mov%eax,(%r15)
9: 74 78 je
t
now also uses allocate_va_range.
Cc: Daniel Vetter
Cc: Mika Kuoppala
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 7b13273..e8c0a
xt_unqueue().
Reported-by: Dan Carpenter
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index fa129b8..199a154 100644
--- a/drivers/gp
PDPs (48b addressing).
Reported-by: Dan Carpenter
Cc: Dave Gordon
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 6fae6b
On 4/30/2015 3:22 PM, Ville Syrjälä wrote:
On Thu, Apr 30, 2015 at 02:59:34PM +0100, Michel Thierry wrote:
The patch 69876bed7e008f5fe01538a2d47c09f2862129d0: "drm/i915/gen8:
page directories rework allocation" added an overflow warning, but the
mask had an extra 0. Use typo-pr
On 4/30/2015 3:53 PM, Dave Gordon wrote:
On 30/04/15 15:33, Michel Thierry wrote:
On 4/30/2015 3:22 PM, Ville Syrjälä wrote:
On Thu, Apr 30, 2015 at 02:59:34PM +0100, Michel Thierry wrote:
The patch 69876bed7e008f5fe01538a2d47c09f2862129d0: "drm/i915/gen8:
page directories rework alloc
cessary after gen8_alloc_va_range handles more
than 4 PDPs (48b addressing).
v2: Really check for 32b overflow (Ville)
Reported-by: Dan Carpenter
Cc: Dave Gordon
Cc: Ville Syrjälä
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
1 file changed, 2 insertions(+)
l4 for the top level, and the pdp is just one of the entries
being pointed to by a pml4e.
v2: Updated after dynamic page allocation changes.
v3: Rebase after s/page_tables/page_table/.
v4: Rebase after changes in "Dynamic page table allocations" patch.
Signed-off-by: Ben Widawsky
Signe
I'm open to rebase these patches after Mika's, or update his patches
after the 48b ones. Please let me know which option is better.
Michel Thierry (16):
drm/i915: Remove unnecessary gen8_clamp_pd
drm/i915/gen8: Make pdp allocation more dynamic
drm/i915/gen8: Abstract PDP usage
dr
PTEs allows the iterator to stay coherent
through a VMA mapping operation spanning multiple page table levels.
v2: Rebase after s/page_tables/page_table/.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 46 +++
pd/pt (unmap_and_free_pdp).
v3: To facilitate testing, 48b mode will be available on Broadwell and
GEN9+, when i915.enable_ppgtt = 3.
v4: Rebase after s/page_tables/page_table/ and added extra information
about 4-level page table formats.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
_insert_entries (Akash).
v5: Do not mix pages and bytes in insert_entries (Akash).
Cc: Akash Goel
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 51 +++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 11
2 files changed, 54 insertions(
ag is ignored in 32b PPGTT.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/i915_gem.c| 11 +++
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 3 +++
include/uapi/drm/i915_drm.h| 3 ++-
4 files change
701 - 800 of 1163 matches
Mail list logo
