nge-Id: Ie3d093b2542ab0e2a44b90460533e2f979788d6c
Cc: Deepak S
Cc: Mika Kuoppala
Cc: Daniel Vetter
Signed-off-by: Michel Thierry
Signed-off-by: Arun Siluvery
---
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/intel_lrc.c|
Otherwise, new platforms without workarounds will hit this warning for
every new context created.
Cc: Tvrtko Ursulin
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_lrc.c| 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions
We already have it for chv, but was missing for bdw.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 788e1b6..91ddcd1 100644
On 12/4/2014 3:25 PM, Ville Syrjälä wrote:
On Thu, Dec 04, 2014 at 03:07:52PM +, Michel Thierry wrote:
We already have it for chv, but was missing for bdw.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a
We already have it for chv, but was missing for bdw.
v2: Label WaForceEnableNonCoherent (Ville)
Cc: Ville Syrjälä
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers
On 12/5/2014 2:41 PM, Daniel Vetter wrote:
On Thu, Dec 04, 2014 at 05:25:56PM +0200, Ville Syrjälä wrote:
On Thu, Dec 04, 2014 at 03:07:52PM +, Michel Thierry wrote:
We already have it for chv, but was missing for bdw.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915
On 12/5/2014 12:11 PM, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Things like reliable GGTT mappings and mirrored 2d-on-3d display will need
to map objects into the same address space multiple times.
Added a GGTT view concept and linked it with the VMA to distinguish between
multiple instances
after
+ * calling the core API functions).
+ *
+ */
+
const struct i915_ggtt_view i915_ggtt_view_normal;
static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv);
Apart from that,
Reviewed-by: Michel Thierry
smime.p7s
Description:
We already implement this workaround, but it was missing its name.
Reviewed-by: Ville Syrjälä
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915
On 12/10/2014 9:18 AM, Daniel Vetter wrote:
On Tue, Dec 09, 2014 at 01:37:21PM +, Michel Thierry wrote:
On 12/5/2014 2:41 PM, Daniel Vetter wrote:
On Thu, Dec 04, 2014 at 05:25:56PM +0200, Ville Syrjälä wrote:
On Thu, Dec 04, 2014 at 03:07:52PM +, Michel Thierry wrote:
We already
iew in i915_gem_obj_bound to align
usage in i915_gem_object_ggtt_unpin. (Michel Thierry)
* Change to single if statement in i915_gem_obj_to_ggtt. (Michel Thierry)
* Removed stray semi-colon in i915_gem_object_set_cache_level.
For: VIZ-4544
Signed-off-by: Tvrtko Ursulin
Cc: Daniel
On 12/10/2014 5:27 PM, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
A short section describing background, implementation and intended usage.
v2:
* Align section name between template and DOC comment. (Michel Thierry)
For: VIZ-4544
Signed-off-by: Tvrtko Ursulin
Reviewed-by: Michel
When execlists submission is enabled, try full ppgtt by default.
Note, this patch considers that execlist support has been enabled by
default on Gen8.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff
On 12/15/2014 8:30 AM, Daniel Vetter wrote:
On Thu, Dec 11, 2014 at 10:19:39AM +, Michel Thierry wrote:
On 12/10/2014 5:27 PM, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
A short section describing background, implementation and intended usage.
v2:
* Align section name between
On 12/15/2014 10:11 AM, Daniel Vetter wrote:
On Thu, Dec 11, 2014 at 12:07:18PM +, Michel Thierry wrote:
When execlists submission is enabled, try full ppgtt by default.
Note, this patch considers that execlist support has been enabled by
default on Gen8.
Signed-off-by: Michel Thierry
On 12/15/2014 2:28 PM, Daniel Vetter wrote:
On Mon, Dec 15, 2014 at 03:22:08PM +0100, Daniel Vetter wrote:
On Mon, Dec 15, 2014 at 12:47:14PM +, Michel Thierry wrote:
On 12/15/2014 10:11 AM, Daniel Vetter wrote:
On Thu, Dec 11, 2014 at 12:07:18PM +, Michel Thierry wrote:
When
comment (Daniel)
Cc: Daniel Vetter
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 171f6ea..b64323b 100644
--- a/drivers
From: Michel Thierry
The workaround to limit SDE poly depth FIFO to 2 is not applied because
3D Chicken-3 mask bit is not set.
WaLimitSizeOfSDEPolyFifo is only for BDW-A and could be removed.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1
Disable FF DOP clock gating.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 4
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e813033..44e7f34 100644
--- a
These workarounds are mainly for D/E/F steppings.
I didn't squash them, because we can eventually get rid of some of them.
Michel Thierry (8):
drm/i915: Add WaDisableFenceDestinationToSLM:bdw
drm/i915: Add WaProgramL3SqcReg1Default:bdw
drm/i915: Add WaDisableFfDopClockGating:bdw
drm
Coherent L3 cache lines are not getting flushed during context switch
which is causing issues.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 4
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b
L3SQCREG4 LQSC RO PERF DIS must be programmed by software to 1h
(Disable) to work around a Gsync Issue in HDC.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915
Instruction Shootdown in ROW_CHICKEN must be disabled.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915
Workaround requires programing L3 tag clock timing register.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915/intel_pm.c | 9 +
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915
For performance, program the default initial value of L3SqcReg1 on BDW
to 0x784000:
L3SQ High Priority Credit Initialization = 2 (1b).
L3SQ General Priority Credit Initialization = 30 (0b).
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915
Set desired default value for HDCCHICKEN register for BDW platform.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
HDC_CHICKEN0 bit 14 (Fence Destination To SLM Disable) must be
programmed by software to 1h (Disable) to work around a LSLM unit issue.
WaDisableFenceDestinationToSLM is only needed for BDW E,F step.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915
This is a rebase from Ben's patches originally sent on July 1st, working in
latest drm-nightly. Below is Ben's original cover-letter.
==
Here be all the patches to make full PPGTT relatively stable on Broadwell. Most
of the work was actually to the generic PPGTT code, and not BDW specific.
is is more accurate.
Signed-off-by: Ben Widawsky
v3: Make it work again after legacy_hw_ctx & user_handle changes.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_context.c | 79 +
1 file changed, 51 insertions(+), 28 deletions(-)
diff --git
From: Ben Widawsky
The bound list is global (all objects which back the VMAs are stored
here). Recently the BUG() in the offset lookup was demoted to a WARN,
but the fault actually lies in the caller, here.
This bug has existed since the initial introduction of PPGTT (however,
it was fixed in un
From: Ben Widawsky
As what was correctly debugged here:
commit acc240d41ea1ab9c488a79219fb313b5b46265ae
Author: Daniel Vetter
Date: Thu Dec 5 15:42:34 2013 +0100
drm/i915: Fix use-after-free in do_switch
It then becomes apparent that the default context cannot be the context
being switch
From: Ben Widawsky
The simple explanation is, the docs say to do this for GEN8. Perhaps we
want to do this for GEN7 too, I am not certain.
PDPs are saved and restored with context. Contexts (without execlists)
only exist on the render ring. The docs say that PDPs are not power
context save/resto
From: Ben Widawsky
This is just a cosmetic change to try to put do_switch_rcs on a diet. As
it stands, the function was quite complex, and error prone.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_context.c | 32
1 file changed, 20 insertions(+
From: Ben Widawsky
Rename some variables, and clean up the code a bit to make things
clearer in our error capture.
There isn't an intentional functional change here.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gpu_error.c | 55 ---
1 file changed,
From: Ben Widawsky
To follow up on the last patch, we can now capture the VMAs instead of
the BOs. The hope if we get more accurate error capture while debugging
PPGTT.
Note that this does not impact the previous argument about whether to
capture all VMAs, or just the guilty VMA. This merely all
From: Ben Widawsky
Some of the original PPGTT patches in this area where unmerged, and this
left a lot of confusion in our error capture with regard to which vm/obj
we want to capture. There have been at least a couple of patches from
Chris, and myself to try to fix this up; so here is another sh
From: Ben Widawsky
The comment [which was mine] is wrong. The context object can never be
bound in a PPGTT because it is only capable of living in the Global GTT.
So, remove the comment, and reorder the unref. What's nice about the
latter is it keeps the context object alive past the PPGTT. This
From: Ben Widawsky
Broadwell is perfectly capable of full PPGTT. I've been using it for
some time, and seen no especially ill effects.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_d
From: Ben Widawsky
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_gem_evict.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c
b/drivers/gpu/drm/i915/i915_gem_evict.c
index bbf4b12..38297d3 100644
--- a/drivers/gpu/drm/i
From: Ben Widawsky
There are no users of this yet, but the idea is presented and split out
to find bugs.
Also, while here, return -ERESTARTSYS to the caller, in case they want
to do something with it.
Signed-off-by: Ben Widawsky
---
drivers/gpu/drm/i915/i915_drv.h| 2 +-
drivers/
From: Ben Widawsky
If a VM still have objects which are bound (exactly: have a node
reserved in the drm_mm), and we are in the middle of a reset, we have no
hope of the standard methods fixing the situation (ring idle won't
work). We must therefore let the reset handler take it's course, and
then
From: Ben Widawsky
The last patch made PPGTT free cases correct. It left a major problem
though where in many cases it was possible to have to idle the GPU in
order to destroy a VM. This is really unfortunate as it is stalling the
active GPU process for the dying GPU process.
The workqueue grew
After unclaimed register detection was enabled for BDW, I started seeing
warnings while reading registers 0x4400c (DEIER) and 0x4401c (GTIER).
>From Gen8, DEIER has been split per display engine pipe, and GTIER has
been split in 4.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i
the ref, and it can just call the base cleanup and free the
ppgtt.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_gem.c | 8
drivers/gpu/drm/i915/i915_gem_context.c | 23 +++
drivers/gpu/drm/i915
After new vma/ppgtt lifetime rules, the ppgtt can outlive the context
it was created for.
- Renamed create_vm_for_ctx to i915_ppgtt_create as ctx/ppgtt are no
longer referenced.
- Updated per_file_stats to cope with this change.
Cc: Daniel Vetter
Signed-off-by: Michel Thierry
---
drivers/gpu
-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_debugfs.c | 25 -
drivers/gpu/drm/i915/i915_gem_context.c | 5 ++---
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 --
3 files changed, 26 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915
The driver will no longer initialize the aliasing ppgtt if we have
full ppgtt enabled.
gen8_ppgtt_info uses the aliasing ppgtt or the ppgtt from the
default context. This patch makes it clear.
Cc: Daniel Vetter
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_debugfs.c | 6
a Kuoppala
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_lrc.c | 57
1 file changed, 57 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 44ddb4d..0cf2f2c 100644
--- a/drivers/gpu/drm/i915/i
On 5/29/2015 1:53 PM, Michel Thierry wrote:
On 5/29/2015 12:05 PM, Michel Thierry wrote:
On 5/22/2015 6:04 PM, Mika Kuoppala wrote:
With BDW/SKL and 32bit addressing mode only, the hardware preloads
pdps. However the TLB invalidation only has effect on levels below
the pdps. This means that if
and save 8 commands). (Mika)
Cc: Dave Gordon
Cc: Mika Kuoppala
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_lrc.c | 43
1 file changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
ind
cleaner.
v9: Rebase after Mika's ppgtt cleanup / scratch merge patch series, while
trying to reuse as much as possible for pdp alloc. pml4_init/fini
replaced by setup/cleanup_px macros.
Cc: Akash Goel
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2+)
---
drivers/gpu/drm
register.
v5: Rebase after Mika's ppgtt cleanup / scratch merge patch series.
PDP update in bb_start is only for legacy 32b mode.
Cc: Akash Goel
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 54 ++
dr
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/i915_gpu_error.c | 17 +
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915
cleanup / scratch merge patch series.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 138 +++-
1 file changed, 89 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/driver
: Ben Widawsky
Signed-off-by: Michel Thierry (v3+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 9 -
drivers/gpu/drm/i915/i915_trace.h | 16
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_
page table
level and here is no exception.
v2: Rebase after Mika's ppgtt cleanup / scratch merge patch series.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 51 -
1 file changed, 39 insertions(+
mber of pages
parameter in insert_pte_entries.
Cc: Akash Goel
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 51 -
drivers/gpu/drm/i915/i915_gem_gtt.h | 11
2 files changed, 50 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/
eries.
Suggested-by: Akash Goel
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 11 ---
2 files changed, 1 insertion(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_
.
v6: Rebase after Mika's ppgtt cleanup / scratch merge patch series, and follow
his nomenclature in pdp functions (there is no alloc_pdp yet).
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2+)
---
drivers/gpu/drm/i915/i915_drv.h | 7 +-
drivers/gpu/drm/i915/i915_gem_g
ture is only available in BDW and Gen9, requires LRC submission
mode (execlists) and setting i915.enable_ppgtt=3.
Also note that this expanded address space is only available for full PPGTT,
aliasing PPGTT remains 32b.
Michel Thierry (18):
drm/i915/lrc: Update PDPx registers with lri co
In a 48b world, users can try to allocate buffers bigger than 4GB; in
these cases it is important that size is a 64b variable.
Also added a warning for illegal bind with size = 0.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem.c | 5 +++--
drivers/gpu/drm/i915
After Mika's ppgtt cleanup series, all the other free functions have
drm_device as the first parameter, except this one.
No functional changes.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --
v2: Use the default ctx to infer the ppgtt max size (Akash).
Cc: Akash Goel
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_userptr.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c
b/drivers/g
Test I915_EXEC_SUPPORTS_48BADDRESS flag to use 32b+ segment.
Driver will try to use lower PDPs of each PPGTT for the objects
requiring Wa32bitGeneralStateOffset or Wa32bitInstructionBaseOffset.
v2: Add flink cases, (suggested by Daniel Vetter).
Signed-off-by: Michel Thierry
---
tests
Signed-off-by: Michel Thierry (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ea20e5a..1c9f662 100644
--- a/drivers/gpu/drm/i915/i915_gem_g
v2: Clean up patch after rebases.
v3: gen8_dump_ppgtt for 32b and 48b PPGTT.
v4: Use used_pml4es/pdpes (Akash).
v5: Rebase after Mika's ppgtt cleanup / scratch merge patch series.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2+)
---
drivers/gpu/drm/i915/i915_debugfs.c
allocated above the 32b address range.
The flag is ignored in 32b PPGTT.
v2: Changed flag logic from neeeds_32b, to supports_48b.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/i915_gem.c| 19 ++--
drivers/gpu/drm
added macros to initialize the pdps.
Suggested-by: Akash Goel
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 53 ++---
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
2 files changed, 51 insertions(+), 3 deletions(-)
diff --git a/drivers/gp
Use 48b addresses if hw supports it and i915.enable_ppgtt=3.
Note, aliasing PPGTT remains 32b only.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_params.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers
On 6/11/2015 8:31 AM, Dave Gordon wrote:
On 10/06/15 12:42, Michel Thierry wrote:
On 5/29/2015 1:53 PM, Michel Thierry wrote:
On 5/29/2015 12:05 PM, Michel Thierry wrote:
On 5/22/2015 6:04 PM, Mika Kuoppala wrote:
With BDW/SKL and 32bit addressing mode only, the hardware preloads
pdps
On 6/11/2015 7:04 PM, Mika Kuoppala wrote:
Michel Thierry writes:
A safer way to update the PDPx registers is sending lri commands, added
in the ring before the batchbuffer start. Otherwise, the ctx must be idle
before trying to change anything (but the ring-tail) in the ctx image. An
example
for legacy
gens. Rename it to clearly point out that it is offset into the
ggtt.
v2: Add comment about ggtt_offset (Michel)
Reviewed-by: Michel Thierry
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 120
On 6/11/2015 6:48 PM, Mika Kuoppala wrote:
All the paging structures are now similar and mapped for
dma. The unmapping is taken care of by common accessors, so
don't overload the reader with such details.
v2: Be consistent with goto labels (Michel)
Reviewed-by: Michel Thierry
Signe
: Changed flag logic from neeeds_32b, to supports_48b.
v3: Moved 48-bit support flag back to exec_object. (Chris, Daniel)
Cc: Chris Wilson
Cc: Daniel Vetter
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/i915_gem.c| 19
Changed size from u32 to u64 to support +4GB.
48-bit PPGTT test cases may need extra memory available.
Signed-off-by: Michel Thierry
---
lib/igt_aux.h | 2 +-
lib/intel_os.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/lib/igt_aux.h b/lib/igt_aux.h
index b2dc267
State Offset and Instruction State Offset
are limited to 32-bits.
Provide a flag to set when the 4GB limit is not necessary in a given bo.
48-bit range will only be used when explicitly requested.
Cc: dri-de...@lists.freedesktop.org
Signed-off-by: Michel Thierry
---
include/drm/i915_drm.h| 3
.
Signed-off-by: Michel Thierry
---
tests/gem_ppgtt.c | 153 +++---
1 file changed, 147 insertions(+), 6 deletions(-)
diff --git a/tests/gem_ppgtt.c b/tests/gem_ppgtt.c
index d1e484a..5b4dd63 100644
--- a/tests/gem_ppgtt.c
+++ b/tests/gem_ppgtt.c
State Offset and Instruction State Offset
are limited to 32-bits.
Set provided bo flag when the 4GB limit is not necessary, to be able to use
the full address space.
Cc: mesa-...@lists.freedesktop.org
Signed-off-by: Michel Thierry
---
src/mesa/drivers/dri/i965/gen8_misc_state.c | 6 +++---
src
the "C" locale).
Thanks, I'll follow up with a patch replacing existing %llu with %'llu.
Reviewed-by: Michel Thierry
Signed-off-by: Chris Wilson
---
lib/igt_core.c | 4
1 file changed, 4 insertions(+)
diff --git a/lib/igt_core.c b/lib/igt_core.c
index 1367863..8ac1
After Chris' "Enable locale dependent output to a terminal" patch,
we can put thousand separators into these long long outputs.
sed "s/%ll/%'ll/g"
Signed-off-by: Michel Thierry
---
lib/intel_os.c| 4 ++--
overlay/cpu-top.c | 2 +-
overlay
Changed size from u32 to u64 to support +4GB.
48-bit PPGTT test cases may need extra memory available.
v2: Use thousands separator (Chris)
Cc: Chris Wilson
Signed-off-by: Michel Thierry
---
lib/igt_aux.h | 2 +-
lib/intel_os.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions
Joonas has any more comments,
Reviewed-by: Michel Thierry
-Mika
bitmap_zero(new_page_tables, I915_PDES);
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On 6/11/2015 5:30 PM, Mika Kuoppala wrote:
Michel Thierry writes:
On 5/22/2015 6:05 PM, Mika Kuoppala wrote:
Lay out scratch page structure in similar manner than other
paging structures. This allows us to use the same tools for
setup and teardown.
Signed-off-by: Mika Kuoppala
valleyview (Ville)
v3: Now really fix flushes (Michel, Ville)
Daniel, I'll do some testing in bxt this week.
Having said that, before this patch the code was doing the flush in bxt,
so it doesn't change the current behavior...
Reviewed-by: Michel Thierry
Signed-off-by: Mik
). Removed superfluous semicolon
Cc: Ville Syrjälä
Reviewed-by: Michel Thierry
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 77 +++--
1 file changed, 40 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915
432314314-23530-17-git-send-email-mika.kuopp...@intel.com
Cc: Mika Kuoppala
Reported-by: John Harrison
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drive
On 6/24/2015 4:51 AM, Ben Widawsky wrote:
Hi. Feel free to Cc me on patches of this nature. I am far behind on mesa-dev,
and no longer read intel-gfx. I'm probably one of the sensible people to look at
this...
On Tue, Jun 23, 2015 at 01:21:27PM +0100, Michel Thierry wrote:
Gen8+ suppor
, but these won't return anything
larger than '512' (so they could be u32 if we want to get rid of size_t
completely).
I also tried reverting commit 501fd70f ("drm/i915: limit PPGTT size to
2GB in 32-bit platforms") in a bdw running a 32-bit kernel and it worked
fi
ds on 5b7e4c9ce ("drm/i915/gtt: Mark TLBS dirty for gen8+").
v2: Combine lri writes (and save 8 commands). (Mika)
v3: Rebase after ring/req changes, and removed references to deprecated patches.
Cc: Dave Gordon
Cc: Mika Kuoppala
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i
Chris Wilson (v2)
Signed-off-by: Michel Thierry
---
lib/igt_aux.h | 2 +-
lib/intel_os.c | 34 +-
2 files changed, 30 insertions(+), 6 deletions(-)
diff --git a/lib/igt_aux.h b/lib/igt_aux.h
index 9ea50de..139e5da 100644
--- a/lib/igt_aux.h
+++ b/lib/igt_aux.h
@@
igt_assert_cmp64 and its derivatives:
- igt_assert_eq64
- igt_assert_neq64
- igt_assert_lte64
- igt_assert_lt64
Signed-off-by: Michel Thierry
---
lib/igt_core.h | 69 +-
1 file changed, 63 insertions(+), 6 deletions(-)
diff --git a/lib
On 6/30/2015 12:42 PM, Chris Wilson wrote:
On Tue, Jun 30, 2015 at 12:31:46PM +0100, Michel Thierry wrote:
igt_assert_cmp64 and its derivatives:
- igt_assert_eq64
- igt_assert_neq64
- igt_assert_lte64
- igt_assert_lt64
Signed-off-by: Michel Thierry
---
lib/igt_core.h | 69
igt_assert_cmp64 and its derivatives:
- igt_assert_cmpu64
- igt_assert_eq64
- igt_assert_eq_u64
- igt_assert_neq64
- igt_assert_lte64
- igt_assert_lt64
v2: Add igt_assert_cmp_t, this macro handles int, long and
double var cases. (Chris)
Cc: Chris Wilson
Signed-off-by: Michel Thierry
---
lib
Also include script output.
Suggested-by: Daniel Vetter
Signed-off-by: Michel Thierry
---
lib/igt.cocci| 42 +++
tests/gem_cs_tlb.c | 2 +-
tests/kms_draw_crc.c | 6 ++---
tests/kms_frontbuffer_tracking.c | 54
On 6/30/2015 2:49 PM, Chris Wilson wrote:
On Tue, Jun 30, 2015 at 02:41:08PM +0100, Michel Thierry wrote:
igt_assert_cmp64 and its derivatives:
+#define INTDECFORMAT "%d"
+#define UINTHEXFORMAT "%#x"
+#define DOUBLEDECFORMAT "%#lf"
+#define LONGHEXFORMAT &
On 6/30/2015 2:54 PM, Chris Wilson wrote:
On Tue, Jun 30, 2015 at 02:41:09PM +0100, Michel Thierry wrote:
@@ -1109,7 +1109,7 @@ static void setup_sink_crc(void)
set_mode_for_params(&prim_mode_params);
sink_crc.fd = igt_debugfs_open("i915_sink_crc_eDP1&q
On 6/30/2015 4:16 PM, Mika Kuoppala wrote:
Maintain base page handling functions in order of
alloc, free, init. No functional changes.
v2: s/Introduce/Maintain (Michel)
v3: Rebase
Cc: Michel Thierry
Signed-off-by: Mika Kuoppala
Reviewed-by: Michel Thierry (v2)
v3 too.
---
drivers/gpu
On 6/30/2015 4:16 PM, Mika Kuoppala wrote:
When dma page is setup, warn if we try to point the entries
to a uninitialized (zero) dma address. Like we do with gen6
Reviewed-by: Michel Thierry
[Mental note to add the same in the future pdp initialize function].
Signed-off-by: Mika Kuoppala
On 6/30/2015 4:16 PM, Mika Kuoppala wrote:
Every other alloc_* function return the pointer to the page
they alloc. Follow the convention with scratch page also.
Reviewed-by: Michel Thierry
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 78
allocate per ppgtt scratch page.
Maybe also say that it moved scratch page/pt/pd operations together
(genx_init/free_scratch functions).
Daniel, since you requested this, should it get yours r-b?
It looks ok to me.
-Michel
Cc: Michel Thierry
Cc: Daniel Vetter
Signed-off-by: Mika Kuoppala
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