On 2/1/2018 2:25 AM, Tvrtko Ursulin wrote:
On 01/02/2018 00:52, Michel Thierry wrote:
From: Daniele Ceraolo Spurio
The main difference with previous GENs is that starting from Gen11
each VCS and VECS engine has its own power well, which only exist
if the related engine exists in the HW.
The
tko Ursulin
Cc: Paulo Zanoni
Acked-by: Michel Thierry
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Oscar Mateo
Signed-off-by: Michel Thierry
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_reg.h | 4 +
drivers/gpu/drm/i915/intel_uncore.c |
hopefully reduces the
frequency to 0...
References: https://bugs.freedesktop.org/show_bug.cgi?id=104262
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Michel Thierry
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c | 13 +
1 file changed, 9 insertions(+), 4 deletions
e was missing a r-b, but all 3:
Reviewed-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_context.c | 31
drivers/gpu/drm/i915/intel_engine_cs.c | 6 ++---
drivers/gpu/drm/i915/intel_guc_submission.c | 24 +-
drivers/gpu/drm
On 2/9/2018 11:38 AM, Yaodong Li wrote:
On 02/09/2018 08:46 AM, Michal Wajdeczko wrote:
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc_wopcm.c
@@ -0,0 +1,48 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2017-2018 Intel Corporation
+ *
Do we really want to keep legacy license
On 2/27/2017 1:35 AM, Daniel Vetter wrote:
On Thu, Feb 09, 2017 at 09:34:49AM +0200, Joonas Lahtinen wrote:
On ke, 2017-02-08 at 18:18 -0800, Michel Thierry wrote:
Bring the test/set/clear bit functions we have into a single place.
Signed-off-by: Michel Thierry
Reviewed-by: Joonas
Bring the test/set/clear bit functions we have into a single place.
v2: Add gtk-doc comment blocks (Daniel)
Cc: Daniel Vetter
Reviewed-by: Joonas Lahtinen (v1)
Signed-off-by: Michel Thierry
---
.../intel-gpu-tools/intel-gpu-tools-docs.xml | 1 +
lib/Makefile.sources
On 01/03/17 23:45, Daniel Vetter wrote:
On Wed, Mar 01, 2017 at 04:14:31PM +, Chris Wilson wrote:
On Wed, Mar 01, 2017 at 07:52:26AM -0800, Michel Thierry wrote:
Bring the test/set/clear bit functions we have into a single place.
v2: Add gtk-doc comment blocks (Daniel)
Hiss, boo! Will
Bring the test/set/clear bit functions we have into a single place.
v2: Add gtk-doc comment blocks (Daniel)
v3: Restore inline keyword.
Cc: Daniel Vetter
Reviewed-by: Joonas Lahtinen (v1)
Signed-off-by: Michel Thierry
---
.../intel-gpu-tools/intel-gpu-tools-docs.xml | 1 +
lib
LOCAL_CONTEXT_PARAM_NO_ERROR_CAPTURE exists in lib/ioctl_wrappers.h
since commit 171b21d9f761 ("igt/gem_ctx_param: Update invalid parma
number").
Cc: Chris Wilson
Signed-off-by: Michel Thierry
---
lib/igt_gt.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/lib/igt_gt.c b/li
).
Reported-by: Antonio Argenziano
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_debugfs.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9fcc4f1a86fc..89f211391ef9 100644
--- a/drive
On 3/14/2017 2:09 AM, Chris Wilson wrote:
On Mon, Mar 13, 2017 at 05:26:06PM -0700, Michel Thierry wrote:
At least in bxt (with decoupled mmio), it prevents a warning while
capturing the reg state:
[ ] WARNING: assert_rpm_wakelock_held.part.4+0x1e/0x20 [i915]
[ ] RPM wakelock ref not held
.
Reported-by: Antonio Argenziano
Signed-off-by: Chris Wilson
Cc: Michel Thierry
---
drivers/gpu/drm/i915/i915_irq.c | 25 ++---
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index
,
provide a simple debugfs entry to see the number of times media reset
has happened.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_debugfs.c | 28
drivers/gpu/drm/i915/intel_guc_fwif.h | 18 ++
2 files changed, 46 insertions(+)
diff --git a
he counter is different between render and
non-render engines.
v2: Move irq handler to tasklet, arm watchdog for a 2nd time to check
against false-positives.
Signed-off-by: Tomas Elf
Signed-off-by: Ian Lister
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/
For watchdog / media reset, the firmware must know the address of the shared
data page (the first page of the default context).
This information should be in DWORD 9 of the GUC_CTL structure.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +-
drivers/gpu/drm/i915
Mika Kuoppala
Signed-off-by: Ian Lister
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.c | 49 +++-
drivers/gpu/drm/i915/i915_drv.h | 7 +++-
drivers/gpu/drm
is is the minimal
set of registers identified for things to work as expected but if we see
any new issues, this register list can be expanded.
Signed-off-by: Arun Siluvery
Signed-off-by: Jeff McGee
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_guc_submission.c
unnecessary. To
avoid this we check if the engine is already prepared, if so we just exit
from that point.
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_uncore.c | 9 +++--
1 file changed, 7 insertions
engine count in i915_engine_info too (Chris).
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_debugfs.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b
From: Arun Siluvery
This feature is made available only from Gen8, for previous gen devices
driver uses legacy full gpu reset.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_params.c | 4
As all other functions related to resetting engines are using reset_engine.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_uncore.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915
of
combined start_watchdog, bb_start and stop_watchdog to avoid any error
after emitting bb_start.
Signed-off-by: Tomas Elf
Signed-off-by: Ian Lister
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_context.h | 4 ++
drivers/gpu/drm/i915/intel_lrc.c
updated to
be per context engine. Check for u32 overflow. Capture ctx threshold
value in error state.
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem_cont
it
is deemed useful, it can be extended to report each engine separately.
v2: s/engine_reset/reset_engine/, use union in uapi to not break compatibility.
Cc: Chris Wilson
Cc: Mika Kuoppala
Cc: mesa-...@lists.freedesktop.org
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915
i915_gem_reset_engine (Chris).
v4: Rebase, modify i915_gem_reset_prepare to use a ring mask and
reuse the function for reset_engine.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.c | 88
From: Arun Siluvery
In preparation for engine reset work update this parameter to handle more
than one type of reset. Default at the moment is still full gpu reset.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915
ngine reset count to error state
drm/i915/tdr: Export per-engine reset count info to debugfs
drm/i915/tdr: Enable Engine reset and recovery support
drm/i915/guc: Provide register list to be saved/restored during engine
reset
Michel Thierry (10):
drm/i915: Fix stale comment
It has been replaced by I915_RESET_BACKOFF / I915_RESET_HANDOFF.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e8250bb79d12
.
v2: s/engine_reset/reset_engine/ (Chris)
Define count as unsigned int (Tvrtko)
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 8
drivers/gpu/drm
Check that we can reset specific engines, also check the fallback to
full reset if something didn't work.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 144 +++
1 file changed, 144 insertions(+)
diff --git a/drivers/gpu/drm
requests are pending so after resetting
a engine, pending workloads/requests are resubmitted again.
Signed-off-by: Arun Siluvery
Signed-off-by: Jeff McGee
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.c| 43 +-
drivers/gpu/drm/i915/i915_drv.h
On 25/03/17 02:01, Chris Wilson wrote:
On Fri, Mar 24, 2017 at 06:29:54PM -0700, Michel Thierry wrote:
As all other functions related to resetting engines are using reset_engine.
However, we should aim to clear any confusion between this and our
requests. Maybe gen8_reset_engine_start and
On 25/03/17 02:26, Chris Wilson wrote:
On Fri, Mar 24, 2017 at 06:30:07PM -0700, Michel Thierry wrote:
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 87e76ef589b1..d484cbc561eb 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915
On 25/03/17 02:38, Chris Wilson wrote:
On Fri, Mar 24, 2017 at 06:30:09PM -0700, Michel Thierry wrote:
Final enablement patch for GPU hang detection using watchdog timeout.
Using the gem_context_setparam ioctl, users can specify the desired
timeout value in microseconds, and the driver will do
On 19/12/16 00:27, Tvrtko Ursulin wrote:
On 16/12/2016 20:20, Michel Thierry wrote:
From: Arun Siluvery
@@ -937,6 +937,7 @@ struct drm_i915_error_state {
enum intel_engine_hangcheck_action hangcheck_action;
struct i915_address_space *vm;
int num_requests
On 19/12/16 01:51, Chris Wilson wrote:
On Sun, Dec 18, 2016 at 09:02:33PM -0800, Michel Thierry wrote:
On 12/16/2016 12:45 PM, Chris Wilson wrote:
On Fri, Dec 16, 2016 at 12:20:05PM -0800, Michel Thierry wrote:
From: Arun Siluvery
This change implements support for per-engine reset as an
From: Arun Siluvery
This feature is made available only from Gen8, for previous gen devices
driver uses legacy full gpu reset.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_params.c | 4
i915_gem_reset_engine (Chris).
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.c | 69 +++--
drivers/gpu/drm/i915/i915_drv.h | 3 ++
drivers/gpu/drm/i915
unnecessary. To
avoid this we check if the engine is already prepared, if so we just exit
from that point.
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_uncore.c | 9 +++--
1 file changed, 7 insertions
: Enable Engine reset and recovery support
Michel Thierry (3):
drm/i915: Keep i915_handle_error kerneldoc parameters together
drm/i915: Update i915_reset parameter for kerneldoc
drm/i915: Add engine reset count in get-reset-stats ioctl
Mika Kuoppala (1):
drm/i915: Skip reset request if there
.
v2: s/engine_reset/reset_engine/ (Chris)
Define count as unsigned int (Tvrtko)
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 8
drivers/gpu/drm
And before the function description.
Tidy up from commit 14bb2c11796d70b ("drm/i915: Fix a buch of kerneldoc
warnings"), all others kerneldoc blocks look ok.
Cc: Tvrtko Ursulin
Reviewed-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
Signed-off-by: Michel Thierry
---
drivers/gp
From: Arun Siluvery
In preparation for engine reset work update this parameter to handle more
than one type of reset. Default at the moment is still full gpu reset.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915
engine count in i915_engine_info too (Chris).
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_debugfs.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b
Since commit c033666a94b57 ("drm/i915: Store a i915 backpointer from
engine, and use it") i915_reset receives dev_priv, but the kerneldoc
was not updated.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
it
is deemed useful, it can be extended to report each engine separately.
v2: s/engine_reset/reset_engine/.
Cc: Chris Wilson
Cc: Mika Kuoppala
Cc: mesa-...@lists.freedesktop.org
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_context.c | 14 +++---
include/uapi/drm
Chris)
Handle reset as 2 level resets, by first going to engine only and fall
backing to full/chip reset as needed, i.e. reset_engine will need the
struct_mutex.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Ian Lister
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
Signed-off-by: M
On 11/01/17 23:30, Chris Wilson wrote:
I'm sorry to do this, but there is a regression fix for gen3 required
first that makes this more complicated.
https://cgit.freedesktop.org/~ickle/linux-2.6/commit/?h=prescheduler&id=de399a0a6baae97910796d81d8b9324db3fdd77c
https://cgit.freedesktop.org/~ick
From: Michel Thierry
HDC_CHICKEN0 bit 14 (Fence Destination To SLM Disable) must be
programmed by software to 1h (Disable) to work around a LSLM unit issue.
WaDisableFenceDestinationToSLM is only needed for BDW E,F step.
Issue: APDEV-3096
Signed-off-by: Michel Thierry
---
drivers/gpu/drm
On 25/02/15 17:54, Arun Siluvery wrote:
Some of the workarounds are to be applied during context save but before
restore and some at the end of context save/restore but before executing
the instructions in the ring. Workaround batch buffers are created for
this purpose as they cannot be applied
No functional changes, but will improve code clarity and removed some
duplicated defines.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 160 ++--
drivers/gpu/drm/i915/i915_gem_gtt.h | 28 ---
2 files changed, 96 insertions(+), 92
refore, we also must
reinitialize.
v2: to->ppgtt is only valid in full ppgtt.
v3: Rebased.
v4: Make post PDP update clearer.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2+)
---
drivers/gpu/drm/i915/i915_gem_context.c | 28 +++-
1 file changed, 19 insertions(+
l)
v3: Add missing pd load logic.
v4: Add warning in case pd_load_pre & pd_load_post are true, and add
missing trace_switch_mm. Cleaned up pd_load conditions. Add more
information about when is pd_load_post needed. (Mika)
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2+)
---
driver
ise bitmap allocation here (gen6_alloc_va_range) and fix
incorrect write_page_range in i915_gem_restore_gtt_mappings (Mika).
Cc: Daniel Vetter
Cc: Mika Kuoppala
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v3+)
---
drivers/gpu/drm/i915/i915_gem.c | 9 ++
drivers/gpu/drm/i915/i915
to i915_hw_ppgtt. Fixes when
neither ctx->ppgtt and aliasing_ppgtt exist.
v5: Removed references to teardown_va_range.
v6: Updated needs_pd_load_pre/post.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2+)
---
drivers/gpu/drm/i915/i915_gem_context.c| 26
ld help to
clean some of the code.
Ben Widawsky (4):
drm/i915: Extract context switch skip and add pd load logic
drm/i915: Track GEN6 page table usage
drm/i915: Track page table reload need
drm/i915: Initialize all contexts
Michel Thierry (1):
drm/i915: page table generalizations
drive
On 3/3/2015 11:48 AM, akash goel wrote:
On Fri, Feb 20, 2015 at 11:15 PM, Michel Thierry
wrote:
From: Ben Widawsky
This transitional patch doesn't do much for the existing code. However,
it should make upcoming patches to use the full 48b address space a bit
easier to swallow. The patch
On 3/3/2015 12:16 PM, akash goel wrote:
On Fri, Feb 20, 2015 at 11:15 PM, Michel Thierry
wrote:
From: Ben Widawsky
Up until now, ppgtt->pdp has always been the root of our page tables.
Legacy 32b addresses acted like it had 1 PDP with 4 PDPEs.
In preparation for 4 level page tables, we n
On 3/3/2015 12:23 PM, akash goel wrote:
On Fri, Feb 20, 2015 at 11:15 PM, Michel Thierry
wrote:
From: Ben Widawsky
Note that there is no gen8 ppgtt debug_dump function yet.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_debugfs.c | 19
On 3/19/2015 9:01 AM, Mika Kuoppala wrote:
Michel Thierry writes:
From: Ben Widawsky
This patch was formerly known as, "Force pd restore when PDEs change,
gen6-7." I had to change the name because it is needed for GEN8 too.
The real issue this is trying to solve is when a new
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2+)
---
drivers/gpu/drm/i915/i915_gem.c| 4
drivers/gpu/drm/i915/i915_gem_context.c| 26 --
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 7 +++
drivers/gpu/drm/i915/i915_gem_gtt.c
bjects are allocated in i915_gem_capture_buffers, but not
released in i915_error_state_free:
- error->active_bo_count
- error->pinned_bo
- error->pinned_bo_count
- error->active_bo[vm_count] (allocated in i915_gem_capture_vm).
Signed-off-by: Michel Thierry
---
drivers/gpu/drm
On 3/19/2015 4:13 PM, Daniel Vetter wrote:
On Mon, Mar 16, 2015 at 04:00:56PM +, Michel Thierry wrote:
+static inline uint32_t i915_pte_count(uint64_t addr, size_t length,
+ uint32_t pde_shift)
+{
+ const uint64_t mask = ~((1 << pde_shif
On 3/19/2015 5:18 PM, Chris Wilson wrote:
On Thu, Mar 19, 2015 at 05:11:17PM +, Michel Thierry wrote:
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index bbf25d0..18f7a2a 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm
e introduced by
commit 95f5301dd880da2dea2c9a9c29750064536d426a
Author: Ben Widawsky
Date: Wed Jul 31 17:00:15 2013 -0700
drm/i915: Update error capture for VMs
v2: Reuse iterator and add culprit commit details (Chris)
Cc: Chris Wilson
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gpu_error.c | 7 +++
1 file
lle)
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_gpu_error.c | 10 ++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
3 files changed, 15 insertions(+)
Thanks for noticing that last typo...
Reviewed-by: Michel Thie
Found by static analysis tool, this was harmless as the pt was not
used out of scope though.
Introduced by commit 678d96fbb3b5995a2fdff2bca5e1ab4a40b7e968
("drm/i915: Track GEN6 page table usage").
Cc: Mika Kuoppala
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem
The first 2 patches are fixes from the previous patchset, reported by static
analysis tools, while the last 2 patches complete the required work for gen6/7.
I've also started changing the authorship of the patches as suggested by Daniel.
Michel Thierry (5):
drm/i915: Prevent out of range
Traces for page directories and tables allocation and map.
v2: Removed references to teardown.
v3: bitmap_scnprintf has been deprecated.
v4: Replace bitmap_scnprintf with scnprintf correctly, and get right
range lengths. (Mika)
Cc: Mika Kuoppala
Signed-off-by: Michel Thierry
---
drivers/gpu
i915_dma_map_single relies on dma_mapping_error, which returns positive
error codes. Found by static checker.
Introduced by commit 678d96fbb3b5995a2fdff2bca5e1ab4a40b7e968
("drm/i915: Track GEN6 page table usage").
Cc: Dan Carpenter
Cc: Mika Kuoppala
Signed-off-by: Michel Thierry
--
d alloc_pt_scratch becomes
redundant. Initialize scratch_pt and pt. (Mika)
v10: Clean up aliasing ppgtt init error path and prevent leaking the
ppgtt obj when init fails. (Mika)
Updated commit author. (Daniel)
Cc: Mika Kuoppala
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v4+)
---
dr
We are already unmapping them in gen6_ppgtt_free. This function became
redundant since commit 06fda602dbca9c59d87db7da71192e4b54c9f5ff
("drm/i915: Create page table allocators").
Cc: Mika Kuoppala
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 11 -
On 3/24/2015 4:03 PM, Dan Carpenter wrote:
On Tue, Mar 24, 2015 at 06:57:13PM +0300, Dan Carpenter wrote:
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 645c363..79ade6f 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i91
Carpenter
Cc: Mika Kuoppala
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 645c363..6bb31c8 100644
--- a/drivers/gp
3: Missing reported-by tag (Daniel)
Reported-by: Dan Carpenter
Cc: Dan Carpenter
Cc: Mika Kuoppala
Cc: Daniel Vetter
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/d
se 7: return print_ivb_error(reg, devid);
case 6: return print_snb_error(reg);
}
--
1.9.1
Looks good (I don't expect to see these PASID errors soon).
Reviewed-by: Michel Thierry
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
("Source ID %d\n", reg >> 3 & 0xff);
+}
+
#define MAX_RINGS 10 /* I really hope this never... */
uint32_t head[MAX_RINGS];
int head_ndx = 0;
@@ -520,6 +558,10 @@ read_data_file(FILE *file)
if (matched == 2)
print_f
print_fault_reg(devid, reg);
+ matched = sscanf(line, " FAULT_TLB_DATA: 0x%08x 0x%08x\n",
®, ®2);
+ if (matched == 2)
+ print_fault_data(devid, reg, reg2);
+
continue;
/coccinelle/misc/simple_return.cocci
CC: Michel Thierry
Signed-off-by: Fengguang Wu
---
i915_gem_gtt.c |8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1344,13 +1344,7 @@ err_out:
static
/page_table/.
v7: Renamed commit to match what it does now (it was "Use dynamic
allocation idioms on free").
v8: Prevent (harmless) out of range access in gen8_for_each_pde and
gen8_for_each_pdpe_e.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2+)
---
drivers/gp
: Initialize all page tables, including the extra ones from systems
with less than 4GB of memory. (Mika)
Cc: Mika Kuoppala
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 83 ++---
1 file changed, 59 insertions
awsky
Signed-off-by: Michel Thierry (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 32 +---
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
2 files changed, 22 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm
)
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 8e47caf..cd28e343 100644
--- a/drivers/gpu/drm/i915
i915_page_directory/
s/struct i915_page_directory_pointer_entry/struct
i915_page_directory_pointer/
Suggested-by: Mika Kuoppala
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 56 ++---
drivers/gpu/drm/i915/i915_gem_gtt.h | 16 +--
drivers/gpu
ce address range in these systems.
Michel Thierry (13):
drm/i915: Remove _entry from PPGTT page structures
drm/i915: Remove unnecessary gen8_ppgtt_unmap_pages
drm/i915/gen8: Initialize page tables
drm/i915/gen8: Add dynamic allocation macros and helper functions
drm/i915/gen8: page director
ft broken
until it was updated to handle the init case without any PDP.
v12: Do not overallocate new_pts bitmap, make alloc_gen8_temp_bitmaps
static and don't abuse of inline functions. (Mika)
Cc: Mika Kuoppala
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2+)
---
driver
True PPGTT is capable of having a full address space, even if the system
has less allocated memory.
Note that aliasing PPGTT always aliases the GGTT and thus should remain
of the same size.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +---
1 file changed, 1
ables/page_table/.
v5: Rebased after page table generalizations.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 59 +
drivers/gpu/drm/i915/i915_gem_gtt.h | 7 +
2 files changed, 54 insertions(+), 12 dele
This will be useful for when we move to 48b addressing, and the PDP isn't
the root of the page table structure.
v2: Rebase after changes for Gen8+ systems with less than 4GB of memory.
v3: Rebase after Mika's code review.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Th
ll PDPs in GEN8+ systems with less than 4GB of
memory, and update populate_lr_context to handle this new case (proper
tracking will be added later in the patch series).
v6: Assign lrc page directory pointer addresses using a macro. (Mika)
Cc: Mika Kuoppala
Signed-off-by: Ben Widawsky
Signed-off-
We are already unmapping them in gen8_ppgtt_free. This function became
redundant since commit 06fda602dbca9c59d87db7da71192e4b54c9f5ff
("drm/i915: Create page table allocators").
Cc: Mika Kuoppala
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_
allocating all page directories in GEN8+ systems with less
than 4GB of memory. Updated gen6_for_all_pdes.
v6: Prevent (harmless) out of range access in gen6_for_all_pdes.
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2+)
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 --
drivers/gpu
: Initialize also the extra PDs from systems with less than 4GB of
memory. (Mika)
Cc: Mika Kuoppala
Signed-off-by: Ben Widawsky
Signed-off-by: Michel Thierry (v2+)
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 100 ++--
1 file changed, 85 insertions(+), 15 deletions(-)
diff
ote about
sampling request->tail in commit message (Chris).
Cc: Chris Wilson
Signed-off-by: Thomas Daniel
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem.c | 15 ++-
drivers/gpu/drm/i915/intel_lrc.c | 27 ++-
2 files changed, 40 insertions
Exercise lite-restore (re-submit a context that is currently running),
by queueing several small batchbuffers.
This test helps to validate WaIdleLiteRestore.
Signed-off-by: Michel Thierry
---
tests/gem_ctx_exec.c | 30 +-
1 file changed, 29 insertions(+), 1 deletion
On 11/4/2014 12:54 PM, Daniel Vetter wrote:
On Tue, Oct 07, 2014 at 06:10:56PM +0100, Michel Thierry wrote:
This is based on the first 55 patches of Ben's 48b addressing work, taking
into consideration the latest changes in (mainly aliasing) ppgtt rules.
Because of these changes in the
On 11/4/2014 7:23 PM, Rodrigo Vivi wrote:
These patches got listed to -collector but got a huge conflict. If it
is still relevant please rebase it.
Also my bikeshed is to findo better names to help on differentiate
them at least.
On Wed, Sep 24, 2014 at 5:02 AM, Michel Thierry
wrote
On 11/10/2014 4:38 PM, Mika Kuoppala wrote:
Arun Siluvery writes:
From: Michel Thierry
Following the legacy ring submission example, update the
ring->init_context() hook to support the execlist submission mode.
v2: update to use the new workaround macros and cleanup unused code.
This ta
ing deferred context creation.
v3: Split init_context (emit) in legacy/lrc modes. For lrc, get the ringbuf
from the context. (Mika/Daniel).
Issue: VIZ-4092
Issue: GMIN-3475
Change-Id: Ie3d093b2542ab0e2a44b90460533e2f979788d6c
Cc: Deepak S
Cc: Mika Kuoppala
Cc: Daniel Vetter
Signed-off-by: Michel Thie
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