inside intel_engines_init_mmio().
Suggested-by: Chris Wilson
Signed-off-by: Michel Thierry
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_engine_cs.c | 2 ++
drivers/gpu/drm/i915/intel_uncore.c| 2 --
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915
: IHD-OS-SKL-Vol 2c-05.16, page 350.
Signed-off-by: Michel Thierry
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 52 +++
drivers/gpu/drm/i915/i915_gpu_error.c | 8 --
drivers/gpu/drm/i915/i915_reg.h | 2 ++
3 files changed, 47 insertions
On 11/10/2017 5:15 PM, Chris Wilson wrote:
Quoting Patchwork (2017-11-11 01:03:20)
== Series Details ==
Series: series starting with [1/2] drm/i915: Clear per-engine fault register as
early as possible
URL : https://patchwork.freedesktop.org/series/33649/
State : success
BAT results arri
check for
engine presence before posting_read (Chris).
References: IHD-OS-BDW-Vol 2c-11.15, page 75.
References: IHD-OS-SKL-Vol 2c-05.16, page 350.
Signed-off-by: Michel Thierry
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 57 ++-
drivers/gpu/drm
bably guc_init_doorbell_hw is no longer the right name, but I'll
leave that to someone else.
Signed-off-by: Michel Thierry
Cc: Sagar Arun Kamble
Cc: Sujaritha Sundaresan
Cc: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_guc_submis
ubtest.
Signed-off-by: Michel Thierry
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_guc_submission.c | 4 +
.../gpu/drm/i915/selftests/i915_live_selftests.h | 1 +
drivers/gpu/drm/i915/selftests/intel_guc.c | 362 +
From: Michal Wajdeczko
Also revert ("drm/i915/guc: Assert that we switch between
known ggtt->invalidate functions")
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++--
drivers/gpu/drm/i915/i915_params.h | 4 ++--
2 files changed, 4 insertions(+), 8 deletions(
On 11/16/2017 7:10 AM, Chris Wilson wrote:
Quoting Michel Thierry (2017-11-15 18:30:27)
The first test aims to check guc_init_doorbell_hw, changing the existing
guc clients and doorbells state before calling it.
The second test tries to create as many clients as it is currently possible
he subtest.
v5: Remove redundant pr_info at the beginning of each subtest (Chris);
rebase (s/i915_guc_client/intel_guc_client/).
Signed-off-by: Michel Thierry
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_guc_submission
From: Michal Wajdeczko
Also revert ("drm/i915/guc: Assert that we switch between
known ggtt->invalidate functions")
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++--
drivers/gpu/drm/i915/i915_params.h | 4 ++--
2 files changed, 4 insertions(+), 8 deletions(
: ELSP[3] = 0x6_fedb2119 [execlist0] - status_reg = 0x7_8308
Note that having to wait for this ack does not disable lite-restores,
although it may reduce their numbers.
And take this as a RFC, since there are probably better ways to still
respect this HW requirement.
Bugzilla: https://bugs.freede
=103800
References: https://bugs.freedesktop.org/show_bug.cgi?id=102035
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
Cc: Michal Winiarski
Cc: Michel Thierry
---
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
early to allow preemption
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102035
Suggested-by: Michel Thierry
Signed-off-by: Chris Wilson
Cc: Michel Thierry
Isn't it nice to come back after the weekend and see everything is ok?
Reviewed-by: Michel Thierry
Thanks,
---
driver
On 11/20/2017 5:26 AM, Chris Wilson wrote:
Make the private array used for stashing test clients static, to silence
sparse.
References: 55bd6bd75717 ("drm/i915/selftests: Add a GuC doorbells selftest")
Signed-off-by: Chris Wilson
Cc: Michel Thierry
Cc: Michal Wajdeczko
Cc: Danie
/i915/selftests: Add a GuC doorbells selftest")
Signed-off-by: Chris Wilson
Cc: Michel Thierry
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Anyway, thanks for fixing it and sorry for these new sparse warnings.
Reviewed-by: Michel Thierry
---
drivers/gpu/drm/i915/selftests/intel_gu
On 10/5/2017 12:10 PM, Chris Wilson wrote:
Michel Thierry noticed that we were applying WaDisableCtxRestoreArbitration
even to gen9, which does not require the w/a. The rationale is that we
need to enable MI arbitration for execlists to work, and to be safe we
do that before every batch (in
hat changed this? E.g.:
Now that we write RING_FORCE_TO_NONPRIV registers directly to hardware
[commit 32ced39c1b12 ("drm/i915: Transform whitelisting WAs into a
simple reg write")]...
Anyway,
Reviewed-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 8 +---
1 fi
On 10/9/2017 11:41 AM, Daniele Ceraolo Spurio wrote:
On 09/10/17 07:52, Michał Winiarski wrote:
We were using first page of kernel context render state for sharing data
with GuC. While it's justified by the fact that those pages are not used
(note, GuC still enforces this layout and refuses to
On 09/10/17 15:35, Michel Thierry wrote:
On 10/9/2017 11:41 AM, Daniele Ceraolo Spurio wrote:
On 09/10/17 07:52, Michał Winiarski wrote:
We were using first page of kernel context render state for sharing data
with GuC. While it's justified by the fact that those pages are not used
rt - we're already in user requested
submission mode.
Signed-off-by: Michał Winiarski
Cc: Chris Wilson
Cc: Michal Wajdeczko
Cc: Michel Thierry
Cc: Mika Kuoppala
Cc: Oscar Mateo
Reviewed-by: Chris Wilson
The nice side-effect of this is that in order support reset engine using
GuC subm
On 12/10/17 13:35, Michel Thierry wrote:
On 09/10/17 15:35, Michel Thierry wrote:
On 10/9/2017 11:41 AM, Daniele Ceraolo Spurio wrote:
On 09/10/17 07:52, Michał Winiarski wrote:
We were using first page of kernel context render state for sharing
data
with GuC. While it's justified b
t;drm/i915:bxt: implement WaProgramL3SqcReg1DefaultForPerf")
Fixes: 450174f ("drm/i915/chv: Tune L3 SQC credits based on actual latencies")
Signed-off-by: Oscar Mateo
Cc: Chris Wilson
Cc: Mika Kuoppala
Cc: Ville Syrjälä
Cc: Imre Deak
Cc: Michel Thierry
If this gets lost i
e bug fixed by
commit 7f1ea2ac3017 ("drm/i915/guc: Fix doorbell id selection").
Signed-off-by: Michel Thierry
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Michal Winiarski
---
drivers/gpu/drm/i915/i915_guc_submission.c | 4 +
.../gpu/drm/i915/selftests/i915_live_self
x27;s also confusing (why are we using this
particular page?). Let's allocate a separate object instead.
v2: Drop kernel_context from GuC suspend/resume action handlers (Michel)
v2 Reviewed-by: Michel Thierry
Suggested-by: Daniele Ceraolo Spurio
Signed-off-by: Michał Winiarski
Cc: C
On 25/10/17 14:08, Chris Wilson wrote:
Quoting Michel Thierry (2017-10-25 21:53:44)
Try to create multiple clients (one of each kind) and exercise the
doorbell alloc/dealloc code.
Since our usage mode require very few clients/doorbells, this code has
been exercised very lightly and it's
On 25/10/17 14:19, Michel Thierry wrote:
On 25/10/17 14:08, Chris Wilson wrote:
Quoting Michel Thierry (2017-10-25 21:53:44)
Try to create multiple clients (one of each kind) and exercise the
doorbell alloc/dealloc code.
Since our usage mode require very few clients/doorbells, this code has
On 26/10/17 07:17, Michał Winiarski wrote:
@@ -763,14 +770,14 @@ static int guc_init_doorbell_hw(struct intel_guc *guc)
/* Now for every client (and not only execbuf_client) make sure their
* doorbells are known by the GuC */
- //for (client = client_list; client != NULL
rbell_hw (Chris).
Signed-off-by: Michel Thierry
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Michal Winiarski
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_guc_submission.c | 15 +-
.../gpu/drm/i915/selftests/i915_live_selftests.h | 1 +
drivers/gpu/drm/i915/selfte
On 26/10/17 11:51, Michel Thierry wrote:
Try to create as many clients as it is currently possible (currently
limited to max number of doorbells) and exercise the doorbell
alloc/dealloc code.
Since our usage mode require very few clients/doorbells, this code has
been exercised very lightly and
On 10/26/2017 1:02 PM, Chris Wilson wrote:
Quoting Michel Thierry (2017-10-26 19:49:06)
On 26/10/17 07:17, Michał Winiarski wrote:
@@ -763,14 +770,14 @@ static int guc_init_doorbell_hw(struct intel_guc *guc)
/* Now for every client (and not only execbuf_client) make sure their
sm
available to submit work."
Suggested-by: Daniele Ceraolo Spurio
Cc: Rodrigo Vivi
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.
ko (1):
HAX enable GuC submission for CI
Michel Thierry (2):
drm/i915/guc: Rename the function that resets the GuC
drm/i915/guc: Add support for reset engine using GuC commands
drivers/gpu/drm/i915/i915_drv.c | 9 +++--
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/gpu/drm
From: Michal Wajdeczko
Also revert ("drm/i915/guc: Assert that we switch between
known ggtt->invalidate functions")
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++--
drivers/gpu/drm/i915/i915_params.h | 4 ++--
2 files changed, 4 insertions(+), 8 deletions(
regardless of submission mode. (Chris)
v4: Rebase.
v5: Do not pass unnecessary reporting flags to the fw (Jeff);
tasklet_schedule(&execlists->irq_tasklet) handles the resubmit; rebase.
Signed-off-by: Michel Thierry
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 9 +++--
: Michel Thierry
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_uc.c | 4 ++--
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm
On 30/10/17 13:58, Chris Wilson wrote:
Quoting Michel Thierry (2017-10-30 18:56:15)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index af745749509c..02fb35744f66 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1984,10
On 30/10/17 14:09, Chris Wilson wrote:
Quoting Michel Thierry (2017-10-30 18:56:15)
This patch adds per engine reset and recovery (TDR) support when GuC is
used to submit workloads to GPU.
In the case of i915 directly submission to ELSP, driver manages hang
detection, recovery and resubmission
EL_VGA_DEVICE(0x8A5D, info), \
+ INTEL_VGA_DEVICE(0x8A52, info), \
+ INTEL_VGA_DEVICE(0x8A5A, info), \
+ INTEL_VGA_DEVICE(0x8A5B, info), \
+ INTEL_VGA_DEVICE(0x8A71, info), \
+ INTEL_VGA_DEVICE(0x8A70, info)
+
#endif /* _I915_PCIIDS_H */
List is still correct and up-to-date.
R
= INTEL_ICELAKE,
.is_alpha_support = 1,
.has_resource_streamer = 0,
+ .ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
};
/*
--
2.14.1
Reviewed-by: Michel Thierry
___
Intel-gfx mailing list
Intel-gfx
(index);
+ case VCS3:
+ return GEN11_MFX2_MOCS(index);
default:
MISSING_CASE(engine_id);
return INVALID_MMIO_REG;
--
2.14.1
Reviewed-by: Michel Thierry
___
Intel-gfx mailing list
Int
Head!=Tail when attempting lite
restore.
Note that after some digging by Michal Winiarski, we found that
RING_HEAD is no longer being updated (due to inhibiting context save
restore) so this patch is already in effect!
Signed-off-by: Chris Wilson
Cc: Michal Winiarski
Cc: Michel Thierr
Mostly doc/print messages that were not updated after commit e61e0f51ba79
("drm/i915: Rename drm_i915_gem_request to i915_request").
Signed-off-by: Michel Thierry
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.h | 2 +-
drivers/gpu/drm/i915/i915_request.c
On 22/02/18 10:45, Michal Wajdeczko wrote:
Right after GPU reset there will be a small window of time during which
some of GuC/HuC fields will still show state before reset. Let's start
to fix that by sanitizing firmware status as we will use it shortly.
Suggested-by: Daniele Ceraolo Spurio
Sig
On 22/02/18 13:21, Michal Wajdeczko wrote:
On Thu, 22 Feb 2018 21:52:39 +0100, Michel Thierry
wrote:
On 22/02/18 10:45, Michal Wajdeczko wrote:
Right after GPU reset there will be a small window of time during which
some of GuC/HuC fields will still show state before reset. Let's sta
On 28/02/18 09:18, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
In decimal its just a weird big number, while in hex can actually log
which engines were requested to be wedged.
And IGT is not reading the hang reason in this case, so
Reviewed-by: Michel Thierry
Signed-off-by: Tvrtko
On 28/02/18 10:42, Piotr Piórkowski wrote:
In the i915 driver, there is a function, intel_guc_init_params(),
which initializes the GuC parameter block which is passed into
the GuC. There is parameter GUC_CTL_DEVICE_INFO with values
GfxGtType and GfxCoreFamily unused by GuC.
This patch remove GUC
On 28/02/18 12:26, Michel Thierry wrote:
On 28/02/18 10:42, Piotr Piórkowski wrote:
In the i915 driver, there is a function, intel_guc_init_params(),
which initializes the GuC parameter block which is passed into
the GuC. There is parameter GUC_CTL_DEVICE_INFO with values
GfxGtType and
So change timeout_ts and use time_after64 in gen11_gt_engine_intr.
Fixes: 51951ae7ed00 ("drm/i915/icl: Interrupt handling").
Suggested-by: Tvrtko Ursulin (long time ago)
Signed-off-by: Michel Thierry
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Oscar Mateo
Cc: Mika Kuoppala
--
On 3/1/2018 10:07 AM, Michel Thierry wrote:
So change timeout_ts and use time_after64 in gen11_gt_engine_intr.
I just read Chris' original comment about this, so ignore the patch,
"The squash should be made, but time_after64 is no more correct since
the native 32b/64b wrapped ari
description
- Remove also GUC_CORE_FAMILY_* definitions (Michel)
Signed-off-by: Piotr Piórkowski
Cc: Sagar Arun Kamble
Cc: Michał Winiarski
Cc: John A Spotswood
Cc: Michal Wajdeczko
Cc: Chris Wilson
Cc: Michel Thierry
---
drivers/gpu/drm/i915/intel_guc.c | 24
15 in functions that don't
perform register reads.
v2: take i915 from error->i915 (Michal), s/dev_priv/i915,
update commit message
Cc: Michal Wajdeczko
Cc: Chris Wilson
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Michel Thierry
---
drivers/
Hi,
On 3/12/2018 7:41 AM, Mika Kuoppala wrote:
Interrupt identity register we already read from hardware
contains engine class and instance fields. Leverage
these fields to find correct engine to handle the interrupt.
add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-160 (-160)
Function
ith pending modeset
updates\n");
+
/*
* Need mode_config.mutex so that we don't
* trample ongoing ->detect() and whatnot.
Looks fine to me since it only affects very old platforms, and is a
temporary measure.
Reviewed-by: Tvrtko Ursulin
Also,
Reviewed-by:
Hi,
First sorry about the delay...
On 7/20/2017 10:57 AM, Daniel Vetter wrote:
There's no reason to entirely wedge the gpu, for the minimal deadlock
bugfix we only need to unbreak/decouple the atomic commit from the gpu
reset. The simplest way to fix that is by replacing the
unconditional fence
block) {
- i915_sw_fence_wait(&intel_state->commit_ready);
+ if (nonblock)
+ queue_work(system_unbound_wq, &state->commit_work);
+ else
intel_atomic_commit_tail(state);
- }
+
return 0;
}
Reviewed-by: Michel Thierry
On 8/4/2017 9:26 AM, Michal Wajdeczko wrote:
GuC may return additional data in the command status response.
Format and meaning of this data is action specific.
We will use this non-negative data as a new success return value.
Signed-off-by: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Michel Thierry
On 8/4/2017 9:26 AM, Michal Wajdeczko wrote:
This is a preparation step for the upcoming patches.
We already can return some small data decoded from the command
status, but we will need more in the future.
Signed-off-by: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Daniele Ceraolo
but still hide underlying details.
Signed-off-by: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_uc.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
ind
status dword as return value */
ret = INTEL_GUC_RECV_TO_DATA(status);
}
Reviewed-by: Michel Thierry
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On 8/4/2017 9:27 AM, Michal Wajdeczko wrote:
From: Oscar Mateo
This function, symmetrical to the send(), will handle Guc2Host message
interrupts (which at the moment still only covers requests to flush
the GuC logs).
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Signed-off-by: Oscar Mateo
On 8/7/2017 8:33 AM, Daniel Vetter wrote:
On Thu, Aug 03, 2017 at 12:44:40PM -0700, Michel Thierry wrote:
On 7/20/2017 10:57 AM, Daniel Vetter wrote:
Blocking in a worker is ok, that's what the unbound_wq is for. And it
unifies the paths between the blocking and nonblocking commit, givi
: fix prohibited space after '~' (Michel)
update commit message (Daniele)
Signed-off-by: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_ct.c | 14 +++---
drivers/gpu/drm/i915/intel_guc_fwif.h | 6 ++
interrupt was for the
stale state from before the reset, and the contents of the CSB buffer
are now invalid.
Reported-by: "Dong, Chuanxiao"
Signed-off-by: Chris Wilson
Cc: "Dong, Chuanxiao"
Cc: Tvrtko Ursulin
Cc: Michal Winiarski
Cc: Michel Thierry
---
drivers/gpu/drm/i
y emabarrassing fixup, I checked the wrong bit and broke the
unbreak/wakeup logic.
v4: Also handle deadlocks in pin_to_display.
v5: Review from Michel:
- Fixup the BUILD_BUG_ON
- Don't forget about the overlay
Reviewed-by: Michel Thierry
Cc: Michel Thierry
Cc: Chris Wilson
Cc: Mika Kuo
where and those results may be clobbered by the concurrent
dropping of forcewake.
Reported-by: Michel Thierry
Fixes: 142bc7d99bcf ("drm/i915: Modify error handler for per engine hang
recovery")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Michel Thierry
---
drivers/gpu/dr
Cc: "Dong, Chuanxiao"
Cc: Tvrtko Ursulin
Cc: Michal Winiarski
Cc: Michel Thierry
Link:
https://patchwork.freedesktop.org/patch/msgid/20170807121919.30165-1-ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/intel_lrc.c | 23 ++-
1 file changed, 22 insertions(+), 1 delet
("drm/i915: Stop
touching forcewake following a gen6+ engine reset"), lets try to enable
per-engine resets in Broxton one more time.
This reverts commit f188258bde0f ("drm/i915: Disable per-engine reset for
Broxton").
Cc: Chris Wilson
Signed-off-by: Michel Thierry
---
&dev_priv->gpu_error.flags)) {
+ engine_mask &= ~intel_engine_flag(engine);
continue;
+ }
if (i915_reset_engine(engine, 0) == 0)
engine_mask &= ~intel_
Gen7 won't get any new engines, and we already added VCS2 there to just
silence gcc's not-handled-in-switch warnings.
Use a default case instead, otherwise we will need to keep adding extra
cases if changes happen in the future.
Signed-off-by: Michel Thierry
---
drivers/gp
On 29/08/17 12:18, Chris Wilson wrote:
Quoting Michel Thierry (2017-08-29 19:55:45)
Gen7 won't get any new engines, and we already added VCS2 there to just
silence gcc's not-handled-in-switch warnings.
Use a default case instead, otherwise we will need to keep adding extra
cases
GEM_BUG_ON (Chris).
Cc: Chris Wilson
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c277a26bbd99..8a
On 05/09/17 06:57, Chris Wilson wrote:
Quoting Chris Wilson (2017-08-21 15:55:34)
Quoting Michel Thierry (2017-08-18 18:23:42)
The corruption in CSB mmio reads we were seeing has been tracked down to
incorrectly touching forcewake of all domains, following an engine reset.
It is still a
Instead of using local string names that we will have to keep
maintaining, use the engine->name directly.
Suggested-by: Michal Wajdeczko
Signed-off-by: Michel Thierry
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_gpu_error.c | 23 ++-
1 file changed, 10 inserti
On 09/01/18 12:46, Chris Wilson wrote:
Quoting Michal Wajdeczko (2018-01-09 20:39:09)
On Tue, 09 Jan 2018 20:33:55 +0100, Michel Thierry
wrote:
Instead of using local string names that we will have to keep
maintaining, use the engine->name directly.
Suggested-by: Michal Wajdeczko
Sig
On 09/01/18 13:37, Michel Thierry wrote:
On 09/01/18 12:46, Chris Wilson wrote:
Quoting Michal Wajdeczko (2018-01-09 20:39:09)
On Tue, 09 Jan 2018 20:33:55 +0100, Michel Thierry
wrote:
Instead of using local string names that we will have to keep
maintaining, use the engine->name direc
Instead of using local string names that we will have to keep
maintaining, use the engine->name directly.
v2: Better invalid engine_id handling, capture_bo will not be able know
the engine_id and end up with -1 (Michal).
Suggested-by: Michal Wajdeczko
Signed-off-by: Michel Thierry
Cc: Mic
rmat) instead of PAGE_SIZE (Chris)
- s/BITS_44_TO_47/HIGHBITS (Chris)
- Right formatting, this time for real
Fixes: b03ec3d67ab8 ("drm/i915: There is only one fault register from GEN8
onwards")
Signed-off-by: Oscar Mateo
Cc: Michel Thierry
Cc: Chris Wilson
Michel, can you double
On 1/9/2018 5:21 PM, Michel Thierry wrote:
Instead of using local string names that we will have to keep
maintaining, use the engine->name directly.
v2: Better invalid engine_id handling, capture_bo will not be able know
the engine_id and end up with -1 (Michal).
Hi,
Fi.CI.IGT didn'
On 1/15/2018 9:15 AM, Tvrtko Ursulin wrote:
On 10/01/2018 01:21, Michel Thierry wrote:
Instead of using local string names that we will have to keep
maintaining, use the engine->name directly.
v2: Better invalid engine_id handling, capture_bo will not be able know
the engine_id and end
eck stats") and therefore
the test was incorrectly failing.
v2:
- Add the commit that changed the behaviour in the Driver to the
commit message (Michel)
Cc: Michel Thierry
Cc: Arkadiusz Hiler
Cc: Chris Wilson
Signed-off-by: Antonio Argenziano
Ping.
---
tests/ge
rrectly failing.
v2:
- Add the commit that changed the behaviour in the Driver to the
commit message. (Michel)
v3:
- Reuse get_reset_count instead of implementing a new function.
(Michel)
Cc: Michel Thierry
Cc: Arkadiusz Hiler
Cc: Chris Wilson
Signed-off-by
On 17/01/18 07:15, Chris Wilson wrote:
Quoting Michel Thierry (2018-01-16 18:33:32)
On 1/15/2018 9:15 AM, Tvrtko Ursulin wrote:
On 10/01/2018 01:21, Michel Thierry wrote:
Instead of using local string names that we will have to keep
maintaining, use the engine->name directly.
v2: Bet
state to use the new naming
scheme. This of course means we need to teach aubinator_error_decode how
to map both sets of ring names onto its register maps.
Signed-off-by: Chris Wilson
Cc: Michel Thierry
Cc: Michal Wajdeczko
Cc: Tvrtko Ursulin
Cc: Lionel Landwerlin
Cc: Kenneth Graunke
: Tvrtko Ursulin
Cc: Michel Thierry
---
drivers/gpu/drm/i915/intel_engine_cs.c | 3 ++-
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index d572b18d39eb
Newer platforms may have subtle offset changes, which will increase the
number of defines, so it is probably better to start moving them to its
own header file. Also move the macros used while setting the reg state.
Signed-off-by: Michel Thierry
Cc: Michal Wajdeczko
Cc: Lucas De Marchi
On 1/22/2018 12:14 PM, Chris Wilson wrote:
Quoting Michel Thierry (2018-01-22 20:06:32)
Newer platforms may have subtle offset changes, which will increase the
number of defines, so it is probably better to start moving them to its
own header file. Also move the macros used while setting the
intel_guc_reg.h (Chris)
Signed-off-by: Michel Thierry
Cc: Michal Wajdeczko
Cc: Lucas De Marchi
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c | 50 +--
drivers/gpu/drm/i915/intel_lrc_reg.h | 78
2 files changed, 79 insertions(+), 49
On 22/01/18 13:28, Michal Wajdeczko wrote:
On Mon, 22 Jan 2018 21:56:36 +0100, Lucas De Marchi
wrote:
On Mon, Jan 22, 2018 at 12:32:57PM -0800, Michel Thierry wrote:
Newer platforms may have subtle offset changes, which will increase the
number of defines, so it is probably better to start
intel_guc_reg.h (Chris)
v3: License notice shenanigans.
Signed-off-by: Michel Thierry
Cc: Michal Wajdeczko
Cc: Lucas De Marchi
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c | 50 +--
drivers/gpu/drm/i915/intel_lrc_reg.h | 57
2
On 1/22/2018 4:31 PM, Lucas De Marchi wrote:
So for this file what I understand is that it should be:
// SPDX-License-Identifier: MIT
// Copyright (C) 2014-2018 Intel Corporation
So be it.
___
Intel-gfx mailing list
Intel-gfx@lists.fr
Cc: Michel Thierry
Cc: Michal Wajdeczko
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
---
Please check the register definition. I know the save-inhibit bit used
to exist, I don't know if it is BIT(1) in RING_CONTEXT_CONTROL -- it
feels like it should be, and the numbers indicate that it does
some
intel_guc_reg.h (Chris)
v3: License notice shenanigans.
v4: Documentation/process/coding-style.rst is always right (Chris)
Signed-off-by: Michel Thierry
Cc: Michal Wajdeczko
Cc: Lucas De Marchi
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c | 50 +-
drivers/gpu/drm
intel_guc_reg.h (Chris)
v3: License notice shenanigans.
v4: Documentation/process/coding-style.rst is always right (Chris)
v5: Rebase.
Signed-off-by: Michel Thierry
Cc: Michal Wajdeczko
Cc: Lucas De Marchi
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c | 55
spaces preferred around that '+' (ctx:VxV)
So fix these issues before they are moved to a new header file.
Suggested-by: Chris Wilson
Signed-off-by: Michel Thierry
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c | 21 +
1 file changed, 13 insertions(+), 8 de
moved into the
submission process rather than the context image.
Suggested-by: Daniele Ceraolo Spurio
Signed-off-by: Chris Wilson
Cc: Michal Winiarski
Cc: Michel Thierry
Cc: Michal Wajdeczko
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_lrc.c
On 1/24/2018 12:46 PM, Chris Wilson wrote:
Quoting Chris Wilson (2018-01-24 09:44:45)
Quoting Michel Thierry (2018-01-24 01:24:25)
On 1/23/2018 1:04 PM, Chris Wilson wrote:
We only use the preempt context to inject an idle point into execlists.
We never need to reference its logical state, so
v2: rebased to intel_lr_indirect_ctx_offset
v3: rebase, move define to intel_lrc_reg.h
BSpec: 11740
Signed-off-by: Michel Thierry
Signed-off-by: Rodrigo Vivi
Signed-off-by: Michal Wajdeczko
Reviewed-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_lrc.c | 4
drivers/gpu/drm/i915
"This is not a true register bit This
bit will always be in clear state on a context save of this bit". Maybe
that's why didn't see any problems. But it doesn't hurt being paranoid.
Reviewed-by: Michel Thierry
Fixes: 517aaffe0c1b ("drm/i915/execlists: Inhib
said the preempt ctx could not be running at this
point.
Michal(s)/Tvrtko/Mika, any thoughts?
Signed-off-by: Chris Wilson
Cc: Michal Winiarski
Cc: Michel Thierry
Cc: Michal Wajdeczko
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c | 7 ---
1 file changed, 7
.
v9: fix rebase issue, change check in fw_domains_init from IS_GEN11
to GEN >= 11
v10: Generate is_genX_shadowed with a macro (Daniele)
Include gen11_fw_ranges in the selftest (Michel)
Cc: Michal Wajdeczko
Cc: Tvrtko Ursulin
Cc: Paulo Zanoni
Acked-by: Michel Thierry
Signed-off
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