On 4/29/2017 7:19 AM, Chris Wilson wrote:
On Thu, Apr 27, 2017 at 04:12:42PM -0700, Michel Thierry wrote:
From: Arun Siluvery
This is a preparatory patch which modifies error handler to do per engine
hang recovery. The actual patch which implements this sequence follows
later in the series
On 12/05/17 12:06, Chris Wilson wrote:
On Fri, May 12, 2017 at 06:55:35PM +0100, Chris Wilson wrote:
On Fri, May 12, 2017 at 06:49:09PM +0100, Chris Wilson wrote:
We have always excluded the top-page of the Global GTT to prevent
prefetching past the end of the address space. We have been lax
On 5/8/2017 11:31 AM, Michel Thierry wrote:
On 4/29/2017 7:19 AM, Chris Wilson wrote:
On Thu, Apr 27, 2017 at 04:12:42PM -0700, Michel Thierry wrote:
From: Arun Siluvery
...
+}
+
intel_prepare_reset(dev_priv);
set_bit(I915_RESET_HANDOFF, &dev_priv->gpu_erro
On 5/12/2017 2:09 PM, Chris Wilson wrote:
On Fri, May 12, 2017 at 01:55:11PM -0700, Michel Thierry wrote:
On 5/8/2017 11:31 AM, Michel Thierry wrote:
On 4/29/2017 7:19 AM, Chris Wilson wrote:
On Thu, Apr 27, 2017 at 04:12:42PM -0700, Michel Thierry wrote:
From: Arun Siluvery
ual purposing of reset-backoff. (Chris)
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Ian Lister
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.c | 13 +
drivers/gpu/drm/i915/i915_drv.h |
(Chris).
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.c | 58 ++-
drivers/gpu/drm/i915/i915_drv.h | 5 ++
drivers/gpu/drm/i915/i915_gem.c | 92
inside _prepare_engine, don't use
ECANCELED, remove unnecessary null checks (Chris).
Suggested-by: Chris Wilson
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.c | 21 +--
drivers/gpu/drm/i915/i915_drv.h | 6 --
drivers/gpu/drm/i915/i915_gem.c
On 5/15/2017 2:47 PM, Chris Wilson wrote:
On Mon, May 15, 2017 at 10:31:58PM +0100, Chris Wilson wrote:
On Mon, May 15, 2017 at 02:20:01PM -0700, Michel Thierry wrote:
@@ -2827,21 +2830,34 @@ int i915_gem_reset_prepare_engine(struct
intel_engine_cs *engine)
if (engine_stalled(engine
On 6/28/2018 7:15 AM, Michal Wajdeczko wrote:
We will add more init steps to misc phase and there is no need
to expose them separately for use in uc_init_misc function.
Signed-off-by: Michal Wajdeczko
Cc: Michel Thierry
---
drivers/gpu/drm/i915/intel_guc.c | 28
c/huc struct.
v2: don't forget to move wopcm_init - Michele
v3: fetch in init_misc phase - Michal
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
Reviewed-by: Michel Thierry #2
R-b stands for v3
---
drivers/gpu/drm/i915/i915_gem.c | 7 ---
drivers/gp
.411064] secondary_startup_64+0xa5/0xb0
The easiest remedy is to remove the defunct code.
Fixes: ff047a87cfac ("drm/i915/icl: Correctly clear lost ctx-switch interrupts
across reset for Gen11")
References: fd8526e50902 ("drm/i915/execlists: Trust the CSB")
If I read &qu
On 7/13/2018 1:18 PM, Chris Wilson wrote:
Check that reset_in_progress() is true when we process the reset.
Signed-off-by: Chris Wilson
Reviewed-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_lrc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c
On 7/13/2018 1:18 PM, Chris Wilson wrote:
Knowing the boundary of each subtest can be instrumental in digesting
the voluminous trace output and finding the critical piece of
information.
Signed-off-by: Chris Wilson
Reviewed-by: Michel Thierry
---
drivers/gpu/drm/i915/selftests
if (__tasklet_is_enabled(t))
I would add a comment that this catches any reset in progress as it
isn't as clear as using reset_in_progress (although you explain why in
the commit message).
Up-to you.
Reviewed-by: Michel Thierr
On 7/13/2018 1:41 PM, Chris Wilson wrote:
Quoting Chris Wilson (2018-07-13 21:35:28)
Inside intel_engine_is_idle(), we flush the tasklet to ensure that is
being run in a timely fashion (ksoftirqd has taught us to expect the
worst). However, if we are in the middle of reset, the HW may not yet be
re we haven't misprogrammed
any WQ or stage descriptor data. This will also help validating
upcoming changes in the db programming flow.
Cc: Michel Thierry
Cc: Michal Wajdeczko
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 1 +
drivers/gp
and use the GuC definitions for the firmware interface.
We also keep the same class id in the ctx descriptor to be able to have
the same values in the driver and firmware logs.
Signed-off-by: Michel Thierry
Signed-off-by: Rodrigo Vivi
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
On 14/03/18 13:04, Michal Wajdeczko wrote:
We try to keep all HuC related code in dedicated file.
There is no need to peek HuC register directly during
handling getparam ioctl.
Signed-off-by: Michal Wajdeczko
Cc: Michel Thierry
Cc: Rodrigo Vivi
Cc: Anusha Srivatsa
---
drivers/gpu/drm/i915
On 14/03/18 15:23, Michal Wajdeczko wrote:
On Wed, 14 Mar 2018 21:17:29 +0100, Michel Thierry
wrote:
On 14/03/18 13:04, Michal Wajdeczko wrote:
We try to keep all HuC related code in dedicated file.
There is no need to peek HuC register directly during
handling getparam ioctl.
Signed-off
)
Suggested-by: Daniele Ceraolo Spurio
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Michel Thierry
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_irq.c | 80 +++--
drivers/gpu/drm/i915/i915_reg.h | 4 ++-
2 files changed
reset when userspace writes -1 into debugfs/i915_wedged.
I thought that was the desired behaviour...
Reported-by: Michał Winiarski
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Michał Winiarski
Please? It papers over the issue in gem_exec_capture...
-Chris
Reviewed-by: Michel Thierry
On 16/03/18 14:50, Chris Wilson wrote:
Not all callers want the GPU error to handled in the same way, so expose
a control parameter. In the first instance, some callers do not want the
heavyweight error capture so add a bit to request the state to be
captured and saved.
Signed-off-by: Chris Wils
i915_reset/i915_reset_engine so that we include the
reason for the reset in the dev_notice(), superseding the earlier option
to not print that notice.
Signed-off-by: Chris Wilson
Cc: Jeff McGee
Cc: Mika Kuoppala
Cc: Michel Thierry
---
drivers/gpu/drm/i915/i915_debugfs.c | 4
On 3/19/2018 5:44 PM, Chris Wilson wrote:
Quoting Michel Thierry (2018-03-20 00:39:35)
On 3/19/2018 5:18 PM, Chris Wilson wrote:
Not all callers want the GPU error to handled in the same way, so expose
a control parameter. In the first instance, some callers do not want the
heavyweight error
Probably lost while rebasing commit eacd8391f977 ("drm/i915/guc: Keep GuC
interrupts enabled when using GuC").
Not really needed since i915_gem_init_hw is called before uc_resume, but
it brings symmetry to uc_suspend.
Signed-off-by: Michel Thierry
Cc: Michał Winiarski
---
drivers/gp
t;.
Fixes: 14b730fcb8d9 ("drm/i915/tdr: Prepare error handler to accept mask of hung
engines")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Michel Thierry
Reviewed-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_hangcheck.c | 4 ++--
1 file changed, 2 insertions(+), 2 dele
eff McGee
Cc: Mika Kuoppala
Cc: Michel Thierry
Reviewed-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 +-
drivers/gpu/drm/i915/i915_drv.c | 17
drivers/gpu/drm/i915/i915_drv.h | 10 ++---
drivers/gpu/drm/i
nprocessed, hanging the GPU.
Fixes: 767a983ab255 ("drm/i915/execlists: Read the context-status HEAD from the
HWSP")
Signed-off-by: Chris Wilson
Cc: Michel Thierry
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c | 21 -
1 file changed,
7; or 'action'
instead of 'code' but that's personal preference (the archaic fw docs
use 'action code' for this field, is it why you decided to use code?).
Plus it isn't like we want to keep the same names, looking at
intel_guc_fwif.h vs the 'or
bited space after '~' (Michel)
update commit message (Daniele)
v3: rebase
Signed-off-by: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Daniele Ceraolo Spurio
Reviewed-by: Michel Thierry #2
The r-b stands for v3.
---
drivers/gpu/drm/i915/intel_guc.c| 3 +++
Wajdeczko
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Daniele Ceraolo Spurio
Reviewed-by: Michel Thierry #1
r-b still applies to v3.
---
drivers/gpu/drm/i915/intel_guc.c| 6 --
drivers/gpu/drm/i915/intel_guc.h| 18 ++
drivers/gpu/drm/i915/intel_guc_ct.c | 7
ted commit message
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Oscar Mateo
Reviewed-by: Michel Thierry #2
---
drivers/gpu/drm/i915/intel_guc.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gp
;handler' makes sense too.
Reviewed-by: Michel Thierry
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 9ce01e5..118db81 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -69,6 +69,7 @@ void intel_guc_in
or without that,
Reviewed-by: Michel Thierry
+ u32 fence,
+ u32 *status)
{
int err;
@@ -395,7 +402,7 @@ static int ctch_send(struct intel_guc *guc,
intel_guc_notify(guc);
- err = wait_for_response(desc, fence, statu
make placeholders
for actual response/request handlers.
v2: misc improvements (Michal)
v3: change response detection (Michal)
invalid status is protocol error (Michal)
v4: rebase
Signed-off-by: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm
will WARN if response from GuC does not
match caller expectation.
v2: fix timeout and checkpatch warnings (Michal)
Signed-off-by: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_ct.c | 137
: Michel Thierry
Acked-by: Oscar Mateo
---
drivers/gpu/drm/i915/intel_uc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 8dc6a9c..9c20b1b 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm
er (Michal)
v3: rebased
Signed-off-by: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/intel_guc_ct.c | 72 -
drivers/gpu/drm/i915/intel_guc_ct.h | 4 +++
2 files changed, 75 insertions(+), 1 deletio
communication, so some
code reuse is still possible.
Spoiler alert, some g2h messages (reset-engine and preemption afaik)
will send us more data, so just passing request->data[1] won't be enough
¯\_(ツ)_/¯
Signed-off-by: Michal Wajdeczko
Cc: Oscar Mateo
---
Reviewed-by: Michel Thierry
On 3/16/2018 1:28 PM, Daniele Ceraolo Spurio wrote:
On 16/03/18 05:14, Mika Kuoppala wrote:
From: Michel Thierry
The bits used to reset the different engines/domains have changed in
GEN11, this patch maps the reset engine mask bits with the new bits
in the reset control register.
v2: Use
of the scratch register used in MMIO based communication, so some
code reuse is still possible.
Signed-off-by: Michal Wajdeczko
Cc: Oscar Mateo
Reviewed-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_guc.c | 5 +
drivers/gpu/drm/i915/intel_guc.h | 1 +
drivers/gpu/drm/i915
er (Michal)
v3: rebased
v4: don't name it 'dispatch' (Michel) and fix checkpatch
add some documentation (Michal)
Signed-off-by: Michal Wajdeczko
Cc: Oscar Mateo
Cc: Michel Thierry
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm
On 3/26/2018 12:48 PM, Michal Wajdeczko wrote:
With this series we will be able to receive more data from the Guc.
New Guc firmwares will be required to actually use that feature.
v4: respin series after 1/2 year break
v5: updated after review comments
Michal Wajdeczko (12):
drm/i915/guc: Ad
communication, so some
code reuse is still possible.
v2: filter disabled messages (Daniele)
Signed-off-by: Michal Wajdeczko
Cc: Oscar Mateo
Reviewed-by: Michel Thierry #1
^ still applies for v2, but I would wait for Daniele's blessing
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm
From: Michal Wajdeczko
Stolen from...
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index c96360398072..53037b5eff22 100644
---
Probably lost while rebasing commit eacd8391f977 ("drm/i915/guc: Keep GuC
interrupts enabled when using GuC").
Not really needed since i915_gem_init_hw is called before uc_resume, but
it brings symmetry to uc_suspend.
Signed-off-by: Michel Thierry
Cc: Michał Winiarski
Reviewed-
It's not like it will magically appear or disappear ;)
Signed-off-by: Michel Thierry
Cc: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_ddi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index a6672a9
gen (pre-gen8) have been left as they
are only used in full device reset mode.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Michał Winiarski
CC: Michel Thierry
Cc: Jeff McGee
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_uncore.c | 31 ---
1 file
On 28/03/18 14:52, Chris Wilson wrote:
Quoting Michel Thierry (2018-03-28 22:47:55)
On 28/03/18 14:18, Chris Wilson wrote:
@@ -2094,7 +2095,7 @@ int intel_gpu_reset(struct drm_i915_private *dev_priv,
unsigned engine_mask)
int retry;
int ret;
- might_sleep
in
Reported-by: Michel Thierry
Cc: Michel Thierry
Thanks,
Reviewed-by: Michel Thierry
---
lib/igt_gt.h | 12 +++-
tests/perf_pmu.c | 30 ++
2 files changed, 17 insertions(+), 25 deletions(-)
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
ind
use correct class / instance limits (Michel)
v4: split engine/other handling
Suggested-by: Daniele Ceraolo Spurio
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Michel Thierry
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_irq.c | 102
; GEN11_GT_DW_IRQ(bank))
+ gen11_gt_bank_handler(i915, bank);
+ }
+
+ spin_unlock(&i915->irq_lock);
}
static irqreturn_t gen11_irq_handler(int irq, void *arg)
But it does what is supposed to do s
I would think of (intel_ringbuffer.h, were other
instances exist) would be also odd since this is not really an engine.
Maybe someone else can think of a better place,
Reviewed-by: Michel Thierry
#define MAX_ENGINE_INSTANCE3
/* PCI config space */
diff --git a/drivers/gp
If it's true that it's the same as Gen10,
Reviewed-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_debugfs.c | 10 +-
drivers/gpu/drm/i915/intel_pm.c | 10 --
2 files changed, 9 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
{
Are the ones in igt_handle_error() still needed?
hangcheck.stalled = true;
hangcheck.seqno = intel_engine_get_seqno(engine);
Because igt_handle_error is sending a real request.
(I think the only ones remaining in the selftest should be in
fake_hangcheck).
Reviewed-by: Miche
On 4/6/2018 2:30 PM, Chris Wilson wrote:
Quoting Michel Thierry (2018-04-06 22:23:21)
And I thought we believed in presumption of innocence...
On 4/6/2018 2:00 PM, Chris Wilson wrote:
If we are resetting just one engine, we know it has stalled. So we can
pass the stalled parameter directly to
rious snooping by reset, be it whole-device or per-engine. \o/
The only real issue now is that this makes it crystal clear that we
don't actually do any testing of hangcheck per se in
drv_selftest/live_hangcheck, merely of resets!
Don't tell anyone
Signed-off-by: Chris Wilson
Cc: Michel Th
On 5/16/2018 4:39 PM, Paulo Zanoni wrote:
Em Qui, 2018-05-10 às 14:59 -0700, Oscar Mateo escreveu:
Stop reading some now deprecated interrupt registers in both
debugfs and error state. Instead, read the new equivalents in the
Gen11 interrupt repartitioning scheme.
Note that the equivalent to th
Hi,
On 5/29/2018 12:16 PM, Lionel Landwerlin wrote:
We want to be able to modify other context images from the kernel
context in a following commit. To be able to do this we need to map
the context image into the kernel context's ppgtt.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i9
5))
+ return MAX_GUC_CONTEXT_HW_ID;
+
+ return MAX_CONTEXT_HW_ID;
+}
+
What was the reason of moving this out of i915_gem_context.c? I don't
see any other user.
Everything else looks good to me so
Reviewed-by: Michel Thierry
int i915_gem_contexts_set_dynamic_sse
r Gen11), but not me.
Reviewed-by: Michel Thierry
Signed-off-by: Lionel Landwerlin
Fixes: 1de401c08fa805 ("drm/i915/perf: enable perf support on ICL")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104252
BSpec: 1237
Testcase: igt/perf/gen8-unprivileged-single-ctx-counters
---
stop trying to do any further preemption on this engine.
References:
https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_2235/shard-apl4/igt@gem_exec_sched...@preempt-bsd.html
Signed-off-by: Chris Wilson
Cc: Michal Wajdeczko
Cc: Michel Thierry
Cc: Michałt Winiarski
Reviewed-by: Michel T
On 6/1/2018 10:08 AM, Lionel Landwerlin wrote:
On 01/06/18 16:18, Chris Wilson wrote:
Quoting Lionel Landwerlin (2018-06-01 10:52:15)
+ /*
+* The LRCA is aligned to a page. As a result the
+* lower 12bits are always at 0 and
'm already writing this...
Reviewed-by: Michel Thierry
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
d-single-ctx-counters
Acked-by: Chris Wilson
Please ping Michel for an r-b confirmation on using the lrca for the guc
ctx_id.
-Chris
Got the information from Michel initially ;)
Will wait for his Rb on the last version.
Both patches,
Reviewed-by: Michel Thierry
_
fic_ctx_id had this
problem.
Signed-off-by: Michel Thierry
Cc: Lionel Landwerlin
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_perf.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index a6c8d61add0c..c15c7
On 06/04/2018 11:58 AM, Patchwork wrote:
== Series Details ==
Series: drm/i915/perf: fix gen11 engine class shift
URL : https://patchwork.freedesktop.org/series/44216/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4277 -> Patchwork_9187 =
== Summary - FAILURE ==
Serio
On 6/4/2018 2:03 PM, Chris Wilson wrote:
Quoting Michel Thierry (2018-06-04 19:17:24)
Use the correct engine class shift value while storing the ctx hw id.
Fixes the copy+paste error from commit 61d5676b5561 ("drm/i915/perf: fix
ctx_id read with GuC & ICL").
Apologies for not sp
The upper 32 bits of the lrc_desc (bits 52-32 to be precise) are the
context hw id in GEN8-10, so use them and have one less thing to
maintain in the unlikely case we change the descriptor sw fields.
Signed-off-by: Michel Thierry
Cc: Lionel Landwerlin
Cc: Chris Wilson
---
drivers/gpu/drm/i915
fic_ctx_id had this
problem.
v2: Just use the upper 32 bits of lrc_desc (Chris)
Fixes: 61d5676b5561 ("drm/i915/perf: fix ctx_id read with GuC & ICL")
Signed-off-by: Michel Thierry
Cc: Lionel Landwerlin
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_perf.c | 7 +--
1 fil
On 6/4/2018 4:11 PM, Lionel Landwerlin wrote:
On 04/06/18 22:40, Michel Thierry wrote:
The upper 32 bits of the lrc_desc (bits 52-32 to be precise) are the
context hw id in GEN8-10, so use them and have one less thing to
maintain in the unlikely case we change the descriptor sw fields.
Signed
The upper 32 bits of the lrc_desc (bits 52-32 to be precise) are the
context hw id in GEN8-10, so use them and have one less thing to
maintain in the unlikely case we change the descriptor sw fields.
v2: If we use the lrc_desc, we must apply the ctx_id_mask too (Lionel)
Signed-off-by: Michel
fic_ctx_id had this
problem.
v2: Just use the upper 32 bits of lrc_desc (Chris)
v3: If we use the lrc_desc, we must apply the ctx_id_mask too (Lionel)
Fixes: 61d5676b5561 ("drm/i915/perf: fix ctx_id read with GuC & ICL")
Signed-off-by: Michel Thierry
Cc: Lionel Landwerlin
Cc: Chris
On 06/15/2018 07:10 AM, Michal Wajdeczko wrote:
While debugging we may want to examine params passed to GuC.
Print them all if config I915_DEBUG_GUC is enabled.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
---
drivers/gpu/drm/i915/intel_guc.c | 5 +
1
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
---
drivers/gpu/drm/i915/intel_guc.c | 7 ++-
drivers/gpu/drm/i915/intel_huc.c | 8
drivers/gpu/drm/i915/intel_huc.h | 6 ++
drivers/gpu/drm/i915/intel_uc.c | 37 -
4 files changed, 40 inserti
don't forget to move wopcm_init - Michele
I'm not Italian ;)
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem.c | 8
drivers/gpu/drm/i915/intel_guc.c | 7 ++-
al Wajdeczko
Cc: Michał Winiarski
Cc: Michel Thierry
---
drivers/gpu/drm/i915/intel_engine_cs.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 32bf3a408d46..d3264bd6e9dc 100644
--- a/drivers/gpu/drm/i915
: Peter Antoine
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
b/drivers/gpu/drm/i915/intel_guc_loader.c
index f2b88c7..413af19 100644
--- a/drivers/gpu/drm/i915
On 6/23/2016 11:01 AM, Peter Antoine wrote:
Daniel,
Is this suggestion acceptable? I don't want to waste time and effort
writing code that is not going to be accepted?
Peter.
Reuse I915_GETPARAM and do more-less what Chris did for i915.enable_gvt? [1]
[1]
https://cgit.freedesktop.org/drm-
On 11/24/2015 1:33 PM, Wang, Zhi A wrote:
Hi Gurus:
I’m wondering what’s the right approach to deal with the context switch
reason: element_switch? According to b-spec, one ELSP submission may
include two elements, when one element is finished, HW will move to
process next element, the previous
On 11/25/2015 1:00 PM, Wang, Zhi A wrote:
Another question about EXECLIST is: Can a preemption happen between element
switch?
I know this is beyond the scope of i915 a little. I'm just curious if it's
possible.
Let's say we have context A B C
At first, we submit context A B in one ELSP write
white spaces.
v11: Keep alphabetical order in Makefile and gitignore; update error code
returned while trying to pin above the max vm size (EINVAL); test attempt
to pin above 4GB without the support 48b flag.
Cc: Michel Thierry
Cc: Tvrtko Ursulin
Signed-off-by: Vinay Belgaumkar
Reviewed-by
drm.h| 12 --
6 files changed, 111 insertions(+), 25 deletions(-)
Extra support from the other patch aside, v6 already had rb from Akash
and this one,
Reviewed-by: Michel Thierry
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index a81c766..52b8289 1
On 12/9/2015 12:34 PM, Tvrtko Ursulin wrote:
On 09/12/15 10:51, Chris Wilson wrote:
On Wed, Dec 09, 2015 at 10:30:41AM +, Tvrtko Ursulin wrote:
On 08/12/15 18:49, Michel Thierry wrote:
On 12/8/2015 11:55 AM, Thomas Daniel wrote:
From: Chris Wilson
Userspace can pass in an offset that
i915 validates that requested offset is in canonical form, so tests need
to convert the offsets as required.
Also add test to verify non-canonical 48-bit address will be rejected.
Signed-off-by: Michel Thierry
---
tests/gem_softpin.c | 66
the lower addresses available for
objects which really need to be there.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
b/drivers/gpu/drm
that userspace is using addresses
in canonical form in case of softpin.
v2: Whitespace fixup, gen8_canonical_addr description (Chris, Ville)
v3: Rebase on top of softpin, fix a hole in relocate_entry,
s/expect/require (Chris)
Cc: Chris Wilson
Cc: Michel Thierry
Cc: Ville Syrjälä
Signed-o
On 12/11/2015 6:57 PM, Daniel Vetter wrote:
On Fri, Dec 11, 2015 at 02:49:52PM +, Chris Wilson wrote:
On Fri, Dec 11, 2015 at 02:34:13PM +, Michel Thierry wrote:
We detected if objects should be moved to the lower parts when 48-bit
support flag was not set, but not the other way around
The cache line offset for the Indirect CS context (0x21C8) varies from gen
to gen.
Cc: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_lrc.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b
The cache line offset for the Indirect CS context (0x21C8) varies from gen
to gen.
v2: Move it into a function (Arun), use MISSING_CASE (Chris)
Cc: Arun Siluvery
Cc: Chris Wilson
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_lrc.c | 26 --
1 file
The cache line offset for the Indirect CS context (0x21C8) varies from gen
to gen.
v2: Move it into a function (Arun), use MISSING_CASE (Chris)
v3: Rebased (catched by ci bat)
Cc: Arun Siluvery
Cc: Chris Wilson
Reviewed-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm
The cache line offset for the Indirect CS context (0x21C8) varies from gen
to gen.
v2: Move it into a function (Arun), use MISSING_CASE (Chris)
v3: Rebased (catched by ci bat)
Cc: Arun Siluvery
Cc: Chris Wilson
Reviewed-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm
On Tue, Feb 23, 2016 at 11:21 AM, Patchwork
wrote:
== Series Details ==
Series: drm/i915/gen9: Set value of Indirect Context Offset based on gen
version (rev4)
URL : https://patchwork.freedesktop.org/series/3629/
State : warning
== Summary ==
Series 3629v4 drm/i915/gen9: Set value of Indire
The driver should only set the "RS context enable" bit in the context
image if we plan to use the resource streamer.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/int
The driver should only set the "RS context enable" bit in the context
image if we plan to use the resource streamer.
Reviewed-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/d
On Thu, Feb 25, 2016 at 11:10 AM, Patchwork
wrote:
== Series Details ==
Series: drm/i915/lrc: Only set RS ctx enable in ctx control reg if there
is a RS (rev2)
URL : https://patchwork.freedesktop.org/series/3725/
State : failure
== Summary ==
Series 3725v2 drm/i915/lrc: Only set RS ctx enab
On 3/9/2016 11:31 AM, akash.g...@intel.com wrote:
From: Akash Goel
This patch provides the testcase to exercise the TRTT hardware.
...
--- /dev/null
+++ b/tests/gem_trtt.c
@@ -0,0 +1,498 @@
...
+
+/* gen8_canonical_addr
+ * Used to convert any address into canonical form, i.e. [63:48] == [
Instead of being hidden in sanitize_enable_ppgtt.
It also seems to be the place to do so nowadays.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/i915_gem_gtt.c | 7 +++
drivers/gpu/drm/i915/i915_pci.c | 11 +++
3 files
As it already says in the comment block...
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 88e70fe..13835b9 100644
--- a/drivers/gpu
On 05/12/16 18:15, Patchwork wrote:
== Series Details ==
Series: series starting with [1/2] drm/i915: Advertise ppgtt support type in
platform definition
URL : https://patchwork.freedesktop.org/series/16403/
State : warning
== Summary ==
Series 16403v1 Series without cover letter
https://pa
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