Prigent
Signed-off-by: Peter Antoine
Signed-off-by: Michel Thierry
Reviewed-by: Rodrigo Vivi
Signed-off-by: Rodrigo Vivi
Reviewed-by: Michel Thierry (v3)
---
drivers/gpu/drm/i915/intel_guc_loader.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915
x27;t there already.
On this race the second patch got merged first so the first one
broke i915 compilation. Thanks to Michel this was found quickly.
Cc: Michel Thierry
Cc: Daniel Vetter
Cc: Hans de Goede
Suggested-by: Michel Thierry
Fixes: 82daca297506 ("drm/i915: Add "panel o
}
- elsp_write(desc, elsp);
+ elsp_write(desc, engine->execlists.elsp);
}
execlists_clear_active(&engine->execlists, EXECLISTS_ACTIVE_HWACK);
}
---
Anyway,
Reviewed-by: Michel Thierry
@@ -496,8 +495,6 @@ static void inject_preempt_context(st
the commit that changed the behaviour,
...when not root. This is no longer true in the driver since commit
4c9c0d09741d ("drm/i915: Fix retrieval of hangcheck stats") and therefore...
the test was incorrectly failing.
Cc: Michel Thierry
Cc: Arkadiusz Hiler
Signed-off-by
by: Michał Winiarski
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Michal Wajdeczko
Cc: Michel Thierry
---
drivers/gpu/drm/i915/intel_guc_submission.c | 151
drivers/gpu/drm/i915/selftests/intel_guc.c | 110 +---
2 files changed, 88 insertions(+), 1
---
Reviewed-by: Michel Thierry
drivers/gpu/drm/i915/intel_guc_submission.c | 33 ++---
1 file changed, 11 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c
b/drivers/gpu/drm/i915/intel_guc_submission.c
index c74e78b6ba41..488110602e7e
at module load/unload though.
Signed-off-by: Michał Winiarski
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Michal Wajdeczko
---
Reviewed-by: Michal Wajdeczko
Reviewed-by: Michel Thierry
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop
stall before we could issue a reset,
so let the engine continue on without a reset. If the engine is truly
stuck, we will back soon enough with the next reset attempt.
Signed-off-by: Chris Wilson
Cc: Michel Thierry
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.c | 14 +++---
1 file
On 12/15/2017 4:16 PM, Chris Wilson wrote:
Quoting Michel Thierry (2017-12-16 00:02:47)
Hi,
On 12/15/2017 3:52 PM, Chris Wilson wrote:
At the beginning of a reset, we disable the submission method and find
the stuck request. We expect to find a stuck request for we have
declared the engine
before we could issue a reset,
so let the engine continue on without a reset. If the engine is truly
stuck, we will back soon enough with the next reset attempt.
v2: Remove the stale debug message.
Signed-off-by: Chris Wilson
Cc: Michel Thierry
Cc: Mika Kuoppala
---
Reviewed-by: Michel Thierry
5_add_request(rq, false);
+ }
}
i915_gem_restore_fences(dev_priv);
It shouldn't hurt and if it fixes something,
Reviewed-by: Michel Thierry
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
i915_reset_engine() by loading it with requests.
Fixes: f6ba181ada55 ("drm/i915: Skip an engine reset if it recovered before our
preparations")
Signed-off-by: Chris Wilson
Cc: Michel Thierry
Cc: Mika Kuoppala
Reviewed-by: Michel Thierry
And all these subtests passed with and without
port->context_id, count,
rq->global_seqno);
GEM_BUG_ON(count == 0);
if (--count == 0) {
--
2.15.1
Reviewed-by: Michel Thierry
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
the style currently in upstream
Suggested-by: Michel Thierry
Signed-off-by: Rodrigo Vivi
Signed-off-by: Michel Thierry
Signed-off-by: Oscar Mateo
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_irq.c | 6 ++--
drivers/gpu/drm/i915/intel_drv.h
t.
v3: Fix double definition of PCI IDs, update IDs according to bspec
and keep them in the same order and rebase (Lucas)
Cc: Michel Thierry
Signed-off-by: Paulo Zanoni
Signed-off-by: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
intel/intel_bufmgr_gem.c | 2 ++
intel/intel_chipset
: Chris Wilson
Cc: Mika Kuoppala
Cc: Michał Winiarski
Cc: Michel Thierry
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
-by-one from including the ppHSWP in with the register
state.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Michał Winiarski
Cc: Michel Thierry
Cc: Tvrtko Ursulin
Reviewed-by: Michel Thierry
Does it need a 'Fixes:' tag or has a bugzilla reference?
---
drivers/gp
On 4/27/2018 1:35 PM, Chris Wilson wrote:
Quoting Michel Thierry (2018-04-27 21:27:46)
On 4/27/2018 1:24 PM, Chris Wilson wrote:
Previously, we just reset the ring register in the context image such
that we could skip over the broken batch and emit the closing
breadcrumb. However, on resume
This is identical to v2.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Michał Winiarski
Cc: Michel Thierry
Cc: Tvrtko Ursulin
Reviewed-by: Michel Thierry #v2
---
drivers/gpu/drm/i915/intel_lrc.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff
still be there when CONFIG_DRM_I915_DEBUG_GEM=n, right?
(btw, until late last year, there where more users of that function).
Reported-by: Matthias Kaehlcke
Signed-off-by: Chris Wilson
Cc: Daniele Ceraolo Spurio
Cc: Michał Winiarski
Cc: Michal Wajdeczko
Cc: Michel Thierry
---
drivers/gpu/drm
On 05/02/2018 02:11 AM, Chris Wilson wrote:
Quoting Michel Thierry (2018-05-01 15:21:53)
On 5/1/2018 12:52 AM, Chris Wilson wrote:
As our early doorbell is split between early allocation and a late setup
after we have a channel to the GuC, it may happen due to a lapse of
programmer judgement
breadcrumb; switching
contexts at this point is futile so don't.
Signed-off-by: Chris Wilson
Cc: Michał Winiarski
Cc: Michel Thierry
Cc: Joonas Lahtinen
Reviewed-by: Tvrtko Ursulin
---
Michał and Michel,
please take a look and see if you can think of any objections.
No objections,
915/cnl: Use mmio access to context status
buffer")
Suggested-by: Mika Kuoppala
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Michał Winiarski
Cc: Rafael Antognolli
Cc: Michel Thierry
Cc: Timo Aaltonen
Tested-by: Timo Aaltonen
Acked-by: Michel
c: Mika Kuoppala
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: Michał Winiarski
Cc: Rafael Antognolli
Cc: Michel Thierry
Cc: Timo Aaltonen
Tested-by: Timo Aaltonen
Acked-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_engine_cs.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/
first
module on boot. This is due to the removal of the distinct global
timeline, and its separate lock class. So instead mark up the expected
nesting. An alternative would be to define a separate lock class for the
engine, but since we only expect to have a single point of nesting, we
can avoid havi
lines") but the issue was
masked in CI by the earlier lockdep spam.
Fixes: a89d1f921c15 ("drm/i915: Split i915_gem_timeline into individual
timelines")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Joonas Lahtinen
Cc: Michel Thierry
Double checked that mock_ring
Factor in clear values wherever required while updating destination
min/max.
References: HSDES#160184
Signed-off-by: Michel Thierry
Cc: mesa-...@lists.freedesktop.org
Cc: Mika Kuoppala
Cc: Oscar Mateo
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915
On 5/11/2018 5:43 AM, Mika Kuoppala wrote:
Chris Wilson writes:
Quoting Mika Kuoppala (2018-05-11 10:56:49)
Michel Thierry writes:
Factor in clear values wherever required while updating destination
min/max.
References: HSDES#160184
Signed-off-by: Michel Thierry
Cc: mesa
Factor in clear values wherever required while updating destination
min/max.
References: HSDES#160184
Signed-off-by: Michel Thierry
Cc: mesa-...@lists.freedesktop.org
Cc: Mika Kuoppala
Cc: Oscar Mateo
Reviewed-by: Mika Kuoppala
Signed-off-by: Chris Wilson
Link:
https
On 5/15/2018 10:13 AM, Jani Nikula wrote:
On Mon, 14 May 2018, Michel Thierry wrote:
Factor in clear values wherever required while updating destination
min/max.
Hi Michel, please elaborate what the intention here is.
Hi Jani, isn't the intention of all the workarounds to preven
On 5/15/2018 11:17 AM, Jani Nikula wrote:
On Tue, 15 May 2018, Michel Thierry wrote:
On 5/15/2018 10:13 AM, Jani Nikula wrote:
On Mon, 14 May 2018, Michel Thierry wrote:
Factor in clear values wherever required while updating destination
min/max.
Hi Michel, please elaborate what the
On 12/04/17 08:58, Chris Wilson wrote:
On Wed, Apr 12, 2017 at 04:48:42PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Looks like intel_guc_reset had the ability to sleep under the
uncore spinlock since forever but it wasn't detected until the
recent changes annotated the wait for registe
On 13/04/17 17:16, Daniele Ceraolo Spurio wrote:
On 24/03/17 18:30, Michel Thierry wrote:
From: Arun Siluvery
GuC expects a list of registers from the driver which are saved/restored
during engine reset. The type of value to be saved is controlled by
flags. We provide a minimal set of
On 14/04/17 09:05, Daniele Ceraolo Spurio wrote:
On 24/03/17 18:30, Michel Thierry wrote:
Final enablement patch for GPU hang detection using watchdog timeout.
Using the gem_context_setparam ioctl, users can specify the desired
timeout value in microseconds, and the driver will do the
On 17/04/17 14:28, Daniele Ceraolo Spurio wrote:
On 24/03/17 18:30, Michel Thierry wrote:
For watchdog / media reset, the firmware must know the address of the
shared
data page (the first page of the default context).
This information should be in DWORD 9 of the GUC_CTL structure.
Signed
mutex-less reset engine.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Ian Lister
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.c | 15 +++
drivers/gpu/drm/i915/i915_drv.h | 6 ++
dr
It has been replaced by I915_RESET_BACKOFF / I915_RESET_HANDOFF.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b5c81de102e8
engine count in i915_engine_info too (Chris).
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_debugfs.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b
.
v2: s/engine_reset/reset_engine/ (Chris)
Define count as unsigned int (Tvrtko)
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 8
drivers/gpu/drm
From: Arun Siluvery
In preparation for engine reset work update this parameter to handle more
than one type of reset. Default at the moment is still full gpu reset.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915
As all other functions related to resetting engines are using
reset_engine.
v2: remove _request_ and use start/cancel instead (Chris)
Cc: Chris Wilson
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_uncore.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff
unnecessary. To
avoid this we check if the engine is already prepared, if so we just exit
from that point.
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_uncore.c | 9 +++--
1 file changed, 7 insertions
and _retire_requests (Chris).
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.c | 76 --
drivers/gpu/drm/i915/i915_drv.h | 12 +++-
drivers/gpu/drm
/tdr: Export per-engine reset count info to debugfs
drm/i915/tdr: Enable Engine reset and recovery support
drm/i915/guc: Provide register list to be saved/restored during engine
reset
Daniele Ceraolo Spurio (1):
drm/i915/guc: fix mmio whitelist mmio_start offset and add reminder
Michel Thi
ecause why not?).
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 29 +
drivers/gpu/drm/i915/i915_gem_context.c | 102
drivers/gpu/drm/i915/intel_lrc.c| 5 +-
in
/resume/reset (Daniele).
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_guc_submission.c | 21 ++---
drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +-
drivers/gpu/drm/i915/intel_guc_loader.c| 11 +++
drivers/gpu
,
provide a simple debugfs entry to see the number of times media reset
has happened.
v2: Remove unnecessary struct_mutex, _get_dirty_page and kmap_atomic;
use READ_ONCE. (Chris)
Cc: Chris Wilson
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_debugfs.c | 22
Save the watchdog threshold (in us) as part of the engine state.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 11 +++
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h
of
combined start_watchdog, bb_start and stop_watchdog to avoid any error
after emitting bb_start.
Signed-off-by: Tomas Elf
Signed-off-by: Ian Lister
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_context.h | 4 ++
drivers/gpu/drm/i915/intel_lrc.c
r, be extra paranoid and save whitelisted registers (Daniele).
Cc: Daniele Ceraolo Spurio
Signed-off-by: Arun Siluvery
Signed-off-by: Jeff McGee
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_guc_submission.c | 60 +-
1 file changed, 58 insertions(
Check that we can reset specific engines, also check the fallback to
full reset if something didn't work.
v2: rebase.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 147 +++
1 file changed, 147 insertions(+)
diff --git a/driver
it
is deemed useful, it can be extended to report each engine separately.
v2: s/engine_reset/reset_engine/, use union in uapi to not break compatibility.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_context.c | 14 +++---
include
requests are pending so after resetting
a engine, pending workloads/requests are resubmitted again.
v2: s/i915_guc_request_engine_reset/i915_guc_reset_engine/ to match the
non-guc funtion names.
Signed-off-by: Arun Siluvery
Signed-off-by: Jeff McGee
Signed-off-by: Michel Thierry
---
drivers/gpu
s. From GEN9 onwards, the stop counter bit is
the same for all engines.
Signed-off-by: Tomas Elf
Signed-off-by: Ian Lister
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++
drivers/gpu/drm/i915/i915_irq.c | 13 ++-
From: Arun Siluvery
This feature is made available only from Gen8, for previous gen devices
driver uses legacy full gpu reset.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_params.c | 4
Winiarski (v2)
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_guc_submission.c | 11 +--
drivers/gpu/drm/i915/intel_guc_fwif.h | 1 -
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gp
On 18/04/17 14:20, Chris Wilson wrote:
On Tue, Apr 18, 2017 at 01:23:32PM -0700, Michel Thierry wrote:
@@ -1329,10 +1331,29 @@ static int gen8_emit_bb_start(struct
drm_i915_gem_request *req,
req->ctx->ppgtt->pd_dirty_rings &=
~intel_engine_fla
On 18/04/17 14:40, Chris Wilson wrote:
On Tue, Apr 18, 2017 at 01:23:19PM -0700, Michel Thierry wrote:
From: Arun Siluvery
This is a preparatory patch which modifies error handler to do per engine
hang recovery. The actual patch which implements this sequence follows
later in the series
On 18/04/17 16:06, Chris Wilson wrote:
On Tue, Apr 18, 2017 at 02:36:14PM -0700, Michel Thierry wrote:
On 18/04/17 14:20, Chris Wilson wrote:
On Tue, Apr 18, 2017 at 01:23:32PM -0700, Michel Thierry wrote:
@@ -1329,10 +1331,29 @@ static int gen8_emit_bb_start(struct
drm_i915_gem_request
On 18/04/17 17:26, Daniele Ceraolo Spurio wrote:
On 18/04/17 13:23, Michel Thierry wrote:
From: Arun Siluvery
GuC expects a list of registers from the driver which are saved/restored
during engine reset. The type of value to be saved is controlled by
flags. We provide a minimal set of
On 19/04/17 03:20, Chris Wilson wrote:
On Tue, Apr 18, 2017 at 01:23:31PM -0700, Michel Thierry wrote:
*** General ***
Watchdog timeout (or "media engine reset") is a feature that allows
userland applications to enable hang detection on individual batch buffers.
The detection
On 19/04/17 10:51, Chris Wilson wrote:
On Wed, Apr 19, 2017 at 10:11:37AM -0700, Michel Thierry wrote:
On 19/04/17 03:20, Chris Wilson wrote:
On Tue, Apr 18, 2017 at 01:23:31PM -0700, Michel Thierry wrote:
*** General ***
Watchdog timeout (or "media engine reset") is a fe
ned-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h| 3 ++
drivers/gpu/drm/i915/i915_guc_submission.c | 68 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 65 +++-
3 files changed, 114 insertions(+), 22 deletions(-)
di
On 19/04/17 03:27, Chris Wilson wrote:
On Tue, Apr 18, 2017 at 01:23:29PM -0700, Michel Thierry wrote:
This patch adds per engine reset and recovery (TDR) support when GuC is
used to submit workloads to GPU.
In the case of i915 directly submission to ELSP, driver manages hang
detection
On 18/04/17 13:23, Michel Thierry wrote:
Final enablement patch for GPU hang detection using watchdog timeout.
Using the gem_context_setparam ioctl, users can specify the desired
timeout value in microseconds, and the driver will do the conversion to
'timestamps'.
The recommend
On 20/04/17 01:52, Chris Wilson wrote:
On Wed, Apr 19, 2017 at 06:09:00PM -0700, Michel Thierry wrote:
This patch is missing:
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index c1013af0b910..a8bdea43a217 100644
--- a/drivers/gpu/drm/i915
On 20/04/17 09:39, Daniele Ceraolo Spurio wrote:
On 20/04/17 04:33, Joonas Lahtinen wrote:
On ke, 2017-04-19 at 11:35 -0700, Michel Thierry wrote:
From: Arun Siluvery
GuC expects a list of registers from the driver which are saved/restored
during engine reset. The type of value to be
On 19/04/17 03:49, Chris Wilson wrote:
On Tue, Apr 18, 2017 at 01:23:20PM -0700, Michel Thierry wrote:
From: Arun Siluvery
This change implements support for per-engine reset as an initial, less
intrusive hang recovery option to be attempted before falling back to the
legacy full GPU reset
On 20/04/17 10:29, Michel Thierry wrote:
On 20/04/17 09:39, Daniele Ceraolo Spurio wrote:
On 20/04/17 04:33, Joonas Lahtinen wrote:
On ke, 2017-04-19 at 11:35 -0700, Michel Thierry wrote:
From: Arun Siluvery
GuC expects a list of registers from the driver which are
saved/restored
On 21/04/17 13:21, Chris Wilson wrote:
On Fri, Apr 21, 2017 at 01:10:37PM -0700, Daniele Ceraolo Spurio wrote:
On 21/04/17 13:07, Michel Thierry wrote:
On 20/04/17 10:29, Michel Thierry wrote:
On 20/04/17 09:39, Daniele Ceraolo Spurio wrote:
On 20/04/17 04:33, Joonas Lahtinen wrote
On 20/04/17 17:17, Michel Thierry wrote:
Hmm. Interesting. This relies on i915_gem_retire_requests() (i.e.
struct_mutex) to skip replaying innocent requests, but here we should be
asserting that we do have the hung request.
i.e.
request = i915_gem_find_active_request(engine);
if (!request
restarted.
Thanks, one less patch for me (and I arrived late to the party, I see
it's already merged).
Suggested-by: Michel Thierry
Signed-off-by: Chris Wilson
Cc: Michel Thierry
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc.c | 29 --
On 12/04/17 09:22, Michel Thierry wrote:
On 12/04/17 08:58, Chris Wilson wrote:
On Wed, Apr 12, 2017 at 04:48:42PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Looks like intel_guc_reset had the ability to sleep under the
uncore spinlock since forever but it wasn't detected unti
On 27/04/17 11:20, Tvrtko Ursulin wrote:
On 27/04/2017 19:14, Michel Thierry wrote:
On 12/04/17 09:22, Michel Thierry wrote:
On 12/04/17 08:58, Chris Wilson wrote:
On Wed, Apr 12, 2017 at 04:48:42PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Looks like intel_guc_reset had the
r reset (s/I915_GUC_REG_WRITE/WA_REG_WR_GUC_RESTORE).
Cc: Daniele Ceraolo Spurio
Signed-off-by: Arun Siluvery
Signed-off-by: Jeff McGee
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h| 3 ++
drivers/gpu/drm/i915/i915_guc_submiss
unnecessary. To
avoid this we check if the engine is already prepared, if so we just exit
from that point.
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/intel_uncore.c | 9 +++--
1 file changed, 7 insertions
mutex-less reset engine.
v7: Pass reset_engine mask as a function parameter, and iterate over the
engine mask for reset_engine. (Chris)
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Ian Lister
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
driver
engine count in i915_engine_info too (Chris).
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_debugfs.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b
Spurio (1):
drm/i915/guc: fix mmio whitelist mmio_start offset and add reminder
Michel Thierry (11):
drm/i915: Cancel reset-engine if we couldn't find an active request
drm/i915: Add engine reset count in get-reset-stats ioctl
drm/i915/selftests: reset engine self tests
drm/i915/g
it
is deemed useful, it can be extended to report each engine separately.
v2: s/engine_reset/reset_engine/, use union in uapi to not break compatibility.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_context.c | 14 +++---
include
intel_guc_reset sounds more like the microcontroller is the one performing
a reset, while in this case is the opposite. intel_reset_guc not only
makes it clearer, it follows the other intel_reset functions available.
Cc: Tvrtko Ursulin
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915
ister
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++
drivers/gpu/drm/i915/i915_irq.c | 12 +-
drivers/gpu/drm/i915/i915_reg.h | 6 +++
drivers/gpu/drm/i915/intel_hangcheck.c | 13 +--
drivers/gpu/drm/i915/int
and _retire_requests (Chris).
v7: Remove leftovers from v5, i.e. no need to disable irq, hold
forcewake or wakeup the handoff bit (Chris).
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.c
regardless of submission mode. (Chris)
Signed-off-by: Arun Siluvery
Signed-off-by: Jeff McGee
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.c| 42 +-
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/i915_guc_submission.c
Save the watchdog threshold (in us) as part of the engine state.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 11 +++
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h
.
v2: s/engine_reset/reset_engine/ (Chris)
Define count as unsigned int (Tvrtko)
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.c | 3 ++-
drivers/gpu/drm/i915/i915_drv.h | 10 ++
drivers
,
provide a simple debugfs entry to see the number of times media reset
has happened.
v2: Remove unnecessary struct_mutex, _get_dirty_page and kmap_atomic;
use READ_ONCE. (Chris)
Cc: Chris Wilson
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_debugfs.c | 22
Check that we can reset specific engines, also check the fallback to
full reset if something didn't work.
v2: rebase.
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 147 +++
1 file changed, 147 insertions(+)
diff --git a/driver
Winiarski (v2)
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_guc_submission.c | 11 +--
drivers/gpu/drm/i915/intel_guc_fwif.h | 1 -
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/drivers/gp
From: Arun Siluvery
In preparation for engine reset work update this parameter to handle more
than one type of reset. Default at the moment is still full gpu reset.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915
ecause why not?).
v4: Checking if watchdog is available should be the first thing to
do, instead of giving false hopes to abi users; remove unnecessary & in
set_watchdog; ignore args->size in getparam.
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
From: Arun Siluvery
This feature is made available only from Gen8, for previous gen devices
driver uses legacy full gpu reset.
Cc: Chris Wilson
Cc: Mika Kuoppala
Signed-off-by: Tomas Elf
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_params.c | 4
in
emit_stop_watchdog. (Chris)
Cc: Chris Wilson
Signed-off-by: Tomas Elf
Signed-off-by: Ian Lister
Signed-off-by: Arun Siluvery
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_gem_context.h | 4 ++
drivers/gpu/drm/i915/intel_lrc.c| 85 +++--
drivers/gpu/drm/i
-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_drv.c | 37 +
drivers/gpu/drm/i915/i915_drv.h | 6 --
drivers/gpu/drm/i915/i915_gem.c | 37 -
3 files changed, 57 insertions(+), 23 deletions(-)
diff --git a/drivers
/resume/reset (Daniele).
Cc: Chris Wilson
Cc: Daniele Ceraolo Spurio
Reviewed-by: Daniele Ceraolo Spurio
Signed-off-by: Michel Thierry
---
drivers/gpu/drm/i915/i915_guc_submission.c | 21 ++---
drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +-
drivers/gpu/drm/i915
On 4/27/2017 4:58 PM, Chris Wilson wrote:
On Thu, Apr 27, 2017 at 04:12:52PM -0700, Michel Thierry wrote:
+#define WA_REG_WR_GUC_RESTORE(addr, val) do { \
+ const int r = guc_wa_add(dev_priv, (addr), (val)); \
+ if (r) \
+ return r
On 4/27/2017 4:50 PM, Chris Wilson wrote:
-static void engine_retire_requests(struct intel_engine_cs *engine)
+void engine_retire_requests(struct intel_engine_cs *engine)
Fortunately stray chunk. I was about to scream.
This chunk has been there for quite a long time, at least since v4...
t
On 28/04/17 00:40, Tvrtko Ursulin wrote:
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -46,9 +46,9 @@ static int __intel_uc_reset_hw(struct
drm_i915_private *dev_priv)
int ret;
u32 guc_status;
-ret = intel_guc_reset(dev_priv);
+ret = intel_reset
On 29/04/17 07:21, Chris Wilson wrote:
On Thu, Apr 27, 2017 at 04:12:44PM -0700, Michel Thierry wrote:
From: Mika Kuoppala
To perform engine reset we first disable engine to capture its state. This
is done by issuing a reset request. Because we are reusing existing
infrastructure, again
On 27/04/17 16:50, Chris Wilson wrote:
On Thu, Apr 27, 2017 at 04:12:43PM -0700, Michel Thierry wrote:
From: Arun Siluvery
This change implements support for per-engine reset as an initial, less
intrusive hang recovery option to be attempted before falling back to the
legacy full GPU reset
1 - 100 of 1163 matches
Mail list logo
