On 2022-03-08 10:58 a.m., Lucas De Marchi wrote:
On Tue, Feb 22, 2022 at 08:24:31PM +0100, Thomas Hellström (Intel) wrote:
Hi, Michael,
On 2/22/22 18:26, Michael Cheng wrote:
This patch removes logic for wbinvd_on_all_cpus and brings in
drm_cache.h. This header has the logic that outputs a
+Daniel for additional feedback!
On 2022-03-14 4:06 p.m., Michael Cheng wrote:
On 2022-03-08 10:58 a.m., Lucas De Marchi wrote:
On Tue, Feb 22, 2022 at 08:24:31PM +0100, Thomas Hellström (Intel)
wrote:
Hi, Michael,
On 2/22/22 18:26, Michael Cheng wrote:
This patch removes logic for
://patchwork.freedesktop.org/patch/475752/?series=1&rev=5
Michael Cheng (4):
i915/gem: drop wbinvd_on_all_cpus usage
Revert "drm/i915/gem: Almagamate clflushes on suspend"
i915/gem: Revert i915_gem_freeze to previous logic
drm/i915/gt: Revert ggtt_resume to previous logic
As we are making i915 more architecture-neutral, lets revert this commit
to the previous logic [1] to avoid using wbinvd_on_all_cpus.
[1]. ac05a22cd07a ("drm/i915/gem: Almagamate clflushes on suspend")
Suggested-by: Lucas De Marchi
Signed-off-by: Michael Cheng
---
drivers/gpu/dr
This patch reverts i915_gem_freeze to previous logic [1] to avoid using
wbinvd_on_all_cpus.
[1]. https://patchwork.freedesktop.org/patch/415007/?series=86058&rev=2
Suggested-by: Lucas De Marchi
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 15 ++
h the pages for when the GPU wants to read
from main memory.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/gem/i915_gem_dma
To avoid having to call wbinvd_on_all_cpus, revert i915_ggtt_resume and
i915_ggtt_resume_vm to previous logic [1].
[1]. 64b95df91f44 drm/i915: Assume exclusive access to objects inside resume
Suggested-by: Lucas De Marchi
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/intel_ggtt.c
On 2022-03-21 3:30 a.m., Tvrtko Ursulin wrote:
On 19/03/2022 19:42, Michael Cheng wrote:
Previous concern with using drm_clflush_sg was that we don't know
what the
sg_table is pointing to, thus the usage of wbinvd_on_all_cpus to flush
everything at once to avoid paranoia.
And now we
On 2022-03-21 10:28 a.m., Tvrtko Ursulin wrote:
On 21/03/2022 16:31, Michael Cheng wrote:
On 2022-03-21 3:30 a.m., Tvrtko Ursulin wrote:
On 19/03/2022 19:42, Michael Cheng wrote:
Previous concern with using drm_clflush_sg was that we don't know
what the
sg_table is pointing to, thu
On 2022-03-21 10:28 a.m., Tvrtko Ursulin wrote:
On 21/03/2022 16:31, Michael Cheng wrote:
On 2022-03-21 3:30 a.m., Tvrtko Ursulin wrote:
On 19/03/2022 19:42, Michael Cheng wrote:
Previous concern with using drm_clflush_sg was that we don't know
what the
sg_table is pointing to, thu
On 2022-03-21 4:07 a.m., Thomas Hellström wrote:
On 3/21/22 11:30, Tvrtko Ursulin wrote:
On 19/03/2022 19:42, Michael Cheng wrote:
Previous concern with using drm_clflush_sg was that we don't know
what the
sg_table is pointing to, thus the usage of wbinvd_on_all_cpus to flush
everythi
Use drm_clflush_virt_range instead of directly invoking clflush. This
will prevent compiler errors when building for non-x86 architectures.
v2(Michael Cheng): Remove extra clflush
v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range
takes care of it.
v4
additional clflush/clflushopt to use drm_clflush*.
(Michael Cheng)
v3: Drop invalidate_csb_entries and directly invoke drm_clflush_virt_ran
v4: Remove extra memory barriers
v5: s/cache_clflush_range/drm_clflush_virt_range
v6: Fix up "Drop invalidate_csb_entries" to use correct parame
Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function call, and prevent complier errors when
building for non-x86 architectures.
v2(Michael Cheng): Drop invalidate_csb_entries function and directly
invoke drm_clflush_virt_range
Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine.h | 13 -
1 file changed, 4 insertions(+), 9
Replace all occurrence of cache_clflush_range with drm_clflush_virt_range.
This will prevent compile errors on non-x86 platforms.
Signed-off-by: Michael Cheng
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++--
drivers/gpu/drm/i915/gt
Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.
v2(Michael Cheng): Use sizeof(*addr) instead of sizeof(addr) to get the
actual size of the page. Thanks to Matt Roper for
pointing
h the pages for when the GPU wants to read
from main memory.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/gem/i915_gem_dma
.
[1]. https://lists.freedesktop.org/archives/dri-devel/2021-November/330928.html
[2]. https://patchwork.freedesktop.org/patch/475752/?series=1&rev=5
v2 (Michael Cheng) : Per feedback from Thomas and Tvrtko, this series should be
split into two parts; First par
h the pages for when the GPU wants to read
from main memory.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c
b/drivers/gpu/drm/i915/gem/i915_gem_dma
.
[1]. https://lists.freedesktop.org/archives/dri-devel/2021-November/330928.html
[2]. https://patchwork.freedesktop.org/patch/475752/?series=1&rev=5
v2 (Michael Cheng) : Per feedback from Thomas and Tvrtko, this series should be
split into two parts; First par
This series is to introduce new macros generic to i915 for checking 0 and 1
bits,
instead on relying on whats defined by the mmu, since it could be different
or non-exisitent between different platforms.
Michael Cheng (1):
drm/i915: Introduce new macros for i915 PTE
drivers/gpu/drm/i915/gt
patch introduces two new macros,
I915_PAGE_PRESENT and I915_PAGE_RW, to check for bits 0 and 1 and, to
replace all occurances of _PAGE_RW and _PAGE_PRESENT within i915.
Looking at the bspecs for pre gen 12 and gen 12, bit 0 and 1 are the
same throughout the generations.
Signed-off-by: Michael
From: Michael Cheng
Certain functions within i915 uses macros that are defined for
specific architectures by the mmu, such as _PAGE_RW and _PAGE_PRESENT
(Some architectures don't even have these macros defined, like ARM64).
Instead of re-using bits defined for the CPU, we should use
From: Michael Cheng
This series is to introduce new macros generic to i915 for checking 0 and 1
bits,
instead on relying on whats defined by the mmu, since it could be different
or non-exisitent between different platforms.
Michael Cheng (1):
drm/i915: Introduce new macros for i915 PTE
This series is to introduce new macros generic to i915 for checking 0 and 1
bits,
instead on relying on whats defined by the mmu, since it could be different
or non-exisitent between different platforms.
v2: Corrected sender's email.
v3: Corrected spelling error.
Michael Cheng (1):
drm
patch introduces two new macros,
I915_PAGE_PRESENT and I915_PAGE_RW, to check for bits 0 and 1 and, to
replace all occurrences of _PAGE_RW and _PAGE_PRESENT within i915.
Looking at the bspecs for pre gen 12 and gen 12, bit 0 and 1 are the
same throughout the generations.
Signed-off-by: Michael
patch introduces two new macros,
I915_PAGE_PRESENT and I915_PAGE_RW, to check for bits 0 and 1 and, to
replace all occurrences of _PAGE_RW and _PAGE_PRESENT within i915.
Looking at the bspecs for pre gen 12 and gen 12, bit 0 and 1 are the
same throughout the generations.
Signed-off-by: Michael
Removes BYT_PTE_WRITEABLE and replace it with
I915_PAGE_RW.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.h | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu
other macros that are checking 0 and 1 bits.
Thanks to Lucas De Marchi for suggesting these cleanups.
Michael Cheng (3):
drm/i915: Introduce new macros for i915 PTE
drm/i915: Clean up GEN6 page valid macros
drm/i915: Clean up BYT_PTE_WRITEABLE
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
dr
GEN6_PTE_VALID and GEN6_PDE_VALID both checks the 0 bit
to see weather the mapping of the corresponding graphics
memory page is valid. Instead of having two different
macros doing the same thing, this patch replaces the macros
with I915_PAGE_PRESENT.
Signed-off-by: Michael Cheng
---
drivers/gpu
vision out.
On 2021-11-12 5:31 p.m., Matt Roper wrote:
On Fri, Nov 12, 2021 at 05:28:09PM -0800, Matt Roper wrote:
On Wed, Nov 10, 2021 at 04:45:47PM -0800, Michael Cheng wrote:
Certain functions within i915 uses macros that are defined for
specific architectures by the mmu, such as _P
leading to compilation
errors.
v2: Corrected sender's email.
v3: Corrected spelling error.
v4: Clean up a few other macros that are checking 0 and 1 bits.
v5: Instead of introducing new macros for checking 0 and 1 bits,
re-use already defined macros for i915.
Michael Cheng (1):
-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 +++---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
drivers/gpu/drm/i915/gvt/gtt.c | 12 ++--
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
b/drivers/gpu/drm
other macros that are checking 0 and 1 bits.
Thanks to Lucas De Marchi for suggesting these cleanups.
v5: Remove changes to GEN6_PTE_VALID/GEN6_PDE_VALID and BYT_PTE_WRITEABLE.
Those macros checks for 32bit PTEs, and our new macro is checking for 64bit.
Michael Cheng (1):
drm/i915: Introduce new m
patch introduces two new 64 bit macros,
I915_PAGE_PRESENT and I915_PAGE_RW, to check for bits 0 and 1 and, to
replace all occurrences of _PAGE_RW and _PAGE_PRESENT within i915.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 +++---
drivers/gpu/drm/i915/gt/intel_ggtt.c
other macros that are checking 0 and 1 bits.
Thanks to Lucas De Marchi for suggesting these cleanups.
v5: Remove changes to GEN6_PTE_VALID/GEN6_PDE_VALID and BYT_PTE_WRITEABLE.
Those macros checks for 32bit PTEs, and our new macro is checking for 64bit.
Michael Cheng (1):
drm/i915: Introduce new m
patch introduces two new 64 bit macros,
I915_PAGE_PRESENT and I915_PAGE_RW, to check for bits 0 and 1 and, to
replace all occurrences of _PAGE_RW and _PAGE_PRESENT within i915.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 6 +++---
drivers/gpu/drm/i915/gt/intel_ggtt.c
acros that are checking 0 and 1 bits.
Thanks to Lucas De Marchi for suggesting these cleanups.
v5: Remove changes to GEN6_PTE_VALID/GEN6_PDE_VALID and BYT_PTE_WRITEABLE.
Those macros checks for 32bit PTEs, and our new macro is checking for 64bit.
v6: Use GEN8_* instead of I915_*
Michael Che
patch introduces two new 64 bit macros,
GEN8_PAGE_PRESENT and GEN8_PAGE_RW, to check for bits 0 and 1 and, to
replace all occurrences of _PAGE_RW and _PAGE_PRESENT within i915.
v2(Michael Cheng): Use GEN8_ instead of I915_
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c
This series moves the logic for wbvind_on_all_cpus to drm_cache. The logic
changes a little here, if platform is not x86 then we throw out a warning
for when wbvind_on_all_cpus is being called.
v2(Michael Cheng): Move and redo logic for wbvind_on_all_cpus. Also
add
Add logic for wbvind_on_all_cpus for non-x86 platforms.
v2(Michael Cheng): Change logic to if platform is not x86, then
we add pr_warn for calling wbvind_on_all_cpus.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/drm_cache.c | 2 --
include/drm/drm_cache.h | 6
Add drm_cache.h to additionals files that calls wbinvd_on_all_cpus and
remove un-needed header files.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff
drm_cache.h now handles calls to wbinvd_on_all_cpus.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index
This series moves the logic for wbvind_on_all_cpus to drm_cache. The logic
changes a little here, if platform is not x86 then we throw out a warning
for when wbvind_on_all_cpus is being called.
v2(Michael Cheng): Move and redo logic for wbvind_on_all_cpus. Also
add drm_cache.h
Add logic for wbvind_on_all_cpus for non-x86 platforms.
v2(Michael Cheng): Change logic to if platform is not x86, then
we add pr_warn for calling wbvind_on_all_cpus.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/drm_cache.c | 2 --
include/drm/drm_cache.h | 6
This patch removes logic for wbinvd_on_all_cpus and brings in
drm_cache.h. This header has the logic that outputs a warning
when wbinvd_on_all_cpus when its being used on a non-x86 platform.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 7 +--
1 file changed, 1
Add drm_cache.h to additionals files that calls wbinvd_on_all_cpus and
remove un-needed header files. This will prevent compile errors when
building for non-x86 platforms, as well as output a warning when
wbinvd_on_all_cpus is being called incorrectly.
Signed-off-by: Michael Cheng
---
drivers
Thanks for letting me know! I will try for a different solution.
On 2022-02-22 11:24 a.m., Thomas Hellström (Intel) wrote:
Hi, Michael,
On 2/22/22 18:26, Michael Cheng wrote:
This patch removes logic for wbinvd_on_all_cpus and brings in
drm_cache.h. This header has the logic that outputs a
additional clflush/clflushopt to use drm_clflush*.
(Michael Cheng)
v3: Drop invalidate_csb_entries and directly invoke drm_clflush_virt_ran
v4: Remove extra memory barriers
v5: s/cache_clflush_range/drm_clflush_virt_range
v6: Fix up "Drop invalidate_csb_entries" to use correct parame
Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc
performs a flush by first performing a clean, follow by an invalidation
operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the
dcache. Thanks Tvrtko for the suggestion.
v3
Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine.h | 13 -
1 file changed, 4 insertions(+), 9
Use drm_clflush_virt_range instead of directly invoking clflush. This
will prevent compiler errors when building for non-x86 architectures.
v2(Michael Cheng): Remove extra clflush
v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range
takes care of it.
v4
Replace all occurrence of cache_clflush_range with drm_clflush_virt_range.
This will prevent compile errors on non-x86 platforms.
Signed-off-by: Michael Cheng
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++--
drivers/gpu/drm/i915/gt
Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function call, and prevent complier errors when
building for non-x86 architectures.
v2(Michael Cheng): Drop invalidate_csb_entries function and directly
invoke drm_clflush_virt_range
Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.
v2(Michael Cheng): Use sizeof(*addr) instead of sizeof(addr) to get the
actual size of the page. Thanks to Matt Roper for
pointing
Use drm_clflush_virt_range instead of directly invoking clflush. This
will prevent compiler errors when building for non-x86 architectures.
v2(Michael Cheng): Remove extra clflush
v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range
takes care of it.
v4
Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine.h | 13 -
1 file changed, 4 insertions(+), 9
Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function call, and prevent complier errors when
building for non-x86 architectures.
v2(Michael Cheng): Drop invalidate_csb_entries function and directly
invoke drm_clflush_virt_range
Add arm64 support for drm_clflush_virt_range. caches_clean_inval_pou
performs a flush by first performing a clean, follow by an invalidation
operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the
dcache. Thanks Tvrtko for the suggestion.
v3
Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.
v2(Michael Cheng): Use sizeof(*addr) instead of sizeof(addr) to get the
actual size of the page. Thanks to Matt Roper for
pointing
Replace all occurrence of cache_clflush_range with drm_clflush_virt_range.
This will prevent compile errors on non-x86 platforms.
Signed-off-by: Michael Cheng
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++--
drivers/gpu/drm/i915/gt
additional clflush/clflushopt to use drm_clflush*.
(Michael Cheng)
v3: Drop invalidate_csb_entries and directly invoke drm_clflush_virt_ran
v4: Remove extra memory barriers
v5: s/cache_clflush_range/drm_clflush_virt_range
v6: Fix up "Drop invalidate_csb_entries" to use correct parame
build the kernel
per specific architecture, but please correct if I am wrong,as I am still
trying to understand how things works!
Michael Cheng
On 2022-02-25 8:28 a.m., Tvrtko Ursulin wrote:
On 25/02/2022 03:24, Michael Cheng wrote:
Add arm64 support for drm_clflush_virt_range. caches_clean_inval_pou
-25 9:33 a.m., Tvrtko Ursulin wrote:
On 25/02/2022 16:52, Michael Cheng wrote:
Hi Tvrtko,
It seems without cacheflush.h being included, when I build for arm64
or x86, it stills pulls in cacheflush.h:
./.drm_cache.o.cmd:838: include/linux/cacheflush.h \
./.drm_cache.o.cmd:839: arch/x86/include
On 25/02/2022 17:40, Michael Cheng wrote:
Ah, thanks for pointing that out, when I do include it though, it
causes a few warning other systems such as h8300 and s390.
Errors look like? I haven't heard that kernel code is not allowed to
include something from linux/ on some arch yet.
., Robin Murphy wrote:
[ +arm64 maintainers for their awareness, which would have been a good
thing to do from the start ]
On 2022-02-25 03:24, Michael Cheng wrote:
Add arm64 support for drm_clflush_virt_range. caches_clean_inval_pou
performs a flush by first performing a clean, follow by
:
On 2022-02-25 19:27, Michael Cheng wrote:
Hi Robin,
[ +arm64 maintainers for their awareness, which would have been a
good thing to do from the start ]
* Thanks for adding the arm64 maintainer and sorry I didn't rope them
in sooner.
Why does i915 need to ensure the CPU's in
Ah Thanks for the great feedback!
@Lucas or @Matt, could you please chime in?
Michael Cheng
On 2022-03-02 11:10 a.m., Robin Murphy wrote:
On 2022-03-02 15:55, Michael Cheng wrote:
Thanks for the feedback Robin!
Sorry my choices of word weren't that great, but what I meant is to
under
Re-work invalidate_csb_entries to use drm_clflush_virt_range. This will
prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a
Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/intel_engine.h | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a
This patch series re-work a few i915 functions to use drm_clflush_virt_range
instead of calling clflush directly. This will prevent errors when building
for non-x86 architectures.
Michael Cheng (2):
drm/i915/gt: Re-work intel_write_status_page
drm/i915/gt: Re-work invalidate_csb_entries
Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers
Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/intel_engine.h | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a
additional clflush/clflushopt to use drm_clflush*.
(Michael Cheng)
Michael Cheng (4):
drm/i915/gt: Re-work intel_write_status_page
drm/i915/gt: Re-work invalidate_csb_entries
drm/i915/gt: Re-work reset_csb
drm/i915/: Re-work clflush_write32
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
Re-work invalidate_csb_entries to use drm_clflush_virt_range. This will
prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a
Use drm_clflush_virt_range instead of directly invoking clflush. This
will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm
future when needed.
On 2022-01-31 6:55 a.m., Tvrtko Ursulin wrote:
On 28/01/2022 22:10, Michael Cheng wrote:
Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gem
Ah, thanks for the clarification! While discussion goes on about the
route you suggested, could we land these patches (after addressing the
reviews) to unblock compiling i915 on arm?
On 2022-02-01 1:25 a.m., Tvrtko Ursulin wrote:
On 31/01/2022 17:02, Michael Cheng wrote:
Hey Tvrtko,
Are
unately I don't have enough expertise to comfortable answer this
question. Maybe someone else can chime in here? Lucas? Matt?
On 2022-02-01 8:32 a.m., Tvrtko Ursulin wrote:
On 01/02/2022 15:41, Michael Cheng wrote:
Ah, thanks for the clarification! While discussion goes on about the
route
Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/intel_engine.h | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a
Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function call, and prevent complier errors when
building for non-x86 architectures.
v2(Michael Cheng): Drop invalidate_csb_entries function and directly
invoke drm_clflush_virt_range
Use drm_clflush_virt_range instead of directly invoking clflush. This
will prevent compiler errors when building for non-x86 architectures.
v2(Michael Cheng): Remove extra clflush
v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range
takes care of it.
Signed
additional clflush/clflushopt to use drm_clflush*.
(Michael Cheng)
v3: Drop invalidate_csb_entries and directly invoke drm_clflush_virt_ran
v4: Remove extra memory barriers
Michael Cheng (4):
drm/i915/gt: Re-work intel_write_status_page
drm/i915/gt: Drop invalidate_csb_entries
drm/i915/gt: Re
Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers
Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function call, and prevent complier errors when
building for non-x86 architectures.
v2(Michael Cheng): Drop invalidate_csb_entries function and directly
invoke drm_clflush_virt_range
additional clflush/clflushopt to use drm_clflush*.
(Michael Cheng)
v3: Drop invalidate_csb_entries and directly invoke drm_clflush_virt_ran
v4: Remove extra memory barriers
v5: s/cache_clflush_range/drm_clflush_virt_range
Michael Cheng (5):
drm/i915/gt: Re-work intel_write_status_page
drm/i915
Use drm_clflush_virt_range instead of directly invoking clflush. This
will prevent compiler errors when building for non-x86 architectures.
v2(Michael Cheng): Remove extra clflush
v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range
takes care of it.
Signed
Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/intel_engine.h | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a
Replace all occurance of cache_clflush_range with
drm_clflush_virt_range. This will prevent compile errors on non-x86
platforms.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++--
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2
Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers
Ah, sorry thanks for pointing that out. We did discuss previously. I
will go ahead and change it.
On 2022-02-07 3:57 a.m., Tvrtko Ursulin wrote:
On 04/02/2022 16:37, Michael Cheng wrote:
Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function
.
v2: s/PAGE_SIZE/sizeof(value) for Re-work intel_write_status_page and added
more patches to convert additional clflush/clflushopt to use drm_clflush*.
(Michael Cheng
Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/intel_engine.h | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a
Use drm_clflush_virt_range instead of directly invoking clflush. This
will prevent compiler errors when building for non-x86 architectures.
v2(Michael Cheng): Remove extra clflush
v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range
takes care of it.
Signed
Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers
Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function call, and prevent complier errors when
building for non-x86 architectures.
v2(Michael Cheng): Drop invalidate_csb_entries function and directly
invoke drm_clflush_virt_range
Replace all occurance of cache_clflush_range with
drm_clflush_virt_range. This will prevent compile errors on non-x86
platforms.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++--
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2
Use flush_tlb_kernel_range when invoking drm_clflush_virt_range on
arm64 platforms. Using flush_tlb_kernel_range will:
1. Make sure prior page-table updates have been completed
2. Invalidate the TLB
3. Check if the TLB invalidation has been completed
Signed-off-by: Michael Cheng
---
drivers
Ah, thanks for asking this question. It seems like I was not thinking
correctly. We are trying to flush dcache lines within this function and
not the tlb.
On 2022-02-08 2:20 a.m., Tvrtko Ursulin wrote:
On 07/02/2022 20:11, Michael Cheng wrote:
Use flush_tlb_kernel_range when invoking
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