On 11/26/2014 7:07 PM, Damien Lespiau wrote:
Hardware team updated the recommended translation values for DP/eDP 1.3.
This should help with some stability and HBR2 issues.
Signed-off-by: Damien Lespiau
---
drivers/gpu/drm/i915/intel_ddi.c | 12 ++--
1 file changed, 6 insertions(+), 6
On 12/11/2014 5:58 PM, sonika.jin...@intel.com wrote:
From: Sonika Jindal
We were incorreectly bypassing the flush everytime which led to fifo
underrun when more than one plane is enabled.
Signed-off-by: Sonika Jindal
---
drivers/gpu/drm/i915/intel_pm.c |3 +--
1 file changed, 1 insert
On 9/22/2014 11:47 PM, Paulo Zanoni wrote:
2014-09-04 8:27 GMT-03:00 Damien Lespiau:
From: Satheeshakrishna M
This patch defines the necessary SKL registers for implementing the
new clocking mechanism.
v2: Addressed review comments by Damien
- Added code comment
- Introduced
On 9/23/2014 1:42 AM, Paulo Zanoni wrote:
2014-09-04 8:27 GMT-03:00 Damien Lespiau:
From: Satheeshakrishna M
v2: Fixup compilation due to the removal of the intel_ddi_dpll_id enum.
And add a fixme about the abuse of pipe_config here.
v3: Rebase on top of the hsw_ddi_clock_get() rename (Damien)
On 9/23/2014 12:49 AM, Paulo Zanoni wrote:
2014-09-04 8:27 GMT-03:00 Damien Lespiau:
From: Satheeshakrishna M
Determine programmed cd clock for SKL.
v2: Fix the LCPLL1 enable warning logic
v3: Rebase over the hsw pll rework.
v4: Rebase on top of the per-platform split (Damien)
Signed-off-by
On 9/23/2014 1:54 AM, Paulo Zanoni wrote:
2014-09-04 8:27 GMT-03:00 Damien Lespiau:
From: Satheeshakrishna M
Modify the implementation to query DPLL attached to a SKL port.
v2: Rebase on top of the run-time PM on DPMS series (Damien)
Signed-off-by: Satheeshakrishna M
Signed-off-by: Damien Les
On 9/23/2014 11:35 PM, Paulo Zanoni wrote:
2014-09-04 8:27 GMT-03:00 Damien Lespiau:
From: Satheeshakrishna M
This patch implements SKL DPLL programming that includes:
- DPLL allocation
- wide range PLL calculation and programming
- DP link rate programming
-
On 9/23/2014 7:58 PM, Paulo Zanoni wrote:
2014-09-04 8:27 GMT-03:00 Damien Lespiau:
From: Satheeshakrishna M
On skylake, DPLL 1, 2 and 3 can be used for DP and HDMI. The shared dpll
framework allows us to share those DPLLs among DDIs when possible.
The most tricky part is to provide a DPLL sta
On 9/23/2014 8:37 PM, Paulo Zanoni wrote:
2014-09-04 8:27 GMT-03:00 Damien Lespiau:
From: Satheeshakrishna M
DPLL0 is not part of the shared PLL infrastructure. We'll use on for
eDP and rely on what the BIOS does for now.
Signed-off-by: Satheeshakrishna M
Signed-off-by: Damien Lespiau
---
dr
