rom spec contains many more entries. The new table for Ice Lake will
be added by other patches, this only reformats the table.
While at it also fix the indentation.
Signed-off-by: Lucas De Marchi
That is much cleaner.
Reviewed-by: Tomasz Lis
-Tomasz
---
drivers/gpu/drm/i915/intel_mocs.c |
On 2019-01-22 06:12, Lucas De Marchi wrote:
Instead of initializing them to uncached, let's set them to PTE for
kernel tracking. While at it do some minor adjustments to comments and
coding style.
Signed-off-by: Lucas De Marchi
Reviewed-by: Tomasz Lis
One comment (with no expectations for c
treat that just as another
item and please source code formatting tools
Signed-off-by: Tomasz Lis
Suggested-by: Lucas De Marchi
Signed-off-by: Lucas De Marchi
Acked-by: Tomasz Lis
-Tomasz
---
drivers/gpu/drm/i915/intel_mocs.c | 57 ++-
1 file changed, 25
On 2019-01-22 06:12, Lucas De Marchi wrote:
Let's use a macro to make tables smaller and at the same time allow us
to add fields that apply to all entries in future.
For the sake of readability, I'm calling an exception on 80 chars limit.
Lines are aligned for easy comparison of the entry valu
ents about the meaning of undefined entries were removed
since they are overly verbose and copy-pasted in several functions: now
the definition is in the top only.
Signed-off-by: Lucas De Marchi
Reviewed-by: Tomasz Lis
-Tomasz
---
drivers/gpu/drm/i915/intel_m
; but that's
just a name, so:
Reviewed-by: Tomasz Lis
-Tomasz
---
drivers/gpu/drm/i915/intel_mocs.c | 27 ++-
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_mocs.c
b/drivers/gpu/drm/i915/intel_mocs.c
index af
On 2019-01-22 06:12, Lucas De Marchi wrote:
From: Tomasz Lis
The table has been unified across OSes to minimize virtualization overhead.
The MOCS table is now published as part of bspec, and versioned. Entries
are supposed to never be modified, but new ones can be added. Adding
entries incre
Only comment issues. Besides these:
Reviewed-by: Tomasz Lis
On 2019-04-11 10:44, Michal Wajdeczko wrote:
GuC stores some data in there, which might be stale after a reset.
Reinitialize whole ADS in case any part of it was corrupted during
previous GuC run.
Signed-off-by: Michal Wajdeczko
Cc
On 2018-12-14 12:10, Joonas Lahtinen wrote:
Quoting Tvrtko Ursulin (2018-12-10 17:40:34)
On 09/11/2018 17:18, Tomasz Lis wrote:
The patch adds support of preempt-to-idle requesting by setting a proper
bit within Execlist Control Register, and receiving preemption result from
Context Status Bu
On 2018-12-21 13:29, Tvrtko Ursulin wrote:
On 14/12/2018 18:20, Lucas De Marchi wrote:
From: Tomasz Lis
The table has been unified across OSes to minimize virtualization
overhead.
The MOCS table is now published as part of bspec, and versioned. Entries
are supposed to never be modified,
t;drm/i915/tgl: Define MOCS entries for Tigerlake")
Cc: Tomasz Lis
Cc: Lucas De Marchi
Cc: Francisco Jerez
Cc: Jon Bloomfield
Signed-off-by: Matt Roper
Reviewed-by: Lucas De Marchi
Lucas De Marchi
Reviewed-by: Tomasz Lis
Tomasz
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
1
On 2019-07-25 00:32, Lucas De Marchi wrote:
On Thu, Jul 18, 2019 at 10:09:27AM -0700, Daniele Ceraolo Spurio wrote:
On 7/18/19 6:08 AM, Ville Syrjälä wrote:
On Fri, Jul 12, 2019 at 06:09:36PM -0700, Lucas De Marchi wrote:
From: Tomasz Lis
The MOCS table is published as part of bspec, and
table.table[0].control_value);
While get_mocs_settings() can return a table with less than 64 entries,
it will never be the case for platforms supporting global MOCS.
So this for() is actually a dead code.. but removing it could cause harm
in case this is forgotten and modifications are made
On 2018-03-30 20:23, Daniele Ceraolo Spurio wrote:
On 27/03/18 16:27, Chris Wilson wrote:
Quoting Tomasz Lis (2018-03-27 16:17:59)
The patch adds support of preempt-to-idle requesting by setting a
proper
bit within Execlist Control Register, and receiving preemption
result from
Context St
On 2018-03-30 21:45, Daniele Ceraolo Spurio wrote:
On 30/03/18 08:42, Lis, Tomasz wrote:
On 2018-03-29 00:28, Chris Wilson wrote:
Quoting Lis, Tomasz (2018-03-28 17:06:58)
On 2018-03-28 01:27, Chris Wilson wrote:
Quoting Tomasz Lis (2018-03-27 16:17:59)
The patch adds support of
So I understand we agree on the change, just waiting for non-RFC version?
-Tomasz
On 2018-09-24 11:34, Jani Nikula wrote:
On Thu, 20 Sep 2018, Tvrtko Ursulin wrote:
Ping!
Any comments here?
Main goal was to allow GEM_WARN_ON as a statement, plus also protect
uses in if statements, which the
On 2018-10-12 08:31, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
GEM_WARN_ON currently has dangerous semantics where it is completely
compiled out on !GEM_DEBUG builds. This can leave users who expect it to
be more like a WARN_ON, just without a warning in non-debug builds, in
complete ignoran
On 2018-10-12 20:25, Daniele Ceraolo Spurio wrote:
With the new interface, GuC now requires every lrc to be registered in
one of the stage descriptors, which have been re-designed so that each
descriptor can store up to 64 lrc per class (i.e. equal to the possible
SW counter values).
Similarly
On 2018-10-16 12:53, Joonas Lahtinen wrote:
Quoting Tomasz Lis (2018-10-15 20:29:18)
The patch adds support of preempt-to-idle requesting by setting a proper
bit within Execlist Control Register, and receiving preemption result from
Context Status Buffer.
Preemption in previous gens required
On 2018-10-23 11:13, Joonas Lahtinen wrote:
Quoting Lis, Tomasz (2018-10-19 19:00:15)
On 2018-10-16 12:53, Joonas Lahtinen wrote:
Quoting Tomasz Lis (2018-10-15 20:29:18)
The patch adds support of preempt-to-idle requesting by setting a proper
bit within Execlist Control Register, and
On 2018-10-22 20:18, Daniele Ceraolo Spurio wrote:
On 22/10/18 10:13, Tomasz Lis wrote:
For Icelake and above, MOCS table for each platform is published
within bspec. The table is versioned, and new entries are assigned
a version number. Existing entries do not change and their version
is co
On 2018-10-22 19:40, Daniele Ceraolo Spurio wrote:
On 22/10/18 10:13, Tomasz Lis wrote:
The table has been unified across OSes to minimize virtualization
overhead.
The MOCS table is now published as part of bspec, and versioned. Entries
are supposed to never be modified, but new ones can b
On 2018-06-11 18:37, Daniele Ceraolo Spurio wrote:
On 25/05/18 11:26, Tomasz Lis wrote:
The patch adds support of preempt-to-idle requesting by setting a proper
bit within Execlist Control Register, and receiving preemption result
from
Context Status Buffer.
Preemption in previous gens re
On 2018-07-09 15:48, Lionel Landwerlin wrote:
On 09/07/18 14:20, Tomasz Lis wrote:
The patch adds a parameter to control the data port coherency
functionality
on a per-context level. When the IOCTL is called, a command to switch
data
port coherency state is added to the ordered list. All prio
On 2018-07-09 16:24, Lionel Landwerlin wrote:
On 09/07/18 15:03, Lis, Tomasz wrote:
On 2018-07-09 15:48, Lionel Landwerlin wrote:
On 09/07/18 14:20, Tomasz Lis wrote:
The patch adds a parameter to control the data port coherency
functionality
on a per-context level. When the IOCTL is
lushes.
-Chris
Joonas did brought that concern in his review; here it is, with my response:
On 2018-06-21 15:47, Lis, Tomasz wrote:
On 2018-06-21 08:39, Joonas Lahtinen wrote:
I'm thinking we should set this value when it has changed, when we
insert the
requests into the command stream
On 2018-07-09 18:28, Tvrtko Ursulin wrote:
On 09/07/2018 14:20, Tomasz Lis wrote:
The patch adds a parameter to control the data port coherency
functionality
on a per-context level. When the IOCTL is called, a command to switch
data
port coherency state is added to the ordered list. All prio
On 2018-07-10 20:03, Lis, Tomasz wrote:
On 2018-07-09 18:28, Tvrtko Ursulin wrote:
On 09/07/2018 14:20, Tomasz Lis wrote:
diff --git a/drivers/gpu/drm/i915/intel_lrc.h
b/drivers/gpu/drm/i915/intel_lrc.h
index 1593194..f6965ae 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers
On 2018-07-13 12:40, Tvrtko Ursulin wrote:
On 12/07/2018 16:10, Tomasz Lis wrote:
The patch adds a parameter to control the data port coherency
functionality
on a per-context level. When the IOCTL is called, a command to switch
data
port coherency state is added to the ordered list. All prio
On 2018-07-18 16:42, Tvrtko Ursulin wrote:
On 18/07/2018 14:24, Joonas Lahtinen wrote:
Quoting Tomasz Lis (2018-07-16 16:07:16)
+static int emit_set_data_port_coherency(struct i915_request *rq,
bool enable)
+{
+ u32 *cs;
+ i915_reg_t reg;
+
+ GEM_BUG_ON(rq->engine->class !
On 2018-07-19 09:12, Joonas Lahtinen wrote:
Quoting Lis, Tomasz (2018-07-18 18:28:32)
On 2018-07-18 16:42, Tvrtko Ursulin wrote:
On 18/07/2018 14:24, Joonas Lahtinen wrote:
Quoting Tomasz Lis (2018-07-16 16:07:16)
+++ b/include/uapi/drm/i915_drm.h
@@ -1456,6 +1456,13 @@ struct
On 2018-07-20 12:19, Chris Wilson wrote:
Not all chipsets have an internal buffer delaying the visibility of
writes via the GGTT being visible by other physical paths, but we use a
very heavy workaround for all. We only need to apply that workarounds to
the chipsets we know suffer from the dela
On 2018-08-30 02:16, Lionel Landwerlin wrote:
On 29/08/2018 20:58, Michel Thierry wrote:
+Lionel
(please see below as this touches the lrca format & relates to OA
reporting too)
On 8/29/2018 12:10 PM, Michal Wajdeczko wrote:
Until now the GuC and HW engine class has been the same, which al
On 2018-08-30 02:08, Lionel Landwerlin wrote:
On 29/08/2018 20:16, Michal Wajdeczko wrote:
The new context descriptor format contains two assignable fields:
the SW Context ID (technically 11 bits, but practically limited to 2032
entries due to some being reserved for future use by the GuC) and
Uhh, sorry - answered on wrong patch.
Please ignore this one.
-Tomasz
On 2018-08-30 15:29, Lis, Tomasz wrote:
On 2018-08-30 02:16, Lionel Landwerlin wrote:
On 29/08/2018 20:58, Michel Thierry wrote:
+Lionel
(please see below as this touches the lrca format & relates to OA
reporting
On 2018-08-30 16:15, Lis, Tomasz wrote:
On 2018-08-30 02:08, Lionel Landwerlin wrote:
On 29/08/2018 20:16, Michal Wajdeczko wrote:
The new context descriptor format contains two assignable fields:
the SW Context ID (technically 11 bits, but practically limited to 2032
entries due to some
On 2018-03-19 13:43, Chris Wilson wrote:
Quoting Tomasz Lis (2018-03-19 12:37:35)
The patch adds a parameter to control the data port coherency functionality
on a per-exec call basis. When data port coherency flag value is different
than what it was in previous call for the context, a command
On 2018-03-19 14:53, Joonas Lahtinen wrote:
+ Dave, as FYI
Quoting Tomasz Lis (2018-03-19 14:37:34)
The OpenCL driver develpers requested a functionality to control cache
coherency at data port level. Keeping the coherency at that level is disabled
by default due to its performance costs. Ope
On 2018-03-19 15:26, Chris Wilson wrote:
Quoting Lis, Tomasz (2018-03-19 14:14:19)
On 2018-03-19 13:43, Chris Wilson wrote:
Quoting Tomasz Lis (2018-03-19 12:37:35)
The patch adds a parameter to control the data port coherency functionality
on a per-exec call basis. When data port
On 2018-03-21 20:42, Oscar Mateo wrote:
On 3/21/2018 3:16 AM, Chris Wilson wrote:
Quoting Oscar Mateo (2018-03-20 18:43:45)
On 3/19/2018 7:14 AM, Lis, Tomasz wrote:
On 2018-03-19 13:43, Chris Wilson wrote:
Quoting Tomasz Lis (2018-03-19 12:37:35)
The patch adds a parameter to control
On 2018-03-28 01:27, Chris Wilson wrote:
Quoting Tomasz Lis (2018-03-27 16:17:59)
The patch adds support of preempt-to-idle requesting by setting a proper
bit within Execlist Control Register, and receiving preemption result from
Context Status Buffer.
Preemption in previous gens required a s
On 2018-03-29 00:28, Chris Wilson wrote:
Quoting Lis, Tomasz (2018-03-28 17:06:58)
On 2018-03-28 01:27, Chris Wilson wrote:
Quoting Tomasz Lis (2018-03-27 16:17:59)
The patch adds support of preempt-to-idle requesting by setting a proper
bit within Execlist Control Register, and receiving
On 2018-05-18 23:08, Daniele Ceraolo Spurio wrote:
On 11/05/18 08:45, Tomasz Lis wrote:
The patch adds support of preempt-to-idle requesting by setting a proper
bit within Execlist Control Register, and receiving preemption result
from
Context Status Buffer.
Preemption in previous gens re
On 2018-05-22 16:39, Ceraolo Spurio, Daniele wrote:
On 5/21/2018 3:16 AM, Lis, Tomasz wrote:
On 2018-05-18 23:08, Daniele Ceraolo Spurio wrote:
On 11/05/18 08:45, Tomasz Lis wrote:
The patch adds support of preempt-to-idle requesting by setting a
proper
bit within Execlist Control
On 2018-06-21 09:05, Chris Wilson wrote:
Quoting Tomasz Lis (2018-06-20 16:03:07)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 33bc914..c69dc26 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -258,6 +258,57 @@ in
On 2018-06-21 08:39, Joonas Lahtinen wrote:
Changelog would be much appreciated. And this is not the first version
of the series. It helps to remind the reviewer that original
implementation was changed into IOCTl based on feedback. Please see the
git log in i915 for some examples.
Will add. I
On 2018-01-27 21:28, Chris Wilson wrote:
If we remove some hardcoded assumptions about the preempt context having
a fixed id, reserved from use by normal user contexts, we may only
allocate the i915_gem_context when required. Then the subsequent
decisions on using preemption reduce to having th
So the functional purpose of this patch is to provide capabilities
(including preemption status) within error information. I agree this is
required.
On 2018-02-01 20:02, Chris Wilson wrote:
Rather than having the high level ioctl interface guess the underlying
implementation details, having t
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