Hi,
On Tue, 1 Jun 2021, Anshuman Gupta wrote:
> DG1 and XE_PLD platforms has Audio MMIO/VERBS lies in PG0 power
> well. Adjusting the power domain accordingly to
> POWER_DOMAIN_AUDIO_VERBS for audio detection and POWER_DOMAIN_AUDIO
> for audio playback.
thanks Anshuman! From audio perspective th
Hi,
On Wed, 6 Oct 2021, Ville Syrjälä wrote:
> On Mon, Sep 13, 2021 at 07:40:04PM +0300, Kai Vehmanen wrote:
> > XE_LPD display adds support for display audio codec keepalive feature.
> > This feature works also when display codec is in D3 state and the audio
> > link
s handling for master device")
Cc: sta...@vger.kernel.org
BugLink: https://gitlab.freedesktop.org/drm/intel/-/issues/4136
Fixes: 9e1ccb4a7700 ("drivers/base: fix devres handling for master device")
Signed-off-by: Kai Vehmanen
Acked-by: Imre Deak
Acked-by: Russell King (Oracle)
---
drivers
timestamps are generated only when the audio codec driver
specifically enables the KeepAlive (KAE) feature.
This patch adds new hooks to intel_set_cdclk() in order to inform
display audio driver when CDCLK change is started and when it is
complete.
Bspec: 53679
Signed-off-by: Kai Vehmanen
Reviewed-by: Uma
timestamps are generated only when the audio codec driver
specifically enables the KeepAlive (KAE) feature.
This patch adds new hooks to intel_set_cdclk() in order to inform
display audio driver when CDCLK change is started and when it is
complete.
Bspec: 53679
Signed-off-by: Kai Vehmanen
---
drivers/gpu
Hi,
On Fri, 10 Sep 2021, Jani Nikula wrote:
> Nitpick, switching to i915 variable name instead of dev_priv is
> preferred for new code throughout.
ack, changed.
> On Fri, 10 Sep 2021, Kai Vehmanen wrote:
> > + if (DISPLAY_VER(dev_priv) >= 13) {
> > + tmp
g for master device").
BugLink: https://gitlab.freedesktop.org/drm/intel/-/issues/4136
Signed-off-by: Kai Vehmanen
---
drivers/base/component.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
Hi,
I'm sending this as RFC as I'm not sure of the implications of
not leavin
ng for master device")
BugLink: https://gitlab.freedesktop.org/drm/intel/-/issues/4136
Signed-off-by: Kai Vehmanen
Acked-by: Imre Deak
Acked-by: Russell King (Oracle)
---
drivers/base/component.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
V2 changes:
- after review form I
Hey,
On Tue, 28 Sep 2021, Takashi Iwai wrote:
> On Wed, 22 Sep 2021 10:54:32 +0200, Kai Vehmanen wrote:
> > --- a/drivers/base/component.c
> > +++ b/drivers/base/component.c
> > @@ -246,7 +246,7 @@ static int try_to_bring_up_master(struct master *master,
>
Hi,
On Tue, 5 Oct 2021, Greg KH wrote:
> On Wed, Sep 22, 2021 at 11:54:32AM +0300, Kai Vehmanen wrote:
> > In current code, the devres group for aggregate master is left open
> > after call to component_master_add_*(). This leads to problems when the
> > master does furthe
thanks Kai-Heng! We were not aware of commercial RKL systems following the
old BIOS guidance, but given you just hit one, then this definitely is
needed:
Reviewed-by: Kai Vehmanen
Br, Kai
timestamps are generated only when the audio codec driver
specifically enables the KeepAlive (KAE) feature.
This patch adds new hooks to intel_set_cdclk() in order to inform
display audio driver when CDCLK change is started and when it is
complete.
Bspec: 53679
Signed-off-by: Kai Vehmanen
---
drivers/gpu
incorrect values.
Bspec: 49279
Signed-off-by: Kai Vehmanen
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_audio.c | 30 ++
1 file changed, 25 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915
When audio power domain is suspended, the display driver must
save state of AUD_FREQ_CNTRL on Tiger Lake and Ice Lake
systems. The initial value of the register is set by BIOS and
is read by driver during the audio component init sequence.
Cc: Jani Nikula
Cc: Imre Deak
Signed-off-by: Kai
_codec.c code),
so I'd say let's go with this patch for GLK:
Reviewed-by: Kai Vehmanen
Br, Kai
problem.
Co-developed-by: Ramalingam C
Signed-off-by: Ramalingam C
Signed-off-by: Kai Vehmanen
---
sound/hda/hdac_i915.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Changes V2->V3:
- drop the loop and just use
wait_for_completion_killable_timeout() (feedback from Tvr
Hi,
On Fri, 22 Jul 2022, Taylor, Clinton A wrote:
> Use BSPEC values for the Audio Keep alive M and N values as included in
> the cdclk BSPEC pages for display > 13
looks good, only a few very minor style comments.
I had a table in my original patch, but Ville preferred calculating
on-the-fly
display_dev->vendor == PCI_VENDOR_ID_INTEL &&
> - connectivity_check(display_dev, hdac_pci))
> + connectivity_check(display_dev, hdac_pci)) {
> + pci_dev_put(display_dev);
> match = true;
> -
> -
1c0
Fix the issue by setting drvdata to NULL at end of azx_remove().
Signed-off-by: Kai Vehmanen
---
sound/pci/hda/hda_intel.c | 1 +
1 file changed, 1 insertion(+)
Some non-persistent direct links showing the bug trigger on
different platforms with linux-next 20211109:
-
https://intel-gfx-ci
Hey,
On Wed, 10 Nov 2021, Takashi Iwai wrote:
> On Wed, 10 Nov 2021 22:03:07 +0100, Kai Vehmanen wrote:
> > Fix a corner case between PCI device driver remove callback and
> > runtime PM idle callback.
[...]
> > Some non-persistent direct links showing the bug trigger on
&g
Hi,
On Thu, 11 Nov 2021, Takashi Iwai wrote:
> A potential problem with the current code is that it doesn't disable
> the runtime PM at the release procedure. Could you try the patch
> below? You can put WARN_ON(!chip) at azx_runtime_idle(), too, for
> catching the invalid runtime call.
[...]
>
Hi,
On Fri, 12 Nov 2021, Takashi Iwai wrote:
> On Thu, 11 Nov 2021 18:39:36 +0100, Kai Vehmanen wrote:
> > And later
> > [ 54.770701] Enabling runtime PM for inactive device (:00:1f.3) with
> > active children
> > [ 54.770718] WARNING: CPU: 0 PID: 10 at driver
ork+0x275/0x5c0
> <6>[ 60.947010] worker_thread+0x37/0x370
> <6>[ 60.947028] ? process_one_work+0x5c0/0x5c0
> <6>[ 60.947038] kthread+0xef/0x120
> <6>[ 60.947047] ? kthread_complete_and_exit+0x20/0x20
> <6>[ 60.947065] ret_from_fork+0x22
: Lucas De Marchi
Co-developed-by: Ramalingam C
Signed-off-by: Ramalingam C
Signed-off-by: Kai Vehmanen
---
sound/hda/hdac_i915.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/sound/hda/hdac_i915.c b/sound/hda/hdac_i915.c
index 454474ac5716..6219de739b56 100644
.
Reviewed-by: Lucas De Marchi
Co-developed-by: Ramalingam C
Signed-off-by: Ramalingam C
Signed-off-by: Kai Vehmanen
---
sound/hda/hdac_i915.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
Changes V1->V2:
- address local variable naming issue raised by Amadeusz
and
Hi,
On Wed, 9 Mar 2022, Tvrtko Ursulin wrote:
> > - /* 60s timeout */
>
> Where does this 60s come from and why is the fix to work around
> DEFAULT_HUNG_TASK_TIMEOUT in a hacky way deemed okay? For instance would
> limiting the wait here to whatever the kconfig is set to be an
Hi,
On Wed, 9 Mar 2022, Takashi Iwai wrote:
>> Takashi Iwai wrote:
>>> The question is how often this problem hits. Basically it's a very
>>> corner case, and I even think we may leave as is; that's a matter of
>>> configuration, and lowering such a bar should expect some
>>> side-effect. OTOH,
Hi,
On Wed, 24 Aug 2022, Jani Nikula wrote:
> On Wed, 24 Aug 2022, "Borah, Chaitanya Kumar"
> wrote:
> > In certain scenarios, we might have to filter out some audio
> > configuration depending on HW limitation. For example, in
> > GLK DP port more than 2 channels are not supported for audio.
[
-by: Kai Vehmanen
---
drivers/gpu/drm/i915/display/intel_audio.c | 5 +
drivers/gpu/drm/i915/i915_reg.h| 2 ++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index 54638d99e021..a731af7ada08
The CDCLK>=2*BCLK constraint applies to all generations since gen10.
Extend the constraint logic in audio get/put_power().
Signed-off-by: Kai Vehmanen
---
drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/disp
Hey,
On Wed, 2 Oct 2019, Chris Wilson wrote:
> > + if (INTEL_GEN(dev_priv) == 11 || INTEL_GEN(dev_priv) == 10)
> > + I915_WRITE(AUD_PIN_BUF_CTL,
> > + (I915_READ(AUD_PIN_BUF_CTL) |
> > + AUD_PIN
Hey,
On Wed, 2 Oct 2019, Imre Deak wrote:
> On Tue, Oct 01, 2019 at 07:35:54PM +0300, Kai Vehmanen wrote:
> > On gen10/11 platforms, driver must set the enable bit of AUD_PIN_BUF_CTL
> > as part of audio power up sequence.
>
> Good catch, seems to match bspec 21352
The CDCLK>=2*BCLK constraint applies to all generations since gen10.
Extend the constraint logic in audio get/put_power().
Signed-off-by: Kai Vehmanen
---
drivers/gpu/drm/i915/display/intel_audio.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i
resume from suspend.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111214
Signed-off-by: Kai Vehmanen
---
drivers/gpu/drm/i915/display/intel_audio.c | 5 +
drivers/gpu/drm/i915/i915_reg.h| 2 ++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display
Hi,
On Wed, 2 Oct 2019, Kai Vehmanen wrote:
> I have one failing case left on ICL where v1 patchset does not seem
> sufficient. The test case involves a loop of doing S3 suspend, resume,
> unload driver, load driver, play audio via HDMI and repeat. I get
> systematically better
Hey,
On Fri, 4 Oct 2019, Patchwork wrote:
> URL : https://patchwork.freedesktop.org/series/67350/
[...]
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_14658_full absolutely need to
> be
> verified manually.
[...]
> * igt@gem_mmap_gtt@hang:
> - shard-kbl:
Starting with gen12, PORT_A can be also connected to DP
transcoder. Update code in intel_dp_init() to take this
into account.
Signed-off-by: Kai Vehmanen
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display
Starting with gen12, PORT_A can be connected to a transcoder
with audio support. Modify the existing logic that disabled
audio on PORT_A unconditionally.
Signed-off-by: Kai Vehmanen
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
Starting with gen12, PORT_A can be also connected to DP
transcoder. Update code in intel_dp_init() to take this
into account.
Signed-off-by: Kai Vehmanen
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display
Starting with gen12, PORT_A can be connected to a transcoder
with audio support. Modify the existing logic that disabled
audio on PORT_A unconditionally.
Signed-off-by: Kai Vehmanen
---
drivers/gpu/drm/i915/display/intel_dp.c | 13 -
1 file changed, 12 insertions(+), 1 deletion
Hi,
On Fri, 22 Nov 2019, Ville Syrjälä wrote:
> > - if (IS_G4X(dev_priv) || port == PORT_A)
> > + if (IS_G4X(dev_priv) || (INTEL_GEN(dev_priv) < 12 && port == PORT_A))
>
> Getting a bit messy.
>
> Hoovering that into something like
> static bool intel_dp_port_has_audio(struct intel_encoder
Hey,
On Tue, 26 Nov 2019, Patchwork wrote:
> Series: series starting with [v2,1/2] drm/i915/dp: fix DP audio for PORT_A on
> gen12+
> URL : https://patchwork.freedesktop.org/series/69982/
[...]
> - shard-skl: [PASS][1] -> [FAIL][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-
Hi,
On Tue, 26 Nov 2019, Matt Roper wrote:
> On Mon, Nov 25, 2019 at 02:53:13PM +0200, Kai Vehmanen wrote:
> > Starting with gen12, PORT_A can be also connected to DP
> > transcoder. Update code in intel_dp_init() to take this
> > into account.
>
> I don't th
Hi Blaž,
On Fri, 27 Dec 2019, Blaž Hrastnik wrote:
> Hi! I'm using a Surface Laptop 3 (Intel version, i7-1065G7) which is
> running the i915 driver. I have a screen flicker issue in 5.5rc that I
[...]
> It works on commit "x86/intel: Disable HPET on Intel Ice Lake
> platforms". But it doesn't
Hey Matt,
On Tue, 24 Dec 2019, Matt Roper wrote:
> > When audio power domain is suspended, the display driver must
> > save state of AUD_FREQ_CNTRL on Tiger Lake and Ice Lake
> > systems. The initial value of the register is set by BIOS and
>
> I realize this patch landed several months ago, but
straint is still enforced at pipe
enable time in intel_crtc_compute_min_cdclk().
Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/913
Signed-off-by: Kai Vehmanen
---
drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/
straint is still enforced at pipe
enable time in intel_crtc_compute_min_cdclk().
Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/913
Signed-off-by: Kai Vehmanen
---
Notes:
v2: d'oh, change put_power() as well
drivers/gpu/drm/i915/display/intel_audio.c | 4 ++--
1 file change
On old platforms the default values of AUD_FREQ_CNTRL are
typically used (as set by BIOS), so this has not been an issue,
but future platforms will definitely need this. Extend the state
save logic to cover all gen9+ platforms.
Bspec: 49281
Cc: Matt Roper
Signed-off-by: Kai Vehmanen
Hey,
On Tue, 31 Dec 2019, Matt Roper wrote:
> On Tue, Dec 31, 2019 at 04:47:18PM +0200, Kai Vehmanen wrote:
> > On old platforms the default values of AUD_FREQ_CNTRL are
> > typically used (as set by BIOS), so this has not been an issue,
> > but future platforms will definit
Hi,
On Thu, 2 Jan 2020, Rodrigo Vivi wrote:
> On Tue, Dec 31, 2019 at 04:00:07PM +0200, Kai Vehmanen wrote:
>> Revert changes done in commit f6ec9483091f ("drm/i915: extend audio
>> CDCLK>=2*BCLK constraint to more platforms"). Audio drivers
[...]
>>
Hey,
On Tue, 10 Mar 2020, Takashi Iwai wrote:
> On Tue, 10 Mar 2020 19:25:22 +0100, Ville Syrjälä wrote:
>> On Tue, Mar 10, 2020 at 07:18:58PM +0200, Kai Vehmanen wrote:
>>> One problematic scenario that this doesn't cover:
>>> - a single display is used (at low
Hey,
On Wed, 11 Mar 2020, Takashi Iwai wrote:
> The remaining question is whether this display_power() call is still
> needed for the recent chips. Basically it's there for HSW/BDW type
> chips that need already the power for the HDA link that is dedicated
> to HDMI. That is, a patch like below
Hey,
On Tue, 10 Mar 2020, Ville Syrjälä wrote:
> On Tue, Mar 10, 2020 at 07:18:58PM +0200, Kai Vehmanen wrote:
>> On Tue, 10 Mar 2020, Ville Syrjälä wrote:
>>> audio at init time. And we could maybe try to remove the modeset from the
>>> put_power() so that at least i
platforms.
Bspec: 49281
Link: https://github.com/thesofproject/linux/issues/1719
Signed-off-by: Kai Vehmanen
---
drivers/gpu/drm/i915/display/intel_audio.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i9
wer()/put_power()
do not result in display artifacts.
If 2*BCLK is below lowest CDCLK, this patch has no effect.
If a future platform provides means to change CDCLK without
a modeset, the constraint code can be moved to get/put_power()
for these platforms.
Signed-off-by: Kai Vehmanen
---
drivers/
Instead of assuming maximum value of BCLK (96Mhz), use the actual value
as configured by BIOS.
Signed-off-by: Kai Vehmanen
---
drivers/gpu/drm/i915/display/intel_audio.c | 13 -
drivers/gpu/drm/i915/display/intel_audio.h | 1 +
drivers/gpu/drm/i915/display/intel_cdclk.c | 6
Hey,
On Thu, 12 Mar 2020, Ville Syrjälä wrote:
> On Thu, Mar 12, 2020 at 07:27:58PM +0200, Kai Vehmanen wrote:
>> So I think this starts to look that we should move calling glk_force_audio
>> to bind/unbind pair. I can make a patch for this.
>
> That would stop us fro
Hey,
On Fri, 13 Mar 2020, Ville Syrjälä wrote:
> On Fri, Mar 13, 2020 at 04:48:21PM +0200, Kai Vehmanen wrote:
>> This patch moves modifying the min_cdclk at audio component bind
>> phase and extends coverage to all gen9+ platforms. This effectively
>
> So this will now f
Hey Ville and others,
On Fri, 13 Mar 2020, Kai Vehmanen wrote:
> On Fri, 13 Mar 2020, Ville Syrjälä wrote:
> Now thinking of another possibility, is it possible to hook code to
> power-up of power domains? E.g. can I hook custom code which is executed
[...]
> If we cou
ng on some gen12 platforms. And based on specs, there
is no reason why this programming sequence should not be applied to all
gen9+ platforms. No side-effects are seen on gen10/11. So apply
the wake-logic to all gen9+ platforms.
Link: https://github.com/thesofproject/linux/issues/1847
Signed-off-by: Ka
Hi Ville and others,
On Fri, 13 Mar 2020, Kai Vehmanen wrote:
> I do know that on more recent hardware (gen12), I will get failures if I
> don't strictly follow the requirement. GLK is a special case as it has the
> 79Mhz low cdclk. I've not been able to trigger the p
Hey folks,
On Fri, 20 Mar 2020, Shankar, Uma wrote:
> Souza, Jose wrote:
> > On Wed, 2020-03-18 at 17:00 +0530, Uma Shankar wrote:
> > > This patch fixes the same by triggering a modeset at boot.
> >
> > We had the same issue for PSR, take a look to the fix:
> > commit 33e059a2e4df454359f642f223
platforms.
Bspec: 49281
Link: https://github.com/thesofproject/linux/issues/1719
Signed-off-by: Kai Vehmanen
---
drivers/gpu/drm/i915/display/intel_audio.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i9
Hi,
thanks Uma! It's good to see the implementation is this localized and
doesn't need changes elsewhere. Other reviewers already covered most
parts, but a few notes:
On Tue, 7 Apr 2020, Uma Shankar wrote:
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel
Hey,
On Mon, 30 Mar 2020, Kai Vehmanen wrote:
> Replace the TGL/ICL specific platform checks with a more generic check
> using INTEL_GEN(). Fixes bug with broken audio after S3 resume on JSL
> platforms.
I would be (gently) beaten with a stick on alsa-devel for sending this
type of con
Hey,
On Thu, 9 Apr 2020, Ville Syrjälä wrote:
> On Thu, Apr 09, 2020 at 05:14:01PM +0300, Kai Vehmanen wrote:
> > type of content free ping, but I still dare to seek your input on what is
> > the proper way to get attention to a patch that are seemingly forever
> > stuck o
addition:
Reviewed-by: Kai Vehmanen
Maybe one point to consider is whether to take the next step and just
block the unload. On audio side, once acomp binding is done to i915
driver, it is only released at hda driver unload. So any test case where
audio driver is bound to i915, and test unl
Gen12 hardware supports HDMI audio pixel clocks of 296.7/297Mhz
and 593.4/594Mhz. Add the missing rates and add logic to ignore
them if running on older hardware.
Bspec: 49333
Signed-off-by: Kai Vehmanen
---
drivers/gpu/drm/i915/display/intel_audio.c | 16 +---
drivers/gpu/drm/i915
Hi,
On Mon, 27 Jan 2020, Ville Syrjälä wrote:
> On Mon, Jan 27, 2020 at 01:39:09PM +0200, Kai Vehmanen wrote:
> > Gen12 hardware supports HDMI audio pixel clocks of 296.7/297Mhz
> > and 593.4/594Mhz. Add the missing rates and add logic to ignore
> > them if runn
Gen12 hardware supports HDMI audio pixel clocks of 296.7/297Mhz
and 593.4/594Mhz. Add the missing rates and add logic to ignore
them if running on older hardware.
Bspec: 49333
Signed-off-by: Kai Vehmanen
---
drivers/gpu/drm/i915/display/intel_audio.c | 14 +++---
drivers/gpu/drm/i915
Hey,
On Mon, 3 Feb 2020, Ville Syrjälä wrote:
> > /* need to hold at least one crtc lock for the global state */
> > - crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
>
> Was thinking a simple 'return 0' would do the trick, but maybe we
> don't want to call this at all. OTOH not sure why
Hey,
some delay but coming back to this CI failure:
On Fri, 31 Jan 2020, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Add missing HDMI audio pixel clocks for gen12 (rev2)
> URL : https://patchwork.freedesktop.org/series/72617/
> State : failure
I've been going through the lo
This reverts commit 3632610d38316bca9b0cd9d649ce3cefab58520a.
DG1 has been supported in upstream since v5.10 with commit
69b08bdfa818 ("ALSA: hda - add Intel DG1 PCI and HDMI ids").
Cc: Chris Wilson
Signed-off-by: Kai Vehmanen
---
sound/hda/hdac_i915.c | 23
incorrect values.
Bspec: 49279
Signed-off-by: Kai Vehmanen
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_audio.c | 30 ++
1 file changed, 25 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915
Hi,
On Fri, 12 Feb 2021, Chris Wilson wrote:
> Quoting Kai Vehmanen (2021-02-12 14:53:02)
> > This reverts commit 3632610d38316bca9b0cd9d649ce3cefab58520a.
> >
> > DG1 has been supported in upstream since v5.10 with commit
> > 69b08bdfa818 ("ALSA: hda
+ b/0001-ALSA-hda-Add-Intel-DG2-PCI-ID-and-HDMI-codec-vid.patch
@@ -0,0 +1,47 @@
+From Mon Sep 17 00:00:00 2001
+From: Kai Vehmanen
+Date: Thu, 18 Feb 2021 12:33:48 +0200
+Subject: [PATCH] ALSA: hda: Add Intel DG2 PCI ID and HDMI codec vid
+
+Add HD Audio PCI
Auto-generated diff between internal/internal..internal
---
sound/pci/hda/hda_intel.c | 6 +-
sound/pci/hda/patch_hdmi.c | 1 +
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 27e02cdef6d9..8d3d7e700ca3 100644
--- a/sou
Add HD Audio PCI ID and HDMI codec vendor ID for Intel DG2.
Signed-off-by: Kai Vehmanen
---
sound/pci/hda/hda_intel.c | 6 +-
sound/pci/hda/patch_hdmi.c | 1 +
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index
Hi,
On Fri, 12 Feb 2021, Kai Vehmanen wrote:
> Update logic to program AUD_FREQ_CNTRL register based on new guidance.
> Earlier this register was configured by BIOS and driver discovered the
> value at init. This is no longer recommended and instead driver should
> set the values
probe.
Fix the design by moving completion mechanism to common acomp
code and remove the related code from hdac_i915.
Co-developed-by: Kai Vehmanen
Signed-off-by: Kai Vehmanen
Signed-off-by: Takashi Iwai
---
include/drm/drm_audio_component.h | 4
sound/hda/hdac_component.c| 3
y audio on GLK platform with 5.9-rc1 kernel. Fix
the issue by moving intel_modeset_checks() call later.
Fixes: 4f0b4352bd26 ("drm/i915: Extract cdclk requirements checking to separate
function)"
BugLink: https://github.com/thesofproject/linux/issues/2410
Signed-off-by: Kai Vehmanen
Hey,
On Thu, 3 Sep 2020, Ville Syrjälä wrote:
> On Tue, Sep 01, 2020 at 06:10:36PM +0300, Kai Vehmanen wrote:
>> In commit 4f0b4352bd26 ("drm/i915: Extract cdclk requirements checking
>> to separate function") the order of force_min_cdclk_changed check and
>> intel
Hi folks,
[+Takashi from ALSA]
On Mon, 6 Jan 2020, Matt Roper wrote:
>>> On Tue, Dec 31, 2019 at 04:00:07PM +0200, Kai Vehmanen wrote:
>>>> Revert changes done in commit f6ec9483091f ("drm/i915: extend audio
>>>> CDCLK>=2*BCLK constraint to more pla
Hey,
On Mon, 9 Mar 2020, Takashi Iwai wrote:
> On Fri, 06 Mar 2020 17:45:44 +0100, Kai Vehmanen wrote:
>> unfortunately it seems this fix that was done is not holding up in wider
>> testing. It now looks we need to enforce the constraint in one form or
[...]
>> So h
Gen12 hardware supports HDMI audio pixel clocks of 296.7/297Mhz
and 593.4/594Mhz. Add the missing rates and add logic to ignore
them if running on older hardware.
Bspec: 49333
Signed-off-by: Kai Vehmanen
---
drivers/gpu/drm/i915/display/intel_audio.c | 14 +++---
drivers/gpu/drm/i915
Hey,
On Tue, 10 Mar 2020, Ville Syrjälä wrote:
> On Tue, Mar 10, 2020 at 03:39:20PM +0200, Kai Vehmanen wrote:
>> Gen12 hardware supports HDMI audio pixel clocks of 296.7/297Mhz
>> and 593.4/594Mhz. Add the missing rates and add logic to ignore
>> them if running on older
Gen12 hardware supports HDMI audio pixel clocks of 296.7/297Mhz
and 593.4/594Mhz. Add the missing rates and add logic to ignore
them if running on older hardware.
Bspec: 49333
Signed-off-by: Kai Vehmanen
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_audio.c | 8
Hi,
On Tue, 10 Mar 2020, Ville Syrjälä wrote:
>> On Fri, 06 Mar 2020 17:45:44 +0100, Kai Vehmanen wrote:
>>> Similarly on i915 side, it would seem pretty unlikely that we are going
>>> to get smooth changes of CDCLK. It might work better on some platforms,
>
> T
hit a fair balance. For the series:
Reviewed-by: Kai Vehmanen
Br, Kai
: sta...@vger.kernel.org
Fixes: 15175a4f2bbb ("ALSA: hda/hdmi: add keep-alive support for ADL-P and DG2")
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/8307
Signed-off-by: Kai Vehmanen
---
sound/pci/hda/patch_hdmi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --g
Hi,
[+Jyri]
On Fri, 9 Jun 2023, Mitul Golani wrote:
> Compute SADs that takes into account the supported rate and channel
> based on the capabilities of the audio source. This wrapper function
> should encapsulate the logic for determining the supported rate and
> channel and should return a set
Hey,
replying to 9th June version (my mistake), but I checked the 15th June
patch version and comments applied to that one as well:
On Fri, 9 Jun 2023, Mitul Golani wrote:
> Initialize the source audio capabilities for HDMI in crtc_state
> property by setting them to their maximum supported valu
Hey,
On Tue, 20 Jun 2023, Borah, Chaitanya Kumar wrote:
> > -Original Message-
> > From: Intel-gfx On Behalf Of Kai
> > Vehmanen
> > On Fri, 9 Jun 2023, Mitul Golani wrote:
[...]
> > This will hit a problem if we have a case where bandwidth is not enough f
Hi,
On Mon, 26 Jun 2023, Golani, Mitulkumar Ajitkumar wrote:
> Let's say, with the obtained audio_req_bandwidth, if I encounter the
> following combination:
> pipe_config->audio.max_channel = 8 and pipe_config->audio.max_frequency = "X"
> value.
> Now, let's assume my sink supports only 7 channe
Hi,
On Tue, 14 Nov 2023, Takashi Iwai wrote:
> On Tue, 14 Nov 2023 14:31:25 +0100, Saarinen, Jani wrote:
> > Was this series tested on CI ever as Ville saying no? How this got merged?
>
> Hm, I somehow believed that patches have been tested by intel people,
> as they came from intel. (Also th
Hi,
I'll send this first to intel-gfx to verify the i915 CI results. If
all ok, I'll send this series to ALSA/sound upstream.
This seriers is to address kms_hdmi_inject@inject-audio failures
reported in:
https://gitlab.freedesktop.org/drm/igt-gpu-tools/-/issues/3
Kai Vehmanen (3):
/-/issues/3
Signed-off-by: Kai Vehmanen
---
sound/pci/hda/patch_hdmi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
index 1cde2a69bdb4..b152c941414f 100644
--- a/sound/pci/hda/patch_hdmi.c
+++ b/sound/pci/hda/patch_hdmi.c
@@ -1994,6 +1994,7
On multiple sysstem with Prime B560M-A with Intel Sky Lake or Kaby Lake,
the display codec pins are not registered properly without the connect-all
quirk.
Link: https://gitlab.freedesktop.org/drm/igt-gpu-tools/-/issues/3
Signed-off-by: Kai Vehmanen
---
sound/pci/hda/patch_hdmi.c | 1 +
1 file
On ASUSTeK Z170 PRO GAMING + Intel Sky Lake system the display codec
pins are not registered properly without the connect-all quirk.
Link: https://gitlab.freedesktop.org/drm/igt-gpu-tools/-/issues/3
Signed-off-by: Kai Vehmanen
---
sound/pci/hda/patch_hdmi.c | 1 +
1 file changed, 1 insertion
.
Link: https://gitlab.freedesktop.org/drm/intel/-/issues/9801
Signed-off-by: Kai Vehmanen
---
sound/pci/hda/patch_hdmi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
index 3d7f8f510ec7..8bf91fe25c65 100644
--- a/sound/pci/hda
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