Look ok to me.
Reviewed-by: Juha-Pekka Heikkila
On 2.7.2021 23.46, Ville Syrjala wrote:
From: Ville Syrjälä
On FBC1 we can specify an arbitrary cfb stride. The hw will
simply throw away any compressed line that would exceed the
specified limit and keep using the uncompressed data instead.
Th
Hi Lakshmi,
Here would be again one false positive result.
/Juha-Pekka
On Wed, Jul 14, 2021 at 7:38 AM Patchwork
wrote:
> *Patch Details*
> *Series:* drm/i915: Fix wm params for ccs
> *URL:* https://patchwork.freedesktop.org/series/92491/
> *State:* failure
> *Details:*
> https://intel-gfx-ci.
Swati Sharma kirjoitti 13.2.2019 klo 15.25:
The following pixel formats are packed format that follows 4:2:2
chroma sampling. For memory represenation each component is
allocated 16 bits each. Thus each pixel occupies 32bit.
Y210: For each component, valid data occupies MSB 10 bits.
I did earlier give R-b for this patch. The patch anyway hasn't changed
as those defines have not changed.
/Juha-Pekka
Swati Sharma kirjoitti 22.10.2018 klo 8.31:
From: Vidya Srinivas
Added needed plane control flag definitions for Y210, Y212 and
Y216 formats.
v3: no change
Signed-off-by: S
Swati Sharma kirjoitti 22.10.2018 klo 8.31:
From: Vidya Srinivas
In this patch, a list for icl specific pixel formats is created
in which Y210, Y212 and Y216 pixel formats are added along with
legacy pixel formats for primary and sprite plane.
v3: since support for planar formats on ICL was
Patches 13, 14 and this 15 look ok to me. Those num/den combos in 13 I
cannot bet my head on but the plumbing look all ok.
Also if on 1..8 some patch wasn't pushed yet, those are all
Reviewed-by: Juha-Pekka Heikkila
Ville Syrjala kirjoitti 8.7.2019 klo 15.53:
From: Ville Syrjälä
Now that t
Hi Lakshmi,
Here would be another false positive, I don't see how my changes would
affect debugfs_test@read_all_entries test on kbl.
/Juha-Pekka
to 16. kesäk. 2022 klo 19.31 Patchwork
kirjoitti:
> *Patch Details*
> *Series:* series starting with [1/3] drm/i915/display: Add smem fallback
> allo
Hi,
On 5.7.2022 12.49, Karthik B S wrote:
On 7/5/2022 3:08 PM, Murthy, Arun R wrote:
On 6/28/2022 4:34 PM, Arun R Murthy wrote:
In oder to trigger the async flip, a dummy flip is required after sync
flip so as to update the watermarks for async in KMD which happens as
part of this dummy flip.
Matthew Auld kirjoitti 11.5.2022 klo 13.41:
On Fri, 6 May 2022 at 14:11, Juha-Pekka Heikkila
wrote:
Add fallback smem allocation for dpt if stolen memory allocation failed.
Signed-off-by: Juha-Pekka Heikkila
---
drivers/gpu/drm/i915/display/intel_dpt.c | 16
1 file cha
Seems my first mail didn't come through so here's second time for this patch:
Reviewed-by: Juha-Pekka Heikkila
On Mon, Apr 4, 2022 at 4:39 PM Imre Deak wrote:
>
> From: Matt Roper
>
> The render/media engines on DG2 unify render compression and media
> compression into a single format for the
Look ok to me. I will try this on my HSW box to see will this affect
those issues which look really similar as seen on IVB/SNB
Reviewed-by: Juha-Pekka Heikkila
Ville Syrjala kirjoitti 28.9.2018 klo 16.24:
From: Ville Syrjälä
Sprite enable on ILK-IVB may take two frames to complete
when the
Alexandru-Cosmin Gheorghe kirjoitti 3.10.2018 klo 20.18:
On Wed, Oct 03, 2018 at 02:31:08PM +0300, Juha-Pekka Heikkila wrote:
Hi Alex,
For my patches there seems limited interest to get them merged before IGT
support these modes..I'm not holding my breath for this.
I'm interested if that co
Swati Sharma kirjoitti 12.9.2018 klo 13.32:
From: Vidya Srinivas
Signed-off-by: Swati Sharma
Signed-off-by: Vidya Srinivas
---
drivers/gpu/drm/i915/intel_display.c | 15 +++
drivers/gpu/drm/i915/intel_sprite.c | 3 +++
2 files changed, 18 insertions(+)
diff --git a/driver
Lisovskiy, Stanislav kirjoitti 14.9.2018 klo 17.30:
On Fri, 2018-09-14 at 16:47 +0300, Ville Syrjälä wrote:
On Fri, Sep 14, 2018 at 01:36:32PM +, Lisovskiy, Stanislav wrote:
On Fri, 2018-09-07 at 11:45 +0300, Stanislav Lisovskiy wrote:
Introduced new XYUV scan-in format for framebuffer a
These display patches probably should go through i915 ci also since it
changes code on i915.
patch itself look ok,
Reviewed-by: Juha-Pekka Heikkila
On Wed, Nov 13, 2024 at 1:53 PM Ankit Nautiyal
wrote:
>
> For Xe3_LPD the PIPE_MISC YUV420 Enable (bit 27), already implies enabling
> full blend
Set look ok to me and those missing ci results seem to never arrive..
Reviewed-by: Juha-Pekka Heikkila
On Wed, Dec 18, 2024 at 7:48 PM Ville Syrjala
wrote:
>
> From: Ville Syrjälä
>
> Get rid of the 64bpp YUV formats on ICL+ SDR planes due to
> some weird underruns they're causing on TGL, and
On Tue, Jan 28, 2025 at 3:08 PM Tvrtko Ursulin wrote:
>
>
> Hi,
>
> On 05/03/2024 16:44, Jani Nikula wrote:
> > On Wed, 28 Feb 2024, Juha-Pekka Heikkila
> > wrote:
> >> AuxCCS framebuffers don't work on Xe driver hence disable them
> >> from plane capabilities until they are fixed. FlatCCS frame
On Wed, Jan 29, 2025 at 10:44 AM Tvrtko Ursulin wrote:
>
>
> On 28/01/2025 15:55, Juha-Pekka Heikkilä wrote:
> > On Tue, Jan 28, 2025 at 3:08 PM Tvrtko Ursulin wrote:
> >>
> >>
> >> Hi,
> >>
> >> On 05/03/2024 16:44, Jani Nikula wrote:
look ok to me
Reviewed-by: Juha-Pekka Heikkila
On Sun, Mar 30, 2025 at 9:06 PM Vinod Govindapillai
wrote:
>
> Woraround recommend programming the fbc_stride for bmg always.
> Display driver handles the need to program the fbc stride using
> the override stride. So ensure that we always get the
19 matches
Mail list logo
