directly after the register read correct and intended?
>
> Also the same pattern is in other places, like vlv_pre_enable_dp.
Hm definitely looks suspect... I'll check it out. On the plus side
that code is actually working in practice, so maybe the zeroing isn't
too harmf
On Tue, 1 Oct 2013 00:19:55 +0300
Ville Syrjälä wrote:
> On Sat, Sep 28, 2013 at 08:05:14AM -0700, Jesse Barnes wrote:
> > On Sat, 28 Sep 2013 11:54:21 +0200
> > Daniel Vetter wrote:
> >
> > > On Fri, Sep 27, 2013 at 04:02:29PM -0700, Jesse Barnes wrote:
>
early (Ville)
consistently set CRI clock source everywhere (Ville)
v4: drop unnecessary setting of bit in vlv enable pll (Ville)
References: https://bugs.freedesktop.org/show_bug.cgi?id=67245
References: https://bugs.freedesktop.org/show_bug.cgi?id=69693
Signed-off-by: Jesse Barnes
---
driver
On Mon, 30 Sep 2013 11:18:28 +0300
Jani Nikula wrote:
> On Sat, 28 Sep 2013, Jesse Barnes wrote:
> > On VLV/BYT, backlight controls a per-pipe, so when adjusting the
> > backlight we need to pass the correct info. So make the externally
> > visible backlight functions take
On Mon, 30 Sep 2013 15:15:12 +0300
Ville Syrjälä wrote:
> On Mon, Sep 30, 2013 at 11:18:28AM +0300, Jani Nikula wrote:
> > On Sat, 28 Sep 2013, Jesse Barnes wrote:
> > > On VLV/BYT, backlight controls a per-pipe, so when adjusting the
> > > backlight we need to pass
Needed to prevent display corruption in high res panels.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_reg.h |2 ++
drivers/gpu/drm/i915/intel_pm.c |4 +++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915
On Tue, 1 Oct 2013 14:54:26 -0700
Jesse Barnes wrote:
> On Wed, 25 Sep 2013 17:34:56 +0100
> Chris Wilson wrote:
>
> > +void gen6_rps_idle(struct drm_i915_private *dev_priv)
> > +{
> > + mutex_lock(&dev_priv->rps.hw_lock);
> &g
On Wed, 25 Sep 2013 17:34:56 +0100
Chris Wilson wrote:
> +void gen6_rps_idle(struct drm_i915_private *dev_priv)
> +{
> + mutex_lock(&dev_priv->rps.hw_lock);
> + if (dev_priv->info->is_valleyview)
> + valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
> + else
> +
to mess with these, but we've gotten some good
numbers so far so I guess it's ok.
As a follow up, it might be nice to expose the power, balanced,
performance profiles to userspace via sysfs. Since we can't solve this
problem for all users and all needs, we can just punt it out to
On Tue, 1 Oct 2013 23:23:32 +0100
Chris Wilson wrote:
> On Tue, Oct 01, 2013 at 02:54:26PM -0700, Jesse Barnes wrote:
> > On Wed, 25 Sep 2013 17:34:56 +0100
> > Chris Wilson wrote:
> >
> > > +void gen6_rps_idle(struct drm_i915_private *dev_priv)
> &g
On Wed, 02 Oct 2013 11:02:29 +0300
Jani Nikula wrote:
> On Tue, 01 Oct 2013, Jesse Barnes wrote:
> > Needed to prevent display corruption in high res panels.
>
> Clueless question, could we do this only when we have a high res panel
> connected? More trouble than it'
that due to rounding, we actually get different
> values (slightly higher) for the effective ring frequency.
>
> CC: Jesse Barnes
> CC: Chris Wilson
> Signed-off-by: Ben Widawsky
> ---
> drivers/gpu/drm/i915/intel_pm.c | 8
> 1 file changed, 4 insertions(+), 4 delet
that due to rounding, we actually get different
> values (slightly higher) for the effective ring frequency.
>
> v3: Use 1.25 instead of 1.33 as the original code did. (Jesse)
>
> CC: Jesse Barnes
> CC: Chris Wilson
> Signed-off-by: Ben Widawsky
> ---
> drivers/gpu/drm/i9
Needed to prevent display corruption in high res panels.
v2: use correct unit names (Rodrigo)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_reg.h |2 ++
drivers/gpu/drm/i915/intel_pm.c |4 +++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm
On Wed, 2 Oct 2013 01:33:24 +0100
Chris Wilson wrote:
> On Tue, Oct 01, 2013 at 03:39:40PM -0700, Jesse Barnes wrote:
> > On Tue, 1 Oct 2013 23:23:32 +0100
> > Chris Wilson wrote:
> >
> > > On Tue, Oct 01, 2013 at 02:54:26PM -0700, Jesse Barnes wrote:
> > &g
On Wed, 2 Oct 2013 15:18:20 -0700
Jesse Barnes wrote:
> On Wed, 2 Oct 2013 22:57:41 +0100
> Chris Wilson wrote:
> > No, that is a factor I had not considered. I had been concerned about
> > monitoring latency whilst minimising frequency and using the power gauge
> > as
On Wed, 2 Oct 2013 22:57:41 +0100
Chris Wilson wrote:
> No, that is a factor I had not considered. I had been concerned about
> monitoring latency whilst minimising frequency and using the power gauge
> as the ultimate measure of success. One thing that is apparent with ivb,
> is that the power ga
On Thu, 3 Oct 2013 19:38:26 +0300
Ville Syrjälä wrote:
> On Fri, Sep 27, 2013 at 12:34:31PM +0300, Ville Syrjälä wrote:
> > On Thu, Sep 26, 2013 at 02:39:14PM -0700, Jesse Barnes wrote:
> > > This fixes resume on my test platform, since I think some DPIO bits need
&
CRI clock select (Ville)
References: https://bugs.freedesktop.org/show_bug.cgi?id=69166
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_display.c | 22 ++
2 files changed, 23 insertions(+), 1 deletion(-)
diff --git a
> - if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
> + if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
> DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
> i915_disable_vga(dev);
> i915_dis
for NULL crtc (Jani)
fixup connector check in ASLE code (Jani)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 11 +
drivers/gpu/drm/i915/intel_dp.c | 5 +--
drivers/gpu/drm/i915/intel_drv.h | 8
Updated these to include Jani's review feedback. Ultimately though, we
need to expand this to properly handle dual-panel support on BYT, or
figure out which is the correct connector in the OpRegion callback code.
I still have an open request from the VBIOS team about that.
And Ville is right that
-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h | 3 ++
drivers/gpu/drm/i915/i915_reg.h | 15 +
drivers/gpu/drm/i915/i915_suspend.c | 29
drivers/gpu/drm/i915/intel_panel.c | 67 ++---
4 files changed, 102 insertions(+), 12
Doesn't completely fix Uli's machine, but apparently it helps a bit, so:
Tested-by: Ulrich Drepper
On Wed, 2 Oct 2013 10:34:19 -0700
Jesse Barnes wrote:
> Needed to prevent display corruption in high res panels.
>
> v2: use correct unit names (Rodrigo)
>
> Si
On Sat, 5 Oct 2013 13:04:08 +0200
Daniel Vetter wrote:
> On Fri, Oct 4, 2013 at 9:42 PM, Jesse Barnes wrote:
> > On VLV/BYT, backlight controls a per-pipe, so when adjusting the
> > backlight we need to pass the correct info. So make the externally
> > visible backl
state, with a danger of causing undefined behaviour. However,
> as the boosting is a optional tweak to RPS, we can simply ignore it
> whilst RPS is not yet enabled.
>
> Signed-off-by: Chris Wilson
> Cc: Daniel Vetter
> Cc: Jesse Barnes
> ---
> drivers/gpu/drm/i915/i9
for NULL crtc (Jani)
fixup connector check in ASLE code (Jani)
v3: make sure we take the mode config lock around lookups (Daniel)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 12 +
drivers/gpu/drm/i915/intel_dp.c
-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h | 3 ++
drivers/gpu/drm/i915/i915_reg.h | 15 +
drivers/gpu/drm/i915/i915_suspend.c | 29
drivers/gpu/drm/i915/intel_panel.c | 67 ++---
4 files changed, 102 insertions(+), 12
On gen7+, CACHE_MODE_0 moved, so we're clobbering some other reg rather
than restoring CACHE_MODE_0. Don't do that.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_suspend.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915
So digging out the right ones is a little easier.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_sideband.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_sideband.c
b/drivers/gpu/drm/i915/intel_sideband.c
index acd1cfe..9944d81
71044)
> -#define _PIPEB_FRMCOUNT_GM45 0x71040
> -#define _PIPEB_FLIPCOUNT_GM450x71044
> +#define _PIPEBFRAMEHIGH 0x71040
> +#define _PIPEBFRAMEPIXEL 0x71044
> +#define _PIPEB_FRMCOUNT_GM45 (dev_priv->info->disp
Rather than using a HSW specific check.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 53c4ea8..5452b34 100644
--- a
lay is off.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_dma.c | 2 ++
drivers/gpu/drm/i915/i915_drv.c | 3 +++
drivers/gpu/drm/i915/i915_suspend.c | 2 --
drivers/gpu/drm/i915/intel_display.c | 4
4 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drive
On Fri, 11 Oct 2013 17:16:55 -0300
Paulo Zanoni wrote:
> 2013/10/11 Jesse Barnes :
> > Rather than using a HSW specific check.
> >
> > Signed-off-by: Jesse Barnes
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 3 +--
> > 1 file changed, 1 insertion(
This may need work if other platforms do the same thing, but in the
meantime we should avoid looking at HSW specific bits in this generic
function.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
On Fri, 11 Oct 2013 23:31:10 +0200
Daniel Vetter wrote:
> On Fri, Oct 11, 2013 at 11:31:53AM -0700, Jesse Barnes wrote:
>
> [snip]
>
> > static int intel_panel_get_brightness(struct backlight_device *bd)
> > {
> > - struct drm_device *dev = b
for NULL crtc (Jani)
fixup connector check in ASLE code (Jani)
v3: make sure we take the mode config lock around lookups (Daniel)
v4: fix double unlock in panel_get_brightness (Daniel)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915
On Fri, 11 Oct 2013 14:46:36 -0700
Jesse Barnes wrote:
> On VLV/BYT, backlight controls a per-pipe, so when adjusting the
> backlight we need to pass the correct info. So make the externally
> visible backlight functions take a connector argument, which can be used
> internally t
On Fri, 11 Oct 2013 14:34:35 -0700
Jesse Barnes wrote:
> > Ideas:
> > - Make sure all lvds/edp connectors are enabled and bash on all backlight
> > interfaces (with igt_fork it's easy to do that concurrently).
> > - Race the above with output changes: dpms
On Fri, 11 Oct 2013 18:39:01 -0300
Paulo Zanoni wrote:
> 2013/10/11 Jesse Barnes :
> > This may need work if other platforms do the same thing, but in the
> > meantime we should avoid looking at HSW specific bits in this generic
> > function.
> >
>
clock->m = i9xx_dpll_compute_m(clock);
> clock->p = clock->p1 * clock->p2;
> - clock->vco = refclk * clock->m / (clock->n + 2);
> - clock->dot = clock->vco / clock->p;
> + clock->vco = DIV_ROUND_CLO
+ vlv_clock(refclk, &clock);
>
> - pipe_config->port_clock = clock.dot / 10;
> + /* clock.dot is the fast clock */
> + pipe_config->port_clock = clock.dot / 5;
> }
>
> static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
Looks like
for NULL crtc (Jani)
fixup connector check in ASLE code (Jani)
v3: make sure we take the mode config lock around lookups (Daniel)
v4: fix double unlock in panel_get_brightness (Daniel)
v5: push ASLE work into a work queue (Daniel)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915
This set adds bits needed for runtime power support, currently only
lightly tested on VLV/BYT:
1) suspend/resume callbacks for different platforms
2) save/restore of display state across a power well toggle
3) get/put of display power well in critical places
The TODO list still has a few ite
For tracking current state.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_debugfs.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5fd6a5d..9f81e80 100644
--- a/drivers/gpu/drm/i915
We were missing a few bits around power well handling and Gunit
save/restore. The code added should be sufficient for runtime D3 as
well (though that requires additional changes to how we handle
save/restore of state).
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.c | 31
well ref will be tracked by the CRTC enable/disable code.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_dma.c | 2 ++
drivers/gpu/drm/i915/intel_display.c | 30 ++
2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers
Had to conditionalize some HSW bits and add virtual functions for
get/set on the power wells.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h | 10 +-
drivers/gpu/drm/i915/intel_drv.h| 2 +
drivers/gpu/drm/i915/intel_pm.c | 128 +++---
drivers/gpu
we'll end up in mode set functions that take more refs on the
power well.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_uncore.c | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm
On Tue, 15 Oct 2013 15:16:11 +0300
Imre Deak wrote:
> On Tue, 2013-10-15 at 11:06 +0300, Ville Syrjälä wrote:
> > On Mon, Oct 14, 2013 at 04:07:44PM -0700, Jesse Barnes wrote:
> > > This set adds bits needed for runtime power support, currently only
> > > lightly t
On Tue, 15 Oct 2013 16:54:00 -0300
Paulo Zanoni wrote:
> 2013/10/14 Jesse Barnes :
> > When accessing the display regs for hw state readout or cross check, we
> > need to make sure the power well is enabled so we can read valid
> > register state.
>
> On the current
On Tue, 15 Oct 2013 17:09:19 -0300
Paulo Zanoni wrote:
> 2013/10/14 Jesse Barnes :
> > If we disable the power well at runtime, we need to save enough display
> > state so we can restore it when the power well comes back again. Add
> > support for that on VLV by reusing so
On Tue, 15 Oct 2013 17:47:20 -0300
Paulo Zanoni wrote:
> 2013/10/15 Jesse Barnes :
> > On Tue, 15 Oct 2013 16:54:00 -0300
> > Paulo Zanoni wrote:
> >
> >> 2013/10/14 Jesse Barnes :
> >> > When accessing the display regs for hw state readout or cross ch
On Wed, 16 Oct 2013 14:10:13 +0300
Imre Deak wrote:
> On Tue, 2013-10-15 at 13:40 -0700, Jesse Barnes wrote:
> > On Tue, 15 Oct 2013 16:54:00 -0300
> > Paulo Zanoni wrote:
> > [...]
> > No that's taken into account here. In __intel_set_mode we take a
> >
)
> +#define POWER_DOMAIN_TRANSCODER(tran) \
> + ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
> + (tran) + POWER_DOMAIN_TRANSCODER_A)
>
> enum hpd_pin {
> HPD_NONE = 0,
Reviewed-by: Jesse Barnes
--
Jesse Barnes, Intel Open Source Technology Center
___
NSCODER_B:
> - case POWER_DOMAIN_TRANSCODER_C:
> - spin_lock_irq(&power_well->lock);
> - __intel_power_well_put(power_well);
> - spin_unlock_irq(&power_well->lock);
> - return;
> - default:
> - BUG();
> - }
> +
> + spin_lock_irq(&power_well->lock);
> + __intel_power_well_put(power_well);
> + spin_unlock_irq(&power_well->lock);
> }
>
> static struct i915_power_well *hsw_pwr;
Reviewed-by: Jesse Barnes
--
Jesse Barnes, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> static void intel_resume_power_well(struct drm_device *dev)
> @@ -5583,9 +5583,9 @@ static void intel_resume_power_well(struct drm_device
> *dev)
> if (!HAS_POWER_WELL(dev))
> return;
>
> - spin_lock_irq(&power_well->l
+{
> + modeset_update_power_wells(dev);
> hsw_update_package_c8(dev);
> }
>
Reviewed-by: Jesse Barnes
--
Jesse Barnes, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
eset_global_resources(struct drm_device *dev)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 189257d..63a5bfd 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -320,6 +320,7 @@ struct intel_cr
el_resume_power_well(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -5602,7 +5569,7 @@ void intel_init_power_well(struct drm_device *dev)
> return;
>
> /* For now, we need the power well to be always enable
On Mon, 28 Oct 2013 13:47:03 +0200
Jani Nikula wrote:
>
> FWIW there's nothing in the logs indicating it's a "graphics failure".
>
> BR,
> Jani.
>
>
> On Fri, 25 Oct 2013, "Wang, Stephanie" wrote:
> > [4.354140] rtc_cmos 00:00: alarms up to one month, y3k, 242 bytes
> > nvram, hpet irqs
The "drm_kms_helper" function is mentioned only because the kernel is
switching back to the text console when the panic occurs. It's not
actually the source of the panic.
The graphics driver does have some code for booting without any BIOS
support. But depending on the specific platform configur
For modifying self-refresh exit latency.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_sideband.c | 16
3 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915
Needed to support large panel resolutions.
Tested-by: Josh Triplett
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_display.c | 64
2 files changed, 66 insertions(+)
diff --git a/drivers/gpu/drm/i915
ns around these
> > places as needed and adjust the RPM refcount only as a consequence.
>
> I haven't read through the patches, but overall we should only get/put the
> most fine-grained power domain possible. If there's nesting going on (e.g.
> nested power wells, or different runtime pm states like pc8/D3/...) then
> the fine-grained power domains should in turn grab references for the next
> level up. So if someone grabs the aux display references to do edid reads
> (which on hsw disables pc8), this will also block D3. Same if we need one
> of the display power wells, that should in turn prevent pc8 (again on
> hsw).
>
> I know that the current code isn't there at all. But long-term this should
> be the direction imo, otherwise we'll have a giant mess between the
> runtime pm handling and the get/put callsites.
Yep, agreed. Fortunately Paulo has tested this and identified where
the get/puts belong, so now it's mainly a matter of figuring out which
power well needs to be referenced, rather than referencing the whole
device.
On other platforms we may need to add more get/puts if we have
new/different power wells, but let's start with HSW and work from there.
--
Jesse Barnes, Intel Open Source Technology Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
We don't want it delayed with the RPS work.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_pm.c | 31 ++-
1 file changed, 18 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bf
We don't want it delayed with the RPS work.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_pm.c | 31 ++-
1 file changed, 18 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bf
Needed to support large panel resolutions.
Tested-by: Josh Triplett
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_display.c | 64
2 files changed, 66 insertions(+)
diff --git a/drivers/gpu/drm/i915
For modifying self-refresh exit latency.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_sideband.c | 16
3 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915
arately and refcount them
like Ben has done with the per-fd work, though we could go back
to sharing a single fd and exposing the feature through the context
create ioctl instead, or possibly a new one if we need the notion of an
ASID as a separate entity.
--
Jesse Barnes, Intel Open Source Technolo
n't see massive churn causing false
positive breakage all the time. In other words, tests are just as
likely to be broken (reporting false breakage or false passing) as the
code they're testing. The best way to avoid that is to keep the tests
very small, simple, and targeted. Converting an
particular, we can probably start to
address some of the "technical debt" you mentioned, where the bar for a
rework is relatively high, requiring additional tests and
infrastructure scope.
--
Jesse Barnes, Intel Open Source Technology Center
__
bool enable);
>
> /* intel_dp.c */
> void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
> +bool intel_dp_init_typed(struct drm_device *dev, int output_reg,
> + enum port port, int type);
> bool intel_dp_init_connector(struct int
For modifying self-refresh exit latency.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_sideband.c | 16
3 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915
We don't want it delayed with the RPS work.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_pm.c | 31 ++-
1 file changed, 18 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a0
necessary.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_reg.h | 2 +
drivers/gpu/drm/i915/intel_display.c | 151 +++
2 files changed, 153 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 737d8a3
otherwise active pipes to get shut down for the
duration of the mode set, then restored at the end.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h | 12
drivers/gpu/drm/i915/intel_display.c | 7 +++
2 files changed, 19 insertions(+)
diff --git a/drivers/gpu
On Tue, 29 Oct 2013 17:10:11 -0700
Jesse Barnes wrote:
> On Tue, 29 Oct 2013 16:08:24 -0700
> Eric Anholt wrote:
>
> > Daniel Vetter writes:
> >
> > > Hi Ben
> > >
> > > So first things first: I rather like what the code looks like overall at
&
o split out these magic bits individually into
something readable? If not, I guess we'll have to trust you, but it
seems fragile.
Reviewed-by: Jesse Barnes
--
Jesse Barnes, Intel Open Source Technology Center
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On Fri, 1 Nov 2013 18:22:41 +0200
ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Reduce the eDP detection to just checking if it's port A, or if
> the VBT tells us that the port is eDP for the other ports.
>
> Suggested-by: Jesse Barnes
> Si
PORT_C);
> + intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
> PORT_C);
> }
>
Spurious whitespace change, but it's fine.
Reviewed-by: Jesse Barnes
--
Jesse Barnes, Intel Open Source Technology Center
__
necessary.
v2: use punit interface for 320 and 266 MHz CDclk adjustments (Ville)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_reg.h | 7 ++
drivers/gpu/drm/i915/intel_display.c | 175 +++
2 files changed, 182 insertions(+)
diff --git a/drivers/gpu
necessary.
v2: use punit interface for 320 and 266 MHz CDclk adjustments (Ville)
v3: reset GMBUS dividers too, since we changed CDclk (Ville)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_reg.h | 7 ++
drivers/gpu/drm/i915/intel_display.c | 178
otherwise active pipes to get shut down for the
duration of the mode set, then restored at the end.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h | 12
drivers/gpu/drm/i915/intel_display.c | 7 +++
2 files changed, 19 insertions(+)
diff --git a/drivers/gpu
On Fri, 1 Nov 2013 12:24:06 -0700
Jesse Barnes wrote:
> In some cases we may need to turn off more pipes than just the ones
> affected by a connector or encoder change, probably due to modifying
> some global resource that requires all pipes to shut down. Add a hook
> for this purp
necessary.
v2: use punit interface for 320 and 266 MHz CDclk adjustments (Ville)
v3: reset GMBUS dividers too, since we changed CDclk (Ville)
v4: jump to highest voltage when going to 400MHz CDclk (Jesse)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_reg.h | 7 ++
drivers/gpu/drm
On Fri, 1 Nov 2013 21:52:44 +0200
Ville Syrjälä wrote:
> On Fri, Nov 01, 2013 at 12:28:16PM -0700, Jesse Barnes wrote:
> > On VLV/BYT, we can adjust the CDclk frequency up or down based on the
> > max pixel clock we need to drive. Lowering it can save power, while
> > raisi
gt; +
> if (i915_semaphores >= 0)
> return i915_semaphores;
>
Reviewed-by: Jesse Barnes
Side note; for stuff like this where we disable a critical feature
(e.g. PPGTT, semaphores) with the intention of enabling it later, maybe
we should do a WARN or something if
We don't want it delayed with the RPS work.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_pm.c | 31 ++-
1 file changed, 18 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a0
)
drop new callback (Daniel)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_display.c | 179 +++
drivers/gpu/drm/i915/intel_i2c.c | 4 -
3 files changed, 185 insertions(+), 4 deletions(-)
diff --git a
;d still take the interrupts)
- use a polling scheme to evaluate busyness, and adjust the freq at a
fixed rate at specific times, maybe using a 60Hz timer or something
while the GPU is busy
--
Jesse Barnes, Intel Open Source Technology Center
_
For modifying self-refresh exit latency.
Reviewed-by: Ville Syrjälä
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_sideband.c | 16
3 files changed, 19 insertions(+)
diff
)
drop new callback (Daniel)
v6: fixup adjusted_mode.clock -> adjusted_mode.crtc_clock again (Ville)
document Bunit reg access better (Ville)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_reg.h | 9 ++
drivers/gpu/drm/i915/intel_display.c |
+
> + gen6_enable_rps_interrupts(dev);
> +
> + gen6_gt_force_wake_put(dev_priv);
> +}
> +
> static void gen6_enable_rps(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -4891,6 +4963,9 @@ static void intel_gen6_powersave_work(struct
>
intel_crtc_disable(&intel_crtc->base);
> ...
>
>
> Then things should just work (tm).
>
Yeah, good catch. It should be safe to push it that late since we
disable the prepare_pipes just after this point.
Maybe once we have atomic mode setting this will all get easier. :)
--
Jesse Barnes, Intel Open Source Technology Center
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)
drop new callback (Daniel)
v6: fixup adjusted_mode.clock -> adjusted_mode.crtc_clock again (Ville)
document Bunit reg access better (Ville)
v7: pass modeset_pipes and pipe_config to global_pipes so we get the right
clock data (Ville)
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i
On Tue, 5 Nov 2013 00:49:57 +0200
Ville Syrjälä wrote:
> On Mon, Nov 04, 2013 at 11:52:45AM -0800, Jesse Barnes wrote:
> > We don't want it delayed with the RPS work.
> >
> > Signed-off-by: Jesse Barnes
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 31
It's possible that the CCK clock could run at a different rate than the
DDR clock, so use the same method to get CCK as the GMBUS code does when
calculating the new CDclk divider in the VLV display code.
Reported-by: Ville Syrjälä
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm
Either the docs were wrong or the values have changed since the old days
before we had wheels.
Reported-by: Ville Syrjälä
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_pm.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915
t; +I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
> +
> + /* WaPsrDPRSUnmaskVBlankInSRD */
> + for_each_pipe(i) {
> + I915_WRITE(CHICKEN_PIPESL_1(i),
> +I915_READ(CHICKEN_PIPE
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