Avoid extra caching of the data.
Cc: José Roberto de Souza
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 26 +++
drivers/gpu/drm/i915/i915_drv.h | 1 -
2 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm
Move code around to avoid a forward declaration in the future.
Cc: José Roberto de Souza
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 154 +++---
1 file changed, 77 insertions(+), 77 deletions(-)
diff --git a/drivers/gpu/drm/i915/display
numbering.
Cc: José Roberto de Souza
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 49 +--
drivers/gpu/drm/i915/i915_drv.h | 2 -
2 files changed, 28 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b
We can finally remove the extra caching in ddi_port_info. Good riddance.
Cc: José Roberto de Souza
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 63 +--
drivers/gpu/drm/i915/i915_drv.h | 7 +--
2 files changed, 25 insertions(+), 45
ion bits in VBT that meet panel's request.
> Driver can refer to this setting then configure max brightness level
> in DCS backlight driver properly.
>
> v2: modify variable name brightness_precision_bits instead of
> max_brightness_level.
>
> Cc: Ville Syrjala
> C
On Tue, 24 Aug 2021, Ville Syrjälä wrote:
> On Mon, Aug 23, 2021 at 12:36:45PM +0300, Jani Nikula wrote:
>> The unsigned doesn't help us here.
>>
>> Cc: Ville Syrjälä
>> Suggested-by: Ville Syrjälä
>> Signed-off-by: Jani Nikula
>
> Reviewed-b
On Tue, 24 Aug 2021, Jani Nikula wrote:
> On Tue, 24 Aug 2021, Rodrigo Vivi wrote:
>> On Mon, Aug 23, 2021 at 03:25:30PM +0300, Jani Nikula wrote:
>>> Make some forward progress on reducing intel_display.c size.
>>>
>>> Jani Nikula (6):
>>
hat while applying.
The series is
Reviewed-by: Jani Nikula
>
> Ville Syrjälä (13):
> drm/i915: Set output_types to EDP for vlv/chv DPLL forcing
> drm/i915: Clean up gen2 DPLL readout
> drm/i915: Extract ilk_update_pll_dividers()
> drm/i915: Constify struct dpll all ov
drivers/gpu/drm/i915/intel_pch.h
> +++ b/include/drm/intel_pch.h
> @@ -84,6 +84,4 @@ enum intel_pch {
> #define HAS_PCH_NOP(dev_priv)
> (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
> #define HAS_PCH_SPLIT(dev_priv)
> (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
>
> -void intel_detect_pch(struct drm_i915_private *dev_priv);
> -
> #endif /* __INTEL_PCH__ */
--
Jani Nikula, Intel Open Source Graphics Center
p; PP_PCIE_DPM_MASK ?
> false : true;
> + data->pcie_dpm_key_disabled = intel_tgp_chk() || !(hwmgr->feature_mask
> & PP_PCIE_DPM_MASK);
> /* need to set voltage control types before EVV patching */
> data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE;
> data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE;
--
Jani Nikula, Intel Open Source Graphics Center
On Wed, 25 Aug 2021, Koba Ko wrote:
> On Wed, Aug 25, 2021 at 5:22 PM Jani Nikula
> wrote:
>>
>> On Wed, 25 Aug 2021, Koba Ko wrote:
>> > AMD polaris GPUs have an issue about audio noise on RKL platform,
>> > they provide a commit to fix but for SMU7-base
more?
BR,
Jani.
Cc: Lyude Paul
Jani Nikula (3):
drm/i915/backlight: extract backlight code to a separate file
drm/i915/backlight: mass rename functions to have intel_backlight_
prefix
drm/i915/panel: mass rename functions to have intel_panel_ prefix
drivers/gpu/drm/i91
In a long overdue refactoring, split out backlight code to new
intel_backlight.[ch]. Simple code movement, leave renames for follow-up
work. No functional changes.
Cc: Lyude Paul
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile |1 +
drivers/gpu/drm/i915/display
Follow the usual naming conventions. As a drive-by cleanup, also pass
intel_connector instead of drm_connector to intel_backlight_setup(). No
functional changes.
Cc: Lyude Paul
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/g4x_dp.c | 2 +-
drivers/gpu/drm/i915/display
Follow the usual naming conventions. Also pull HAS_GMCH() check to
intel_panel_fitting(). No functional changes.
Cc: Lyude Paul
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++--
drivers/gpu/drm/i915/display/intel_dp.c| 9 +++-
drivers/gpu/drm/i915
On Mon, 23 Aug 2021, Vandita Kulkarni wrote:
> Enable MIPI DSI support on ADL-P platform.
> The esc clock changes, WA changes are taken care
> in the previous patches.
> As per the Bspec the seq remains to be same as TGL.
>
> Signed-off-by: Vandita Kulkarni
Review
GL_DSI_CHKN_REG_0 0x6B0C0
> +#define _TGL_DSI_CHKN_REG_1 0x6B8C0
> +#define TGL_DSI_CHKN_REG(port) _MMIO_PORT(port,\
> + _TGL_DSI_CHKN_REG_0, \
> + _TGL_DSI
On Thu, 19 Aug 2021, Ville Syrjälä wrote:
> On Fri, Aug 13, 2021 at 01:43:20PM +0300, Jani Nikula wrote:
>> Extend the use of extended receiver cap at 0x2200 to cover
>> MAIN_LINK_CHANNEL_CODING_CAP in 0x2206, in case an implementation hides
>> the DP 2.0 128b/132b channel en
7;re using GEM_BUG_ON()
in generic driver code.
BR,
Jani.
> + if (init_funcs[i].exit)
> + init_funcs[i].exit();
> + }
> +}
--
Jani Nikula, Intel Open Source Graphics Center
The tables should be const arrays of const pointers, not just arrays of
const pointers.
Cc: Matt Roper
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_snps_phy.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display
Follow the usual naming conventions. While at it, fix i915_pci.h SPDX
license comment format and add header include guards.
Cc: Daniel Vetter
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_module.c | 4 ++--
drivers/gpu/drm/i915/i915_pci.c| 4 ++--
drivers/gpu/drm/i915
Axe more stuff from intel_display.c.
Jani Nikula (5):
drm/i915/fdi: move intel_update_fdi_pll_freq to intel_fdi.c
drm/i915/fdi: move fdi bc bifurcation functions to intel_fdi.c
drm/i915/fdi: move more FDI stuff to FDI link train hooks
drm/i915/fdi: move fdi mphy reset and programming to
Move FDI related functions to intel_fdi.c. Rename to have intel_fdi
prefix while at it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 18 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 16
drivers/gpu/drm/i915/display
Move FDI related functions to intel_fdi.c. Don't bother with renaming as
we'll make the functions static shortly.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 49
drivers/gpu/drm/i915/display/intel_fdi.
Accept slight duplication in the fdi link train hooks in exchange for
simplification in ilk_pch_enable(). This lets us make
ivb_update_fdi_bc_bifurcation() static again, now in intel_fdi.c.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 8 ---
drivers/gpu/drm
This fairly detailed stuff that really has no place in
intel_display.c. Combine the calls into one to avoid exposing both.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 102 +--
drivers/gpu/drm/i915/display/intel_fdi.c | 100
These shouldn't happen, but in the off chance they do, we'll want a
warning rather than panic.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_fdi.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
b/d
{
>> Local0 = CLID /* \_SB_.PC00.GFX0.CLID */
>> If ((0x8000 & Local0))
>> {
>> CLID &= 0x0F
>> GLID (CLID)
>>
t; comes.
Thanks!
BR,
Jani.
>
> On Wed, 2021-08-25 at 14:06 +0300, Jani Nikula wrote:
>> Extract the backlight code out of intel_panel.c, and rename the panel
>> and backlight functions according to usual conventions.
>>
>> Lyude, I haven't seen follow-ups on the
On Wed, 25 Aug 2021, Jani Nikula wrote:
> On Wed, 25 Aug 2021, Lyude Paul wrote:
>> Reviewed-by: Lyude Paul (assuming this still applies)
>>
>> As I mentioned on IRC pretty much all of the DPCD backlight helpers already
>> made it upstream. There are some changes I
On Wed, 25 Aug 2021, Rodrigo Vivi wrote:
> On Wed, Aug 25, 2021 at 06:06:23PM +0300, Jani Nikula wrote:
>> Follow the usual naming conventions. While at it, fix i915_pci.h SPDX
>> license comment format and add header include guards.
>>
>> Cc: Daniel Vetter
&g
add this kind of
checks in the middle of the generic functions. What if the type was bool
or ulong, where the generic function is a debugfs helper outside of
i915?
See the comment in i915_debugfs_params() that I added there exactly
because I envisioned someone was going to need this facility:
display.c | 3 +++
drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 4 +--
drivers/gpu/drm/i915/i915_module.c | 37 ++--
4 files changed, 30 insertions(+), 16 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center
On Wed, 25 Aug 2021, Matt Roper wrote:
> On Wed, Aug 25, 2021 at 05:58:11PM +0300, Jani Nikula wrote:
>> The tables should be const arrays of const pointers, not just arrays of
>> const pointers.
>>
>> Cc: Matt Roper
>> Signed-off-by: Jani Nikula
>
> R
On Wed, 25 Aug 2021, Jani Nikula wrote:
> On Thu, 19 Aug 2021, Ville Syrjälä wrote:
>> On Fri, Aug 13, 2021 at 01:43:20PM +0300, Jani Nikula wrote:
>>> Extend the use of extended receiver cap at 0x2200 to cover
>>> MAIN_LINK_CHANNEL_CODING_CAP in 0x2206, in case an i
Apparently the last reader of i915->active_pipes was removed with commit
ef79d62b5ce5 ("drm/i915: Encapsulate dbuf state handling harder"), and
now it's only ever written to. Remove it completely.
Cc: Stanislav Lisovskiy
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
dr
On Thu, 26 Aug 2021, Rodrigo Vivi wrote:
> On Wed, Aug 25, 2021 at 06:47:48PM +0300, Jani Nikula wrote:
>> Move FDI related functions to intel_fdi.c. Rename to have intel_fdi
>> prefix while at it.
>>
>> Signed-off-by: Jani Nikula
>
> Reviewed-by: Rodrigo Vivi
From: Animesh Manna
UHBR modes has higher link rate and added new values for programming
mpll of SNPS phy. No change in sequence, only the pll parameters
are different for UHBR modes.
Signed-off-by: Animesh Manna
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_snps_phy.c
On Fri, 27 Aug 2021, Ville Syrjälä wrote:
> On Thu, Aug 26, 2021 at 05:18:30PM +0300, Jani Nikula wrote:
>> Apparently the last reader of i915->active_pipes was removed with commit
>> ef79d62b5ce5 ("drm/i915: Encapsulate dbuf state handling harder"), and
>> now
On Fri, 27 Aug 2021, Jani Nikula wrote:
> From: Animesh Manna
>
> UHBR modes has higher link rate and added new values for programming
> mpll of SNPS phy. No change in sequence, only the pll parameters
> are different for UHBR modes.
>
> Signed-off-by: Animesh Manna
> Si
We need the DisplayID VESA vendor block data for properly configuring
eDP MSO (Multi-SST Operation) pixel overlap.
I haven't actually tested this on a panel that requires the overlap, but
this is all pretty straightforward to prepare for that use case.
BR,
Jani.
Jani Nikula (5):
drm/disp
Make the values easier to read. Also add DisplayID Structure version and
revision information (this is different from the spec version).
Signed-off-by: Jani Nikula
---
include/drm/drm_displayid.h | 57 +++--
1 file changed, 29 insertions(+), 28 deletions(-)
diff
tending it to parse also DisplayID data to
avoid requiring extra calls to update the information.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 63 +
include/drm/drm_connector.h | 12 +++
include/drm/drm_displayid.h | 11 +++
3 files c
MSO will require segment pixel overlap information from the
EDID. Postpone MSO init until after we've read and cached the EDID.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm
Now that we have MSO pixel overlap in display info, use it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
DisplayID v2.0 changes the data block identifiers and product types (now
called primary use cases).
Signed-off-by: Jani Nikula
---
include/drm/drm_displayid.h | 29 +
1 file changed, 29 insertions(+)
diff --git a/include/drm/drm_displayid.h b/include/drm
On Mon, 30 Aug 2021, Jani Nikula wrote:
> The VESA Organization Vendor-Specific Data Block, defined in VESA
> DisplayID Standard v2.0, specifies the eDP Multi-SST Operation (MSO)
> stream count and segment pixel overlap.
>
> DisplayID v1.3 has Appendix B: DisplayID as an
Some minor cleanupi of the display debugfs code.
BR,
Jani.
Jani Nikula (5):
drm/i915/debugfs: clean up LPSP status
drm/i915/debugfs: clean up LPSP capable
drm/i915/debugfs: register LPSP capability on all platforms
drm/i915/display: stop returning errors from debugfs registration
drm
Clean up the LPSP status printout. No functional changes.
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_debugfs.c | 37 ++-
1 file changed, 11 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu
Clean up the LPSP capability printout. No functional changes.
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_debugfs.c | 44 +++
1 file changed, 17 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers
The debugfs file shows it's not capable, don't duplicate the info.
Signed-off-by: Jani Nikula
---
.../gpu/drm/i915/display/intel_display_debugfs.c| 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
Failures to register debugfs should be ignored anyway, so stop
propagating errors altogether for clarity and simplicity. No functional
changes.
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_debugfs.c | 19 +--
.../drm/i915/display/intel_display_debugfs.h
Prefer the intel_ types. No functional changes.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_connector.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 3 ++-
drivers/gpu/drm/i915/display/intel_display_debugfs.h | 4 ++--
3 files changed, 5 insertions
Prefer the intel_ types. No functional changes.
v2: Fix build.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_connector.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 3 ++-
drivers/gpu/drm/i915/display/intel_display_debugfs.h | 6 +++---
3 files
On Mon, 30 Aug 2021, Ville Syrjälä wrote:
> On Mon, Aug 30, 2021 at 01:29:01PM +0300, Jani Nikula wrote:
>> The VESA Organization Vendor-Specific Data Block, defined in VESA
>> DisplayID Standard v2.0, specifies the eDP Multi-SST Operation (MSO)
>> stream count and
->aux.ddc);
if (edid) {
if (drm_add_edid_modes(connector, edid)) {
drm_connector_update_edid_property(connector, edid);
In any case, I think it's just plain wrong to use both the display and
opregion EDIDs at the same time. It's probably all around safer to start
with fallback.
P
box #5 [1]
>
> The first patch is based on Jani's patch series [2] adding support for
> the opregion, with changes. I've changed authorship, but I'd be glad to
> revert it
If you don't mind, please just add:
Co-developed-by: Jani Nikula
Thanks,
Jani.
>
> The
v2 of https://patchwork.freedesktop.org/series/94161/ with the VESA OUI
check and an OUI helper patch added.
Jani Nikula (6):
drm/displayid: re-align data block macros
drm/displayid: add DisplayID v2.0 data blocks and primary use cases
drm/edid: abstract OUI conversion to 24-bit int
drm
Make the values easier to read. Also add DisplayID Structure version and
revision information (this is different from the spec version).
Signed-off-by: Jani Nikula
---
include/drm/drm_displayid.h | 57 +++--
1 file changed, 29 insertions(+), 28 deletions(-)
diff
DisplayID v2.0 changes the data block identifiers and product types (now
called primary use cases).
Signed-off-by: Jani Nikula
---
include/drm/drm_displayid.h | 29 +
1 file changed, 29 insertions(+)
diff --git a/include/drm/drm_displayid.h b/include/drm
Replace the open coded OUI conversion from three bytes to a 24-bit int,
as we'll be adding one more user shortly. No functional changes.
Side note: CTA-861 format has the OUI bytes in reverse order.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 17 +++--
1
tending it to parse also DisplayID data to
avoid requiring extra calls to update the information.
v2: Check for VESA OUI (Ville)
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 72 +
include/drm/drm_connector.h | 12 +++
include/drm/drm_displa
MSO will require segment pixel overlap information from the
EDID. Postpone MSO init until after we've read and cached the EDID.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm
Now that we have MSO pixel overlap in display info, use it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_dp.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
On Tue, 31 Aug 2021, Jani Nikula wrote:
> On Mon, 30 Aug 2021, Ville Syrjälä wrote:
>> Don't we need to check the OUI to make sure the block is the right
>> type? I don't have the v2 spec at hand atm, but I presume a vendor
>> specific block could contai
On Thu, 12 Aug 2021, Animesh Manna wrote:
> HBR3 support for display gen11+ platform is depends upon some
> conditions which are mentioned below.
The series no longer applies, please rebase and resend.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
Accidentally dropped the else in a rebase fail, causing the DG2 max rate
to be overwritten later in the if ladder.
Fixes: e752d1f9c14a ("drm/i915/dg2: add DG2 UHBR source rates")
Cc: Manasi Navare
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/inte
st robot
> Cc: Ville Syrjala
> Cc: Jani Nikula
> Cc: Vandita Kulkarni
> Cc: Cooper Chiou
> Cc: William Tseng
> Signed-off-by: Lee Shawn C
> ---
> .../drm/i915/display/intel_dsi_dcs_backlight.c| 15 +--
> 1 file changed, 9 insertions(+), 6 deletions(
v2 of https://patchwork.freedesktop.org/series/93957/ with the CI issues
fixed (fingers crossed!).
BR,
Jani.
Jani Nikula (7):
drm/i915/bios: use hdmi level shift directly from child data
drm/i915/bios: use max tmds clock directly from child data
drm/i915/bios: use dp max link rate directly
Avoid extra caching of the data.
Cc: José Roberto de Souza
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 26 +--
drivers/gpu/drm/i915/i915_drv.h | 4
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu
Avoid extra caching of the data.
Cc: José Roberto de Souza
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 52 +++
drivers/gpu/drm/i915/i915_drv.h | 2 -
2 files changed, 26 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm
Avoid extra caching of the data.
Cc: José Roberto de Souza
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 28 ++-
drivers/gpu/drm/i915/i915_drv.h | 2 --
2 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm
Avoid extra caching of the data.
v2: Check for !info->devdata in intel_bios_port_aux_ch() (Ankit)
Cc: José Roberto de Souza
Cc: Ankit Nautiyal
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 26 +++
drivers/gpu/drm/i915/i915_drv.h |
numbering.
v2: Check !devdata in intel_bios_alternate_ddc_pin()
Cc: José Roberto de Souza
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 49 +--
drivers/gpu/drm/i915/i915_drv.h | 2 -
2 files changed, 28 insertions(+), 23 deletions(-)
diff
Move code around to avoid a forward declaration in the future.
Cc: José Roberto de Souza
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 154 +++---
1 file changed, 77 insertions(+), 77 deletions(-)
diff --git a/drivers/gpu/drm/i915/display
We can finally remove the extra caching in ddi_port_info. Good riddance.
v2: Rebased
Cc: José Roberto de Souza
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_bios.c | 63 +--
drivers/gpu/drm/i915/i915_drv.h | 7 +--
2 files changed, 25
On Wed, 01 Sep 2021, Rodrigo Vivi wrote:
> On Mon, Aug 30, 2021 at 03:53:43PM +0300, Jani Nikula wrote:
>> Failures to register debugfs should be ignored anyway, so stop
>> propagating errors altogether for clarity and simplicity. No functional
>> changes.
>
> not eve
On Wed, 01 Sep 2021, Rodrigo Vivi wrote:
> On Mon, Aug 30, 2021 at 03:53:44PM +0300, Jani Nikula wrote:
>> Prefer the intel_ types. No functional changes.
>>
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/display/intel_connector.c | 2 +-
On Wed, 01 Sep 2021, Imre Deak wrote:
> On Wed, Sep 01, 2021 at 02:28:15PM +0300, Jani Nikula wrote:
>> Accidentally dropped the else in a rebase fail, causing the DG2 max rate
>> to be overwritten later in the if ladder.
>>
>> Fixes: e752d1f9c14a ("drm/i91
On Wed, 01 Sep 2021, Rodrigo Vivi wrote:
> On Mon, Aug 30, 2021 at 03:53:41PM +0300, Jani Nikula wrote:
>> Clean up the LPSP capability printout. No functional changes.
>>
>> Signed-off-by: Jani Nikula
>
> Reviewed-by: Rodrigo Vivi
Thanks, pushed the first
ghtness value more easily.
>
> Reported-by: kernel test robot
> Cc: Ville Syrjala
> Cc: Jani Nikula
> Cc: Vandita Kulkarni
> Cc: Cooper Chiou
> Cc: William Tseng
> Signed-off-by: Lee Shawn C
Reviewed-by: Jani Nikula
> ---
> .../i915/display/intel_dsi_dcs_backlight
checked
> d2500f03aee8 drm/i915/dsi: Read/write proper brightness value via MIPI DCS
> command
>
>
--
Jani Nikula, Intel Open Source Graphics Center
On Wed, 01 Sep 2021, Jani Nikula wrote:
> v2 of https://patchwork.freedesktop.org/series/93957/ with the CI issues
> fixed (fingers crossed!).
José, I'd like to get an ack from you on this before applying. I know
it's bound conflict with your in flight series. Thoughts?
B
onnector [i915]] eDP
> DPCD: 04 fb ff
> <7>[8.234921] [drm:drm_dp_read_dpcd_caps] AUX A/DDI A/PHY A: Base DPCD:
> 14 0a 82 41 00 00 01 c0 02 00 00 00 0f 09 80
> <7>[8.234943] [drm:drm_dp_read_dpcd_caps] AUX A/DDI A/PHY A: DPCD: 14 0a
> 82 c1 00 00 01 c0 02 00 00 00 0f 09 80
Should try this in combination with [1]?
BR,
Jani.
[1]
https://patchwork.freedesktop.org/patch/msgid/20210719235927.283173-1-khaled.almahall...@intel.com
--
Jani Nikula, Intel Open Source Graphics Center
On Mon, 06 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
> This is the first step in an idea to refactor the display code
> into a bit more of a corner.
So, do we want to make i915->display a pointer?
If we do, and we're about to touch every place accessing the display
struct, we might jus
On Fri, 03 Sep 2021, "Souza, Jose" wrote:
> On Fri, 2021-09-03 at 14:04 +0300, Jani Nikula wrote:
>> José, I'd like to get an ack from you on this before applying. I know
>> it's bound conflict with your in flight series. Thoughts?
>
> If you a
On Thu, 26 Aug 2021, "Nautiyal, Ankit K" wrote:
> On 8/24/2021 7:04 PM, Jani Nikula wrote:
>> Avoid extra caching of the data.
>>
>> Cc: José Roberto de Souza
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/display/intel_bios.c
: %d (%lldns)\n",
> -rpprevup,
> -intel_gt_pm_interval_to_ns(&dev_priv->gt, rpprevup));
> - seq_printf(m, "Up threshold: %d%%\n",
> -rps->power.up_threshold);
> -
> - seq_printf(m, "RP CUR DOWN EI: %d (%lldns)\n",
> -rpdownei,
> -intel_gt_pm_interval_to_ns(&dev_priv->gt,
> - rpdownei));
> - seq_printf(m, "RP CUR DOWN: %d (%lldns)\n",
> -rpcurdown,
> -intel_gt_pm_interval_to_ns(&dev_priv->gt,
> - rpcurdown));
> - seq_printf(m, "RP PREV DOWN: %d (%lldns)\n",
> -rpprevdown,
> -intel_gt_pm_interval_to_ns(&dev_priv->gt,
> - rpprevdown));
> - seq_printf(m, "Down threshold: %d%%\n",
> -rps->power.down_threshold);
> -
> - max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
> - rp_state_cap >> 16) & 0xff;
> - max_freq *= (IS_GEN9_BC(dev_priv) ||
> - GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER :
> 1);
> - seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
> -intel_gpu_freq(rps, max_freq));
> -
> - max_freq = (rp_state_cap & 0xff00) >> 8;
> - max_freq *= (IS_GEN9_BC(dev_priv) ||
> - GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER :
> 1);
> - seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
> -intel_gpu_freq(rps, max_freq));
> -
> - max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
> - rp_state_cap >> 0) & 0xff;
> - max_freq *= (IS_GEN9_BC(dev_priv) ||
> - GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER :
> 1);
> - seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
> -intel_gpu_freq(rps, max_freq));
> - seq_printf(m, "Max overclocked frequency: %dMHz\n",
> -intel_gpu_freq(rps, rps->max_freq));
> -
> - seq_printf(m, "Current freq: %d MHz\n",
> -intel_gpu_freq(rps, rps->cur_freq));
> - seq_printf(m, "Actual freq: %d MHz\n", cagf);
> - seq_printf(m, "Idle freq: %d MHz\n",
> -intel_gpu_freq(rps, rps->idle_freq));
> - seq_printf(m, "Min freq: %d MHz\n",
> -intel_gpu_freq(rps, rps->min_freq));
> - seq_printf(m, "Boost freq: %d MHz\n",
> -intel_gpu_freq(rps, rps->boost_freq));
> - seq_printf(m, "Max freq: %d MHz\n",
> -intel_gpu_freq(rps, rps->max_freq));
> - seq_printf(m,
> -"efficient (RPe) frequency: %d MHz\n",
> -intel_gpu_freq(rps, rps->efficient_freq));
> - } else {
> - seq_puts(m, "no P-state info available\n");
> - }
> + struct drm_i915_private *i915 = node_to_i915(m->private);
> + struct intel_gt *gt = &i915->gt;
> + struct drm_printer p = drm_seq_file_printer(m);
>
> - seq_printf(m, "Current CD clock frequency: %d kHz\n",
> dev_priv->cdclk.hw.cdclk);
> - seq_printf(m, "Max CD clock frequency: %d kHz\n",
> dev_priv->max_cdclk_freq);
> - seq_printf(m, "Max pixel clock frequency: %d kHz\n",
> dev_priv->max_dotclk_freq);
> + debugfs_gt_pm_frequency_dump(gt, &p);
>
> - intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
> return 0;
> }
--
Jani Nikula, Intel Open Source Graphics Center
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
> This reworks the uncore function vtable so that it's constant.
There's a bug in there, see comment inline, with that fixed,
Reviewed-by: Jani Nikula
>
> Signed-off-by: Dave Airlie
> ---
> driv
d symmetrical, and the compiler will
inline the call away.
Other than that, and the fact that this fails to apply and thus doesn't
give us CI results,
Reviewed-by: Jani Nikula
>
> fw_domains_reset(uncore, uncore->fw_domains);
> assert_forcewakes_inactive(
rivers/gpu/drm/i915/intel_pm.h
> @@ -29,7 +29,6 @@ struct skl_wm_level;
> void intel_init_clock_gating(struct drm_i915_private *dev_priv);
> void intel_suspend_hw(struct drm_i915_private *dev_priv);
> int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
> -void intel_update_watermarks(struct drm_i915_private *dev_priv);
> void intel_init_pm(struct drm_i915_private *dev_priv);
> void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
> void intel_pm_setup(struct drm_i915_private *dev_priv);
--
Jani Nikula, Intel Open Source Graphics Center
priv)) {
> if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
> dev_priv->is_ddr3,
> @@ -8008,18 +8008,18 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
> dev_priv->fsb_freq, dev_priv->mem_freq);
> /* Disable CxSR and never update its watermark again */
> intel_set_memory_cxsr(dev_priv, false);
> - dev_priv->display.update_wm = NULL;
> + dev_priv->wm_disp.update_wm = NULL;
> } else
> - dev_priv->display.update_wm = pnv_update_wm;
> + dev_priv->wm_disp.update_wm = pnv_update_wm;
> } else if (DISPLAY_VER(dev_priv) == 4) {
> - dev_priv->display.update_wm = i965_update_wm;
> + dev_priv->wm_disp.update_wm = i965_update_wm;
> } else if (DISPLAY_VER(dev_priv) == 3) {
> - dev_priv->display.update_wm = i9xx_update_wm;
> + dev_priv->wm_disp.update_wm = i9xx_update_wm;
> } else if (DISPLAY_VER(dev_priv) == 2) {
> if (INTEL_NUM_PIPES(dev_priv) == 1)
> - dev_priv->display.update_wm = i845_update_wm;
> + dev_priv->wm_disp.update_wm = i845_update_wm;
> else
> - dev_priv->display.update_wm = i9xx_update_wm;
> + dev_priv->wm_disp.update_wm = i9xx_update_wm;
> } else {
> drm_err(&dev_priv->drm,
> "unexpected fall-through in %s\n", __func__);
--
Jani Nikula, Intel Open Source Graphics Center
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
> These are only used internally in the color module
I think this patch is a testament to my comment on wrappers for calling
vfuncs. It's all intel_color.c implementation details.
Reviewed-by: Jani Nikula
I might
odec_enable;
> + dev_priv->audio_funcs.audio_codec_disable =
> ilk_audio_codec_disable;
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7e5a8b1bbdd8..3e60bf8182e3 100644
> --- a/drivers/gpu/drm/i915/i915_d
tate->force_min_cdclk)
> *need_cdclk_calc = true;
>
> - ret = dev_priv->display.bw_calc_min_cdclk(state);
> + ret = dev_priv->cdclk_funcs.bw_calc_min_cdclk(state);
> if (ret)
> return ret;
>
> diff --git a/drivers/gpu
10 @@ struct drm_i915_display_cdclk_funcs {
> u8 (*calc_voltage_level)(int cdclk);
> };
>
> +struct drm_i915_irq_funcs {
Here, I'm a bit divided with the naming, irqs being more of i915 core,
even if serving display. I could go with intel_hotplug_funcs. *shrug*.
Reviewed-by:
rivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ece23401cb46..49b23ea46475 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -388,6 +388,11 @@ struct drm_i915_irq_funcs {
> void (*hpd_irq_setup)(struct drm_i
/i915/i915_drv.h
> @@ -393,6 +393,10 @@ struct drm_i915_fdi_link_train_funcs {
> const struct intel_crtc_state *crtc_state);
> };
>
> +struct drm_i915_dpll_funcs {
Nitpick, intel_dpll_funcs. Starting to spot the pattern? ;D
Part of the point is
On Wed, 08 Sep 2021, Dave Airlie wrote:
> From: Dave Airlie
>
> Avoid having writeable function pointers.
Would benefit from the call wrapper and naming.
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/d
pd_irq_setup;
> + dev_priv->irq_funcs = &icp_hpd_funcs;
> else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
> - dev_priv->irq_funcs.hpd_irq_setup = spt_hpd_irq_setup;
> + dev_priv->irq_funcs = &spt_hpd_funcs;
> else
> - dev_priv->irq_funcs.hpd_irq_setup = ilk_hpd_irq_setup;
> + dev_priv->irq_funcs = &ilk_hpd_funcs;
> }
> }
--
Jani Nikula, Intel Open Source Graphics Center
701 - 800 of 17407 matches
Mail list logo
