On Fri, 2014-04-11 at 08:55 +, Daniel Vetter wrote:
> On Thu, Apr 10, 2014 at 10:12:39AM +0000, Gupta, Sourab wrote:
> > On Wed, 2014-04-09 at 13:06 +, Daniel Vetter wrote:
> > > On Tue, Apr 08, 2014 at 06:53:03AM +0000, Gupta, Sourab wrote:
> > > > On Tue, 20
On Tue, 2014-04-01 at 10:53 +0530, sourab gupta wrote:
> On Tue, 2014-03-25 at 12:23 +0530, sourab gupta wrote:
> > On Mon, 2014-03-24 at 17:56 +, Lespiau, Damien wrote:
> > > On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gu...@intel.com wrote:
> > > > From: Akash Goel
> > > >
> > > > For
On Tue, 2014-05-06 at 11:34 +, Chris Wilson wrote:
> On Tue, May 06, 2014 at 04:40:58PM +0530, sourab.gu...@intel.com wrote:
> > From: Sourab Gupta
> >
> > This patch is in continuation of and is dependent on earlier patch
> > series to 'reduce the time for which device mutex is kept locked'.
On Tue, 2014-05-06 at 13:12 +, Chris Wilson wrote:
> On Tue, May 06, 2014 at 12:59:37PM +0000, Gupta, Sourab wrote:
> > On Tue, 2014-05-06 at 11:34 +, Chris Wilson wrote:
> > > On Tue, May 06, 2014 at 04:40:58PM +0530, sourab.gu...@intel.com wrote:
> >
On Tue, 2014-05-06 at 17:56 +, Eric Anholt wrote:
> sourab.gu...@intel.com writes:
>
> > From: Sourab Gupta
> >
> > This patch is in continuation of and is dependent on earlier patch
> > series to 'reduce the time for which device mutex is kept locked'.
> > (http://lists.freedesktop.org/archi
On Thu, 2014-05-15 at 12:27 +, Ville Syrjälä wrote:
> On Thu, May 15, 2014 at 11:47:37AM +0530, sourab.gu...@intel.com wrote:
> > From: Sourab Gupta
> >
> > Using MMIO based flips on Gen5+ for Media power well residency optimization.
> > The blitter ring is currently being used just for comma
On Fri, 2014-05-16 at 12:51 +, Ville Syrjälä wrote:
> On Fri, May 16, 2014 at 12:34:08PM +0000, Gupta, Sourab wrote:
> > On Thu, 2014-05-15 at 12:27 +, Ville Syrjälä wrote:
> > > On Thu, May 15, 2014 at 11:47:37AM +0530, sourab.gu...@intel.com wrote:
> >
On Tue, 2014-05-20 at 11:59 +, Chris Wilson wrote:
> On Tue, May 20, 2014 at 04:19:46PM +0530, sourab.gu...@intel.com wrote:
> > +int i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno);
>
> Be strict and add __must_check
>
We'll add this.
> > +static bool intel_use_mmio_flip(struc
On Thu, 2014-05-22 at 14:36 +, Gupta, Sourab wrote:
> From: Sourab Gupta
>
> This patch series replaces Blitter ring based flips with MMIO based flips.
> This is useful for Media power well residency optimization. These may be
> enabled on architectures where Render and
On Mon, 2014-04-14 at 10:22 +, Gupta, Sourab wrote:
> On Tue, 2014-04-01 at 10:53 +0530, sourab gupta wrote:
> > On Tue, 2014-03-25 at 12:23 +0530, sourab gupta wrote:
> > > On Mon, 2014-03-24 at 17:56 +, Lespiau, Damien wrote:
> > > > On Mon, Mar 24, 2014
On Wed, 2014-05-28 at 07:30 +, Chris Wilson wrote:
> On Wed, May 28, 2014 at 12:42:01PM +0530, sourab.gu...@intel.com wrote:
> > +static int intel_postpone_flip(struct drm_i915_gem_object *obj)
> > +{
> > + int ret;
> > +
> > + if (!obj->ring)
> > + return 0;
> > +
> > + if (i91
On Mon, 2014-04-14 at 09:45 +, Gupta, Sourab wrote:
> From: Akash Goel
>
> This workaround is needed on VLV for the HW context feature.
> It is used after adding the mi_set_context command in ring buffer
> for Hw context switch. As per the spec
> "The software must sen
On Mon, 2014-06-02 at 06:56 +, Chris Wilson wrote:
> On Sun, Jun 01, 2014 at 04:43:13PM +0530, sourab.gu...@intel.com wrote:
> > From: Sourab Gupta
> >
> > This patch enables the framework for using MMIO based flip calls,
> > in contrast with the CS based flip calls which are being used curre
On Wed, 2014-05-28 at 15:27 +0530, sourab gupta wrote:
> On Mon, 2014-04-14 at 09:45 +0000, Gupta, Sourab wrote:
> > From: Akash Goel
> >
> > This workaround is needed on VLV for the HW context feature.
> > It is used after adding the mi_set_context command in rin
On Tue, 2014-06-10 at 07:24 +, Chris Wilson wrote:
> On Tue, Jun 10, 2014 at 12:48:44PM +0530, sourab.gu...@intel.com wrote:
> > From: Akash Goel
> >
> > Removed the unconditional cross engine/ring update of MBOX registers.
> > The MBox update will done only when needed when the actual inter
chris-wilson.co.uk]
Sent: Wednesday, March 05, 2014 5:19 PM
To: Gupta, Sourab
Cc: intel-gfx@lists.freedesktop.org; Vetter, Daniel; Barnes, Jesse; Wilson,
Chris; Goel, Akash
Subject: Re: [RFC 3/3] drm/i915: Add the truncation logic for Stolen objects.
On Wed, Mar 05, 2014 at 05:05:40PM +0530, sour
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Wednesday, March 05, 2014 6:15 PM
To: Gupta, Sourab
Cc: intel-gfx@lists.freedesktop.org; Vetter, Daniel; Barnes, Jesse; Wilson,
Chris; Goel, Akash
Subject: Re: [RFC 3/3] drm/i915: Add the truncation logic for Stolen objects.
On We
the madvise ioctl
Thanks,
Sourab
-Original Message-
From: Vetter, Daniel
Sent: Thursday, March 06, 2014 1:18 AM
To: Gupta, Sourab; Chris Wilson
Cc: intel-gfx@lists.freedesktop.org; Barnes, Jesse; Wilson, Chris; Goel, Akash
Subject: Re: [RFC 3/3] drm/i915: Add the truncation logic for St
: Gupta, Sourab; Chris Wilson
Cc: intel-gfx@lists.freedesktop.org; Barnes, Jesse; Wilson, Chris; Goel, Akash
Subject: Re: [RFC 3/3] drm/i915: Add the truncation logic for Stolen objects.
On 06/03/2014 10:39, Gupta, Sourab wrote:
> Hi Daniel,
>
> We had also considered the two points
chris-wilson.co.uk]
Sent: Friday, March 07, 2014 3:32 PM
To: Gupta, Sourab
Cc: intel-gfx@lists.freedesktop.org; Vetter, Daniel; Wilson, Chris
Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915: Memory node free handling on
truncation of stolen obj
On Fri, Mar 07, 2014 at 03:29:27PM +0530, sourab.gu...@inte
[mailto:ch...@chris-wilson.co.uk]
Sent: Friday, March 07, 2014 3:36 PM
To: Gupta, Sourab
Cc: intel-gfx@lists.freedesktop.org; Vetter, Daniel; Wilson, Chris; Goel, Akash
Subject: Re: [PATCH 1/3] drm/i915: Added a new 'I915_CPU_MAP_NOT_NEEDED' flag
to gem_create ioctl.
On Fri, Mar 07, 2014 at
Hi Daniel/Chris,
> As Chris said, instead of rolling your own code to track when flips are
> emitted to the ring simply add a real request (with the add_request function)
> like the execbuf paths.Then add any additional trackin you need to our
> request structure.
We can use the 'add_request'
ifferent version of ioctl
structures in this case. But this may not be the desired behaviour
Can you provide your opinion regarding the above approaches.
Regards,
Sourab
-Original Message-
From: Gupta, Sourab
Sent: Friday, March 07, 2014 4:26 PM
To: Chris Wilson
Cc: intel-gfx@lists.fre
Hi Ville,
Can you please review the below patch.
Regards,
Sourab
-Original Message-
From: Gupta, Sourab
Sent: Thursday, March 13, 2014 2:32 PM
To: intel-gfx@lists.freedesktop.org
Cc: Gupta, Sourab; Ville Syrjälä; Daniel Vetter; Chris Wilson; Goel, Akash
Subject: [PATCH v2] drm/i915
On Mon, 2014-03-10 at 22:07 +, 'Chris Wilson' wrote:
> On Mon, Mar 10, 2014 at 04:12:23PM +, Gupta, Sourab wrote:
> >
> > Hi Chris,
> >
> > For the issue mentioned by you ( regarding botching up ioctls), we
> > understand that this is related
On Fri, 2014-02-07 at 12:22 +, Goel, Akash wrote:
> From: Akash Goel
>
> Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'.
> In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI
> Store data commands.
>
> v2: Modified the WA comment. (Ville)
>
>
On Wed, 2014-01-22 at 11:11 +, Chris Wilson wrote:
> On Wed, Jan 22, 2014 at 12:54:51PM +0200, Ville Syrjälä wrote:
> > On Wed, Jan 22, 2014 at 09:15:06AM +0530, akash.g...@intel.com wrote:
> > > From: Akash Goel
> > >
> > > Added a new rendering specific Workaround 'WaReadAfterWriteHazard'.
>
On Fri, 2014-03-21 at 12:58 +, Chris Wilson wrote:
> On Fri, Mar 21, 2014 at 06:05:04PM +0530, sourab.gu...@intel.com wrote:
> > From: Akash Goel
> >
> > This patch Enables the bit for TLB invalidate in GFX Mode register.
> >
> > According to bspec, When enabled this bit limits the invalida
On Fri, 2014-03-21 at 13:17 +, Chris Wilson wrote:
> On Fri, Mar 21, 2014 at 01:09:12PM +0000, Gupta, Sourab wrote:
> > On Fri, 2014-03-21 at 12:58 +, Chris Wilson wrote:
> > > On Fri, Mar 21, 2014 at 06:05:04PM +0530, sourab.gu...@intel.com wrote:
> &
On Mon, 2014-03-17 at 15:15 +0530, sourab gupta wrote:
> On Mon, 2014-03-10 at 22:07 +, 'Chris Wilson' wrote:
> > On Mon, Mar 10, 2014 at 04:12:23PM +, Gupta, Sourab wrote:
> > >
> > > Hi Chris,
> > >
> > > For the iss
On Fri, 2014-03-21 at 15:15 +, Daniel Vetter wrote:
> On Fri, Mar 21, 2014 at 06:02:36PM +0530, sourab.gu...@intel.com wrote:
> > From: Akash Goel
> >
> > Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'.
> > In this WA, before pipecontrol with TLB invalidate set, ne
On Fri, 2014-03-21 at 14:58 +, Daniel Vetter wrote:
> On Fri, Mar 21, 2014 at 11:53:40AM +0000, Gupta, Sourab wrote:
> > On Wed, 2014-01-22 at 11:11 +, Chris Wilson wrote:
> > > On Wed, Jan 22, 2014 at 12:54:51PM +0200, Ville Syrjälä wrote:
> > > > On Wed, Ja
Hi Ville,
Can you provide your feedback on this patch.
Waiting for your response.
Regards,
Sourab
-Original Message-
From: Gupta, Sourab
Sent: Monday, March 17, 2014 10:04 AM
To: Syrjala, Ville
Cc: Daniel Vetter; Chris Wilson; Goel, Akash; intel-gfx@lists.freedesktop.org
Subject: RE
his looks fine. It clears the confusion around TLB INVALIDATE Bit.
We'll be developing our patch on top of this and sending the full series
of WA patches for VLV.
> Signed-off-by: Chris Wilson
> Cc: "Gupta, Sourab"
> ---
> Alternatively, we could call it GFX_TLB_INVAL
On Fri, 2014-03-21 at 16:52 +, Chris Wilson wrote:
> On Fri, Mar 21, 2014 at 08:58:08PM +0530, sourab.gu...@intel.com wrote:
> > From: Akash Goel
> >
> > This patch Enables the bit for TLB invalidate in GFX Mode register.
> >
> > According to bspec, When enabled this bit limits the invalida
On Sat, 2014-03-22 at 11:23 +, Daniel Vetter wrote:
> On Sat, Mar 22, 2014 at 03:29:11AM +0000, Gupta, Sourab wrote:
> > On Fri, 2014-03-21 at 17:18 +, Chris Wilson wrote:
> > > The documentation calls this GFX_MODE bit "Flush TLB invalidate Mode".
> >
On Mon, 2014-03-24 at 09:35 +, Daniel Vetter wrote:
> On Mon, Mar 24, 2014 at 12:19:18PM +0530, sourab.gu...@intel.com wrote:
> > From: Sourab Gupta
> >
> > This patch series adds rendering specific HW workarounds for VLV platform.
> > These patches leads to stable behavior on VLV, especially
On Mon, 2014-03-24 at 09:31 +, Daniel Vetter wrote:
> On Mon, Mar 24, 2014 at 12:19:20PM +0530, sourab.gu...@intel.com wrote:
> > From: Akash Goel
> >
> > This workaround is needed on VLV for the HW context feature.
> > It is used after adding the mi_set_context command in ring buffer
> > for
On Mon, 2014-03-24 at 09:32 +, Chris Wilson wrote:
> On Mon, Mar 24, 2014 at 12:19:19PM +0530, sourab.gu...@intel.com wrote:
> > From: Akash Goel
> >
> > Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'.
> > In this WA, before pipecontrol with TLB invalidate set, nee
On Mon, 2014-03-24 at 17:47 +, Chris Wilson wrote:
> On Mon, Mar 24, 2014 at 11:00:05PM +0530, sourab.gu...@intel.com wrote:
> > From: Akash Goel
> >
> > Removing the VS_TIMER_DISPATCH bit enable for MI MODE reg for
> > VLV platform as it is not required.
> >
> > Signed-off-by: Akash Goel
>
On Mon, 2014-03-24 at 18:47 +, Chris Wilson wrote:
> On Mon, Mar 24, 2014 at 08:32:30PM +0200, Ville Syrjälä wrote:
> > On Mon, Mar 24, 2014 at 11:20:40AM +0000, Gupta, Sourab wrote:
> > > On Mon, 2014-03-24 at 09:32 +, Chris Wilson wrote:
> > > > On Mon, Ma
On Mon, 2014-03-24 at 17:56 +, Lespiau, Damien wrote:
> On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gu...@intel.com wrote:
> > From: Akash Goel
> >
> > For disabling L3 clock gating we need to set bit 25 of MMIO
> > register 940c. Earlier this was being done by just writing 1
> > into bi
On Tue, 2014-03-25 at 09:15 +, Chris Wilson wrote:
> On Tue, Mar 25, 2014 at 02:01:05PM +0530, sourab.gu...@intel.com wrote:
> > From: Akash Goel
> >
> > Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'.
> > This workaround has to be applied before doing TLB Invalida
On Tue, 2014-03-25 at 10:59 +, Chris Wilson wrote:
> On Tue, Mar 25, 2014 at 03:23:34PM +0530, sourab.gu...@intel.com wrote:
> > From: Akash Goel
> >
> > Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'.
> > This workaround has to be applied before doing TLB Invalida
Hi Ville/Damien,
Can you please review the below patch(v3) for mmio flips.
Thanks,
Sourab
On Sun, 2014-03-23 at 09:01 +, Gupta, Sourab wrote:
> From: Sourab Gupta
>
> Using MMIO based flips on VLV for Media power well residency optimization.
> The blitter ring is currently bei
On Wed, 2014-03-26 at 07:54 +, Chris Wilson wrote:
> On Wed, Mar 26, 2014 at 05:14:05AM +0000, Gupta, Sourab wrote:
> > On Tue, 2014-03-25 at 10:59 +, Chris Wilson wrote:
> > > On Tue, Mar 25, 2014 at 03:23:34PM +0530, sourab.gu...@intel.com wrote:
> &
On Mon, 2014-03-24 at 17:30 +, Gupta, Sourab wrote:
> From: Akash Goel
>
> This patch Enables the bit for TLB invalidate in GFX Mode register
> for Gen7.
>
> According to bspec, When enabled this bit limits the invalidation
> of the TLB only to batch buffer bounda
On Tue, 2014-03-25 at 12:23 +0530, sourab gupta wrote:
> On Mon, 2014-03-24 at 17:56 +, Lespiau, Damien wrote:
> > On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gu...@intel.com wrote:
> > > From: Akash Goel
> > >
> > > For disabling L3 clock gating we need to set bit 25 of MMIO
> > > regis
On Wed, 2014-03-26 at 13:20 +0530, sourab gupta wrote:
> Hi Ville/Damien,
> Can you please review the below patch(v3) for mmio flips.
> Thanks,
> Sourab
>
> On Sun, 2014-03-23 at 09:01 +0000, Gupta, Sourab wrote:
> > From: Sourab Gupta
> >
> > Using MMIO bas
On Thu, 2014-04-03 at 14:11 +0530, sourab gupta wrote:
> On Wed, 2014-03-26 at 13:20 +0530, sourab gupta wrote:
> > Hi Ville/Damien,
> > Can you please review the below patch(v3) for mmio flips.
> > Thanks,
> > Sourab
> >
> > On Sun, 2014-03-23 at 09:01
memory pressure to trigger stolen eviction nor
> any purgeable objects inside the stolen arena. However, this will change
> in the near future, and so better management and defragmentation of
> stolen memory will become a real issue.
>
> Signed-off-by: Chris Wilson
> Cc: &q
On Mon, 2014-03-24 at 17:30 +, Gupta, Sourab wrote:
> From: Akash Goel
>
> This workaround is needed on VLV for the HW context feature.
> It is used after adding the mi_set_context command in ring buffer
> for Hw context switch. As per the spec
> "The software must sen
On Tue, 2014-04-08 at 06:45 +, Chris Wilson wrote:
> On Tue, Apr 08, 2014 at 04:32:02AM +0000, Gupta, Sourab wrote:
> > Hi Rodrigo,
> > In this patch, while freeing the purgeable stolen object, the memory
> > node also has to be freed, so as to make space for new object
On Wed, 2014-04-09 at 13:06 +, Daniel Vetter wrote:
> On Tue, Apr 08, 2014 at 06:53:03AM +0000, Gupta, Sourab wrote:
> > On Tue, 2014-04-08 at 06:45 +, Chris Wilson wrote:
> > > On Tue, Apr 08, 2014 at 04:32:02AM +0000, Gupta, Sourab wrote:
> > > > Hi Rodrigo
On Fri, 2014-06-20 at 10:02 +, Gupta, Sourab wrote:
> From: Sourab Gupta
>
> This patch series introduces a new gem create ioctl for user specified
> placement.
>
> Despite being a unified memory architecture (UMA) some bits of memory
> are more equal than others. In p
On Tue, 2014-06-10 at 20:15 +0530, sourab gupta wrote:
> On Tue, 2014-06-10 at 07:24 +, Chris Wilson wrote:
> > On Tue, Jun 10, 2014 at 12:48:44PM +0530, sourab.gu...@intel.com wrote:
> > > From: Akash Goel
> > >
> > > Removed the unconditional cross engine/ring update of MBOX registers.
> >
On Sun, 2014-07-06 at 18:29 +0530, sourab gupta wrote:
> On Fri, 2014-06-20 at 10:02 +0000, Gupta, Sourab wrote:
> > From: Sourab Gupta
> >
> > This patch series introduces a new gem create ioctl for user specified
> > placement.
> >
> > Despite being a
On Mon, 2015-06-22 at 16:09 +, Daniel Vetter wrote:
> On Mon, Jun 22, 2015 at 02:22:54PM +0100, Chris Wilson wrote:
> > On Mon, Jun 22, 2015 at 03:25:07PM +0530, sourab.gu...@intel.com wrote:
> > > From: Sourab Gupta
> > >
> > > To collect timestamps around any GPU workload, we need to insert
On Thu, 2015-06-25 at 07:42 +, Daniel Vetter wrote:
> On Thu, Jun 25, 2015 at 06:02:35AM +0000, Gupta, Sourab wrote:
> > On Mon, 2015-06-22 at 16:09 +, Daniel Vetter wrote:
> > > On Mon, Jun 22, 2015 at 02:22:54PM +0100, Chris Wilson wrote:
> > > > On Mon, Ju
On Wed, 2015-07-15 at 09:40 +, Chris Wilson wrote:
> On Wed, Jul 15, 2015 at 02:21:40PM +0530, sourab.gu...@intel.com wrote:
> > From: Sourab Gupta
> >
> > This patch adds the mechanism for forwarding the timestamp data to
> > userspace using the Gen PMU perf event interface.
> >
> > The tim
On Wed, 2015-08-05 at 09:22 +, Chris Wilson wrote:
> On Wed, Aug 05, 2015 at 11:25:37AM +0530, sourab.gu...@intel.com wrote:
> > +static void gen_buffer_destroy(struct drm_i915_private *i915)
> > +{
> > + mutex_lock(&i915->dev->struct_mutex);
> > + vunmap(i915->gen_pmu.buffer.addr);
> > +
On Wed, 2015-08-05 at 09:38 +, Chris Wilson wrote:
> On Wed, Aug 05, 2015 at 11:25:37AM +0530, sourab.gu...@intel.com wrote:
> > From: Sourab Gupta
> >
> > The current perf PMU driver is specific for collection of OA counter
> > statistics (which may be done in a periodic or asynchronous way)
On Wed, 2015-08-05 at 15:17 +0530, sourab gupta wrote:
> On Wed, 2015-08-05 at 09:38 +, Chris Wilson wrote:
> > On Wed, Aug 05, 2015 at 11:25:37AM +0530, sourab.gu...@intel.com wrote:
> > > From: Sourab Gupta
> > >
> > > The current perf PMU driver is specific for collection of OA counter
> >
On Wed, 2015-08-05 at 09:30 +, Chris Wilson wrote:
> On Wed, Aug 05, 2015 at 11:25:40AM +0530, sourab.gu...@intel.com wrote:
> > From: Sourab Gupta
> >
> > This patch adds the routines through which one can insert commands in the
> > ringbuf for capturing timestamps, which are used to insert
On Wed, 2015-08-05 at 10:03 +, Chris Wilson wrote:
> On Wed, Aug 05, 2015 at 11:25:44AM +0530, sourab.gu...@intel.com wrote:
> > From: Sourab Gupta
> >
> > This patch adds support for retrieving MMIO register values alongwith
> > timestamps and forwarding them to userspace through perf.
> > T
On Wed, 2015-08-05 at 10:30 +, Chris Wilson wrote:
> On Wed, Aug 05, 2015 at 10:18:50AM +0000, Gupta, Sourab wrote:
> > On Wed, 2015-08-05 at 10:03 +, Chris Wilson wrote:
> > > On Wed, Aug 05, 2015 at 11:25:44AM +0530, sourab.gu...@intel.com wrote:
> >
On Wed, 2014-09-03 at 10:58 +, Daniel Vetter wrote:
> On Wed, Sep 03, 2014 at 03:39:55PM +0530, sourab.gu...@intel.com wrote:
> > From: Sourab Gupta
> >
> > Currently the Graphics Driver provides an interface through which
> > one can get a snapshot of the overall Graphics memory consumption.
On Thu, 2014-09-04 at 10:01 +, Daniel Vetter wrote:
> On Thu, Sep 4, 2014 at 9:03 AM, Gupta, Sourab wrote:
> > On Wed, 2014-09-03 at 13:09 +, Daniel Vetter wrote:
> >> On Wed, Sep 03, 2014 at 11:49:52AM +0000, Gupta, Sourab wrote:
> >> > On Wed, 2014-09-03
68 matches
Mail list logo
