[Intel-gfx] [PATCH 17/37] drm/i915: add SSC offsets for SBI access

Different registers are identified by their target id and offset. To simplify their programming, they are called as . For example, SSCCTL register accessed through SBI at target id 6 and offset 0c is called SBI_SSCCTL6. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 15

[Intel-gfx] [PATCH 37/37] drm/i915: dump registers read/write ops

other words, this is ugly, but if you run into an issue and send me dmesg with those included, my chances of investigating the problems will increase exponentially. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_drv.c |2 ++ drivers/gpu/drm/i915/intel_display.c |2 ++ 2

[Intel-gfx] [PATCH 14/37] drm/i915: add PIXCLK_GATE register

Pixel clock gating control for Lynx point. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h |6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4ee8965..9ff9856 100644 --- a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 22/37] drm/i915: program WM_LINETIME on Haswell

The line time can be programmed according to the number of horizontal pixels vs effective pixel rate ratio. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers

[Intel-gfx] [PATCH 16/37] drm/i915: add port clock selection support for HSW

Multiple clocks can drive different outputs. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 23 +++ 1 file changed, 23 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e38dafc..eebe9d3 100644 --- a

[Intel-gfx] [PATCH 23/37] drm/i915: do not set 6BPP dithering on haswell

We don't have those bits on Haswell anymore, so do not set them. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c |5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] [PATCH 21/37] drm/i915: calculate watermarks on Gen7 archs in one place

Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c225de4..46633fe 100644 --- a/drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] [PATCH 31/37] drm/i915: enable PCH earlier

The modesetting sequence for PCH-related connections mentions that the order of plane/pipe enablement could happen either before of after PCH enablement. With LPT, however, we need to enable some things earlier to be able to talk to PCH. So let's do it a bit in advance. Signed-off-by: E

[Intel-gfx] [PATCH 12/37] drm/i915: add SBI registers

Those are responsible for the Sideband Interface programming. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0af47b4..4ee8965 100644 --- a

[Intel-gfx] [PATCH 20/37] drm/i915: add WM_LINETIME registers

Watermark line time registers for display low power watermark. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index fa9e3a8..76f7acb 100644

[Intel-gfx] [PATCH 10/37] drm/i915: add definition of LPT FDI port width registers

Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h |3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2927460..b732aa1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH 27/37] drm/i915: share pipe count handling with Ivybridge

Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 27ab70d..2978597 100644 --- a/drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] [PATCH 25/37] drm/i915: haswell has 3 pipes as well

They work differently, but the count is the same. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_dma.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 9341eb8..a2c0e75 100644 --- a

[Intel-gfx] [PATCH 33/37] drm/i915: double-write DDI translation table

Some double-buffered registers need to be written twice. Note that it is being sent as a separate patch because sometimes these registers do work when written only once. But double-writing on my machine ensured that they work more often. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 28/37] drm/i915: share IVB cursor routine with Haswell

Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 2978597..3b3dc15 100644 --- a/drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] [PATCH 11/37] drm/i915: add definition of DDI buffer translations regs

Those registers are used to train DDI buffer translations for each link type. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h |7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b732aa1..0af47b4

[Intel-gfx] [PATCH 30/37] drm/i915: disable rc6 on haswell for now

This needs proper enablement to avoid machine hangs, so let's just avoid it for now. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c |4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_disp

[Intel-gfx] [PATCH 13/37] drm/i915: add support for SBI ops

With Lynx Point, we need to use SBI to communicate with the display clock control. This commit adds helper functions to access the registers via SBI. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c | 44 ++ 1 file changed, 44 insertions

[Intel-gfx] [PATCH 29/37] drm/i915: enable power wells on haswell init

This attempts to enable all the available power wells during the initialization. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c | 31 +++ 1 file changed, 31 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm

[Intel-gfx] [PATCH 18/37] drm/i915: add GTC registers

Add Global Time Clock registers Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h |5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 193fb11..03fb10d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH 19/37] drm/i915: add LCPLL control registers

Those are used to control the display core clock. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_reg.h |7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 03fb10d..fa9e3a8 100644 --- a/drivers/gpu/drm

[Intel-gfx] [PATCH 35/37] drm/i915: program iCLKIP on Lynx Point

calculate those values manually in case no match is found. But I don't think we'll encounter a mode not covered by those table, and VGA is pretty much going away in the future anyway. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c | 309 +++

[Intel-gfx] [PATCH 24/37] drm/i915: share forcewaking code between IVB and HSW

Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 24a0a6c..27ab70d 100644 --- a/drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] [PATCH 26/37] drm/i915: reuse Ivybridge interrupts code for Haswell

Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_irq.c |6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index afd4e03..ede51f0 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu

Re: [Intel-gfx] [PATCH 23/37] drm/i915: do not set 6BPP dithering on haswell

On Thu, Mar 22, 2012 at 07:16, Daniel Vetter wrote: > On Wed, Mar 21, 2012 at 10:09:58PM -0300, Eugeni Dodonov wrote: > > We don't have those bits on Haswell anymore, so do not set them. > > > > Signed-off-by: Eugeni Dodonov > > Hm, how is 6bpp dithering suppos

Re: [Intel-gfx] [PATCH 26/37] drm/i915: reuse Ivybridge interrupts code for Haswell

On Thu, Mar 22, 2012 at 07:22, Daniel Vetter wrote: > On Wed, Mar 21, 2012 at 10:10:01PM -0300, Eugeni Dodonov wrote: > > Signed-off-by: Eugeni Dodonov > > Hm, I have a feeling that some of these s/IS_IVB/IS_GEN7/ checks will > collide with the vlv code. I guess neither Jesse

Re: [Intel-gfx] [PATCH 07/37] drm/i915: add DP_TP_CTL registers

On Thu, Mar 22, 2012 at 07:43, Chris Wilson wrote: > On Wed, 21 Mar 2012 22:09:42 -0300, Eugeni Dodonov < > eugeni.dodo...@intel.com> wrote: > > This is one set of those registers for each pipe. > Would these not benefit from a #define DP_TP_CTL(pipe)? > Sorry, my typo we

Re: [Intel-gfx] [PATCH] drm/i915: Sanitize BIOS debugging bits from PIPECONF

ted by the latest VBIOS update on Ivy Bridge which resulted in somewhat strange display issues, could you please test this patch and verify if it fixes the issue for you? -- Eugeni Dodonov <http://eugeni.dodonov.net/> ___ Intel-gfx mailing li

[Intel-gfx] [PATCH 0/2] RC6 changes for 3.4 got missing

any). And with this, we'll complete the lets-try-rc6-by-default-one-more-time saga. Eugeni Dodonov (2): drm/i915: allow to select rc6 modes via kernel parameter drm/i915: enable plain RC6 on Sandy Bridge by default drivers/gpu/drm/i915/i915_drv.c |6 +- drivers/gpu/drm/i915/i9

[Intel-gfx] [PATCH 1/2] drm/i915: allow to select rc6 modes via kernel parameter

://bugs.freedesktop.org/show_bug.cgi?id=42579 Reviewed-by: Chris Wilson Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/i915_drv.c |6 +- drivers/gpu/drm/i915/i915_drv.h | 21 + drivers/gpu/drm/i915/intel_display.c | 20 3 files changed, 42

[Intel-gfx] [PATCH 2/2] drm/i915: enable plain RC6 on Sandy Bridge by default

.cgi?id=44867 Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c |8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c6d8bc4..dcae2c9 100644 --- a/drivers/gpu/drm/i915/i

Re: [Intel-gfx] [PATCH] drm/i915: add rc6 residency times to debugfs

5cb972cc94f1fbd9882d4e5c2e72ac43 . But if it makes sense to include it into kernel as well, why not? Reviewed-by: Eugeni Dodonov -- Eugeni Dodonov <http://eugeni.dodonov.net/> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH 25/26] drm/i915: disable turbo on ValleyView for now

hese platforms do have turbo, but it is simple not ready to be enabled yet by default. So for me, Reviewed-by: Eugeni Dodonov -- Eugeni Dodonov <http://eugeni.dodonov.net/> ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.

Re: [Intel-gfx] [PATCH 18/26] drm/i915: add ValleyView specific CRT detect function

l return code into intel_crt_detect_hotplug() block? Or maybe add a /* FIXME */ comment at least? Otherwise, it feel that it could be too error-prone to leave this assignment here by itself. Other than that, it looks correct to me. Reviewed-by: Eugeni Dodo

Re: [Intel-gfx] [PATCH 19/26] drm/i915: add ValleyView specific force wake get/put functions

LEYVIEW((dev_priv)->dev)) > In the spirit of bikeshedding, I think that NEEDS_FORCE_WAKE is becoming a bit scary this way. But I don't know if it makes sense to move the gen and dev check into a feature flag, to avoid similar issues with po

Re: [Intel-gfx] [PATCH 08/26] drm/i915: add DPIO read/write functions for ValleyView

gisters changes make them different enough not to be directly reused AFAIK. So I think we'll have to stick with a set of DPIO and SBI ops for now. So other that the other Ben's and Chris' comments about this: Reviewed-by: Eugeni Dodon

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