of XAA, the legacy i810 offers no more functionality
> > or performance than is available through VESA?
>
> Afaict we're still have left
> - dri1 for glxgears
>
Wasn't DRI1 ripped from mesa as well?
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the HDMI connector
>
> drivers/gpu/drm/i915/intel_display.c | 14 ++
> drivers/gpu/drm/i915/intel_hdmi.c|2 +-
> drivers/gpu/drm/i915/intel_sdvo.c|2 +-
> 3 files changed, 16 insertions(+), 2 deletions(-)
>
Everything looks correct to me, t
p?page=news_item&px=MTA0MjI
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gressed (XAA/EXA/UXA/SNA) - and that happend quite often in the last
> few years. I now if I am prepared for another round just yet...
>
Don't forget that there is Glamor now as well :).
--
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<http://eugeni.dodonov.net/>
__
On Mon, Jan 16, 2012 at 21:19, Wu Fengguang wrote:
>
> Signed-off-by: Wu Fengguang
> ---
> tools/intel_audio_dump.c | 35 +++
> 1 file changed, 35 insertions(+)
>
Everything looks fine to me, so:
Reviewed-by: Eugeni Dodonov
--
Eu
On Mon, Jan 23, 2012 at 22:14, Eric Anholt wrote:
> Signed-off-by: Eric Anholt
> Cc: sta...@vger.kernel.org
>
Reviewed-by: Eugeni Dodonov
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On Mon, Jan 23, 2012 at 22:14, Eric Anholt wrote:
> We had two things in a row claiming to be RC6.
>
Reviewed-by: Eugeni Dodonov
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On Tue, Jan 24, 2012 at 06:44, Daniel Vetter wrote:
> Corresponding changes to improve our error_state are pending
> some other patches to clean up things first.
>
> Signed-Off-by: Daniel Vetter
>
Reviewed-by: Eugeni Dodonov
I've send the patches to provide .has_sem
On Tue, Jan 24, 2012 at 06:44, Daniel Vetter wrote:
> We need this to correctly access registers in the gt power well from
> userspace.
>
> Signed-Off-by: Daniel Vetter
>
Reviewed-by: Eugeni Dodonov
--
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<http://
hecks.
>
> I'll jot down a todo to create a cleanup patch for -next that introduce
> some feature flags like has_forcewake has_rc6 and such to avoid such
> gaffles (hopefully).
>
I actually wrote about the very same idea in my previous email :). So +1 to
that!
--
Eugeni Dodonov
&l
On Tue, Jan 24, 2012 at 20:42, Ben Widawsky wrote:
> Sometimes it may be the case when we idle the gpu or wait on something
> we don't actually want to process the retiring list. This patch allows
> callers to choose the behavior.
>
> Signed-off-by: Ben Widawsky
>
Revi
21) /* gen4 only */
> +#define PIPECONF_INTERLACE_W_FIELD_INDICATION(6 << 21)
> +#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
>
As you are touching this code, perhaps you could align the
tabification/spacing as well?
Other than that,
Revi
ngs in frames. Enforce this in
> our crtc mode_fixup function and rip out any redudant timing
> computations from the encoders' mode_fixup function.
>
> v2-4: Adjust the vertical timings a bit.
>
> v5: Split out the 'subtract-one for interlaced' fixes.
>
>
ys that this is irrespective of whether the interlaced mode
> has an odd or even vtotal, both modes are supported.
>
> Signed-off-by: Daniel Vetter
>
Reviewed-by: Eugeni Dodonov
--
Eugeni Dodonov
<http://eugeni.dodonov.net/>
___
lowed for the crt on gen2. dvo and lvds are the only other
> encoders that gen2 supports and these already disallow interlaced
> modes.
>
> Signed-Off-by: Daniel Vetter
>
Reviewed-by: Eugeni Dodonov
--
Eugeni Dodonov
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__
On Sat, Jan 28, 2012 at 11:49, Daniel Vetter wrote:
> From: Peter Ross
>
> Signed-off-by: Peter Ross
> Signed-off-by: Daniel Vetter
>
Reviewed-by: Eugeni Dodonov
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On Sat, Jan 28, 2012 at 11:49, Daniel Vetter wrote:
> From: Peter Ross
>
> Signed-off-by: Peter Ross
> Signed-off-by: Daniel Vetter
>
Reviewed-by: Eugeni Dodonov
--
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___
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On Mon, Jan 30, 2012 at 15:41, Chad Versace wrote:
> If the pci_device's actual gen was > 4, then we stupidly set
> bufmgr_gem->gen = 6.
>
> Signed-off-by: Chad Versace
>
Reviewed-by: Eugeni Dodonov
I was thinking on maybe making this more future-proof to help th
s on Sandy Bridge / Ivy Bridge.
Thanks,
Eugeni
Daniel Vetter (3):
drm/i915: check ACTHD of all rings
drm/i915: convert force_wake_get to func pointer in the gpu reset
code
drm/i915: protect force_wake_(get|put) with the gt_lock
Eugeni Dodonov (1):
drm/i915: handle IVB 3rd pipe duri
on.
Upstream patch:
commit 2deed761188d7480eb5f7efbfe7aa77f09322ed8
Author: Wu Fengguang
Date: Fri Dec 9 20:42:20 2011 +0800
drm/i915: HDMI hot remove notification to audio driver
CC: Wang Zhenyu
Signed-off-by: Wu Fengguang
Signed-off-by: Keith Packard
Signed-off-by: Eugeni Dodonov
off-by: Wu Fengguang
Signed-off-by: Keith Packard
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_dp.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 92b041b..db3b461 100644
--- a/drive
ke on snb/ivb.
Upstream patch:
commit 097354eb14fa94d31a09c64d640643f58e4a5a9a
Author: Daniel Vetter
Date: Sun Nov 27 18:58:17 2011 +0100
drm/i915: check ACTHD of all rings
Signed-Off-by: Daniel Vetter
Reviewed-by: Chris Wilson
Signed-off-by: Keith Packard
Signed-off-by: Eugeni Do
-0200
drm/i915: Fix TV Out refresh rate.
Signed-off-by: Rodrigo Vivi
Reviewed-by: Jesse Barnes
Signed-off-by: Keith Packard
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_tv.c | 16
1 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu
ugeni Dodonov
Date: Sat Jan 7 23:40:35 2012 -0200
drm/i915: handle 3rd pipe
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41977
Signed-off-by: Eugeni Dodonov
Reviewed-by: Jesse Barnes
Signed-off-by: Keith Packard
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_susp
8109021313c7a3d8947677391ce6ab9cd0bb1d28
Author: Daniel Vetter
Date: Fri Jan 13 16:20:06 2012 -0800
drm/i915: convert force_wake_get to func pointer in the gpu reset code
Signed-Off-by: Daniel Vetter
Reviewed-by: Eugeni Dodonov
Signed-off-by: Keith Packard
Signed-off-by: Eugeni Dodonov
---
drivers/gpu
lson's suggestions.
Upstream patch:
commit 9f1f46a45a681d357d1ceedecec3671a5ae957f4
Author: Daniel Vetter
Date: Wed Dec 14 13:57:03 2011 +0100
drm/i915: protect force_wake_(get|put) with the gt_lock
Signed-Off-by: Daniel Vetter
Reviewed-by: Chris Wilson
Reviewed-by: Eugeni Dodonov
Signe
s, but couldn't find any
> > inconsistencies. Still, dump them too.
> >
> > Signed-Off-by: Daniel Vetter
> Reviewed-and-wanted-by: Chris Wilson
>
Yeah!! Thanks a lot for that.
Reviewed-by: Eugeni Dodonov
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___
This allows to hopefully find out who was responsible for the GPU death.
To simplify post-portem analysis, we also search for the the processes
names when gathering the i915_error_state and when peeking at the list of
active gem objects in debugfs.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu
memcpy hungry.
CC: Eric Anholt
CC: Daniel Vetter
CC: Ben Widawsky
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_debugfs.c| 45
drivers/gpu/drm/i915/i915_drv.h|5 +++
drivers/gpu/drm/i915/i915_gem_execbuffer.c |6
memcpy hungry.
v2: also track objects accessed via mmap or pwrite.
CC: Konstantin Belousov
CC: Eric Anholt
CC: Daniel Vetter
CC: Ben Widawsky
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_debugfs.c| 45
drivers/gpu/drm/i915/i915_drv.h
The combination of those 4 workarounds seem to solve random hand-hangs observed
in GLBenchmark Egypt and (much more rarely) in World of Padman and Unigine
demos.
Eugeni Dodonov (4):
drm/i915: gen7: implement rczunit workaround
drm/i915: gen7: add two more IVB workarounds
drm/i915: gen7
This is yet another workaround related to clock gating which we need on Gen7.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c |4
2 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915
This adds two cache-related workarounds for Ivy Bridge which can lead to 3D
ring hangs and corruptions.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h |7 +++
drivers/gpu/drm/i915/intel_display.c |6 ++
2 files changed, 13 insertions(+), 0 deletions
This adds the workaround for WaCatErrorRejectionIssue which could result in a
system hang..
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h |4
drivers/gpu/drm/i915/intel_display.c |4
2 files changed, 8 insertions(+), 0 deletions(-)
diff --git a
Add the WaDisableEUInstructionShootdown workaround for Ivy Bridge.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h |5 +
drivers/gpu/drm/i915/intel_display.c |9 +
2 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915
Reviewed-by: Eugeni Dodonov
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exuiz).
Eugeni Dodonov (3):
drm/i915: gen7: implement rczunit workaround
drm/i915: gen7: add two more IVB workarounds
drm/i915: gen7: work around a system hang on IVB
drivers/gpu/drm/i915/i915_reg.h | 12
drivers/gpu/drm/i915/intel_display.c | 25 ++-
This is yet another workaround related to clock gating which we need on
Ivy Bridge.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c | 14 +++---
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a
This adds two cache-related workarounds for Ivy Bridge which can lead to
3D ring hangs and corruptions.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h |7 +++
drivers/gpu/drm/i915/intel_display.c |6 ++
2 files changed, 13 insertions(+), 0 deletions
This adds the workaround for WaCatErrorRejectionIssue which could result
in a system hang.
Reviewed-by: Kenneth Graunke
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h |4
drivers/gpu/drm/i915/intel_display.c |5 +
2 files changed, 9 insertions(+), 0
at.
>
It is from Message-ID: <4f2c80bc.8060...@whitecape.org>
I'll update patch1 with Ken's comments and resend with better summaries.
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hedding spirit, but why do we
need intel_ring_get_tail()? Wouldn't just:
request_ring_position = ring->tail;
be self-explainable? Or some additional logic could be involved there at
some point?
But in overall, I like this, so:
Reviewed-by: Eugeni Dodonov
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Eugeni Dodonov
<http://e
Hi,
if you are among the ones affected by any kind of RC6 issues on Sandy Bridge
platform, please, try the following patch and report if it changes the
behavior somehow on your machine.
This patch allows to enable different and separate RC6 stages independently
from each other. So chances are, wi
i915_enable_rc6=7
Note that this changes behavior - previously, value of 1 would enable both
RC6 and deep RC6. Now it should only enable RC6 and deep/deepest RC6
stages must be enabled manually.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_drv.c |6 +-
drivers/gpu/drm/i915
On Wed, Feb 8, 2012 at 20:14, Kai Krakow wrote:
> Eugeni Dodonov schrieb:
>
> > if you are among the ones affected by any kind of RC6 issues on Sandy
> > Bridge platform, please, try the following patch and report if it changes
> > the behavior somehow on your machine.
&
ything worse. It'd be nice to understand
> why the register writes aren't sticking, though...
>
Complementing Ken's mail, Li Bo from our QA team has did a full round of
tests with these patches on IVB and all known issues were gone apparently.
Keith, Jesse - I think
On Wed, Feb 8, 2012 at 21:29, Eugeni Dodonov wrote:
> On Wed, Feb 8, 2012 at 20:14, Kai Krakow wrote:
>
>> Eugeni Dodonov schrieb:
>>
>> > if you are among the ones affected by any kind of RC6 issues on Sandy
>> > Bridge platform, please, try the followi
d to keep the enable check here, because this can be called
from within i915_reset as well.
To fix this and prevent clash between i915_gem_init_ppgtt and
i915_gem_init_ppgtt, I guess you could add the 'i915_enable_ppgtt && '
check to the i915_gem_init_ppgtt call in Patch3 as w
ms with LVDS attached which we fail to detect. So for PCH,
> trust the LVDS presence pin and quirk all the lying manufacturers.
>
> Reported-by: Daniel Woff
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43171
> Signed-off-by: Chris Wilson
>
Reviewed-by: Eugeni Dodonov
ave a small suggestion for the
module parameter patch (Patch7), but other than that, for the series:
Reviewed-by: Eugeni Dodonov
>
Also, I was using this pretty extensively for the past few months, on
different SNB and IVB machines, so you can add the:
Tested-b
On Wed, Feb 8, 2012 at 18:09, Chris Wilson wrote:
> So that we can tally the request against the command sequence in the
> ringbuffer, or merely jump to the interesting locations.
>
> Signed-off-by: Chris Wilson
>
For both patches:
Reviewed-by: Eugeni Dodonov
--
Eugen
of an interlaced pipe.
>
> Tested-by: Christopher Egert
> Signed-Off-by: Daniel Vetter
>
This makes sense, and we have a test-case where it actually solves issues.
So
Reviewed-by: Eugeni Dodonov
--
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<http://eugeni.dodonov.net/>
___
6 issues in the future.
Eugeni Dodonov (2):
drm/i915: allow to select rc6 modes via kernel parameter
drm/i915: enable plain RC6 on Sandy Bridge by default
drivers/gpu/drm/i915/i915_drv.c |6 +-
drivers/gpu/drm/i915/i915_drv.h |5 +
drivers/gpu/drm/i915/intel_d
debugging
on user machines.
Note that this changes behavior - previously, value of 1 would enable both
RC6 and deep RC6. Now it should only enable RC6 and deep/deepest RC6
stages must be enabled manually.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_drv.c |6 +-
drivers
27;t given any problems - at least,
none we are aware of.
So with this, when i915_enable_rc6=-1 (e.g., the default value), we'll
attempt to enable plain RC6 only on SNB. For Ivy Bridge, the behavior
stays the same as always - we enable both RC6 and deep RC6.
Signed-off-by: Eugeni Dodonov
---
mask now. So it will always return some meaningful values to us
and explicitly say if RC6 should be disabled or enabled (and if enabled,
which states are active).
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Intel-gfx@l
debugging
on user machines.
Note that this changes behavior - previously, value of 1 would enable both
RC6 and deep RC6. Now it should only enable RC6 and deep/deepest RC6
stages must be enabled manually.
v2: address Chris Wilson comments and clean up the code.
Signed-off-by: Eugeni Dodonov
On Sat, Feb 11, 2012 at 10:59, Chris Wilson wrote:
> On Sat, 11 Feb 2012 10:34:15 -0200, Eugeni Dodonov <
> eugeni.dodo...@intel.com> wrote:
> > This is yet another chapter in the ongoing saga of bringing RC6 to Sandy
> > Bridge machines by default.
> >
> >
On Feb 12, 2012 6:53 PM, "Ben Widawsky" wrote:
>
> On 02/11/2012 08:23 PM, Eugeni Dodonov wrote:
> > This allows to select which rc6 modes are to be used via kernel
parameter,
> > via a bitmask parameter. E.g.:
> >
> > - to enable rc6, i915_enabl
On Sun, Feb 12, 2012 at 18:10, Keith Packard wrote:
> <#part sign=pgpmime>
> On Sat, 11 Feb 2012 17:24:16 -0200, Eugeni Dodonov
> wrote:
>
> > So far I had 2 reports saying that RC6 solved the problems which were
> > present with RC6+RC6p (previous default) on S
ve this possibility, so in case we ever observe something similar on any
other GEN arch we'd have a quick way to debug.
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g specific RC6 states according to the GPU
generation) were proposed for the -next kernel, but we are too late in the
release process now to pick such changes.
CC: Keith Packard
CC: Jesse Barnes
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c |4 ++--
1 files
On Tue, Feb 14, 2012 at 19:09, Ben Widawsky wrote:
> This is needed for an upcoming workaround.
>
> Signed-off-by: Ben Widawsky
>
Reviewed-by: Eugeni Dodonov
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___
Intel-gfx mail
with an execbuf (likely execbuf3). Since that part is mostly trivial,
> and will surely be contentious, it's ignored for now.
>
> Signed-off-by: Ben Widawsky
>
Reviewed-by: Eugeni Dodonov
--
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<http://eugeni.dodonov.net/>
___
, I think this should do the trick.
Reviewed-by: Eugeni Dodonov
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On Tue, Feb 14, 2012 at 19:09, Ben Widawsky wrote:
> From: Ben Widawsky
>
> Parameters tell user space if contexts are available.
>
> Signed-off-by: Ben Widawsky
>
Reviewed-by: Eugeni Dodonov
--
Eugeni Dodonov
<http
On Tue, Feb 14, 2012 at 19:09, Ben Widawsky wrote:
> Nice to have a list of contexts handy for debug and perhaps other things
> in the future.
>
> Signed-off-by: Ben Widawsky
>
Reviewed-by: Eugeni Dodonov
--
Eugeni Dodonov
<http://
On Tue, Feb 14, 2012 at 19:09, Ben Widawsky wrote:
> Signed-off-by: Ben Widawsky
>
Reviewed-by: Eugeni Dodonov
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d the things a bit :))
[1] http://www.opengl.org/registry/specs/ARB/robustness.txt
[2] http://www.opengl.org/registry/specs/EXT/transform_feedback.txt
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}
>
Wouldn't it be cleaner and more consistent with the rest of the code to use:
if (!bus->has_gpio)
ret = -EIO;
else {
bus->force_bit = true;
ret = intel_i2c_quirk_xfer(bus, msgs, num);
}
instead?
Other than that, it looks correct to me, and certainly makes
know by filing bugs
following the http://intellinuxgraphics.org/how_to_report_bug.htmlguidelines.
Thanks,
Eugeni Dodonov
Intel Open Source Technology Center
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ixes I think.
And as for Patch2, I guess it should fix
https://bugs.freedesktop.org/show_bug.cgi?id=46043.
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As noticed by Torsten Kaiser, the operator precedence can play tricks with
us here.
CC: Dave Airlie
CC: Jesse Barnes
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915
On Tue, Feb 14, 2012 at 19:37, Daniel Vetter wrote:
> This way we can free up the bus->adaptor.algo_data pointer and make it
> available for use with the bitbanging fallback algo.
>
> Signed-Off-by: Daniel Vetter
>
Reviewed-by: Eugeni Dodonov
--
Eugeni Dodonov
<http
rted by the bit-banging together with
> what gmbus can do, so that this doesn't randomly change any more.
>
> v2: Chris Wilson noticed that I've mixed up && and & ...
>
> v3: Clarify an if block as suggested by Eugeni Dodonov.
>
> Signed-Off-by: Daniel
This will allow us to pass more options to it in the future.
Signed-off-by: Eugeni Dodonov
---
tools/intel_reg_read.c | 44 +++-
1 file changed, 35 insertions(+), 9 deletions(-)
diff --git a/tools/intel_reg_read.c b/tools/intel_reg_read.c
index cad30ff
The registers must be passed on the command line and will be read
sequentially, one at a time.
Signed-off-by: Eugeni Dodonov
---
tools/intel_reg_read.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/tools/intel_reg_read.c b/tools/intel_reg_read.c
index
this will become much more
difficult to read when printing multiple registers at the same time.
Signed-off-by: Eugeni Dodonov
---
tools/intel_reg_read.c | 25 +++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/tools/intel_reg_read.c b/tools/intel_reg_read.c
ind
This will allow us to pass more options to it in the future.
v2: fix whitespacing issues and improve scary warning text as suggested by
Paul Menzel.
Reviewed-by: Paul Menzel
Signed-off-by: Eugeni Dodonov
---
tools/intel_reg_read.c | 44 +++-
1 file
The registers must be passed on the command line and will be read
sequentially, one at a time.
Signed-off-by: Eugeni Dodonov
---
tools/intel_reg_read.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/tools/intel_reg_read.c b/tools/intel_reg_read.c
index
this will become much more
difficult to read when printing multiple registers at the same time.
v2: fix spacing to get us a bit closer to the code nirvana.
Signed-off-by: Eugeni Dodonov
---
tools/intel_reg_read.c | 25 +++--
1 file changed, 23 insertions(+), 2 deletions(-)
di
please report it into our bugzilla, attaching the files and
information mentioned at
http://intellinuxgraphics.org/how_to_report_bug.html please?
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Eugeni Dodonov
<http://eugeni.dodonov.net/>
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I am fine with either spelling though, it just looks more semantically
correct to me. But in any case,
Reviewed-by: Eugeni Dodonov
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d to split is for now. It is a
nice way to have all the registers in just one place, and at least I never
had a problem with it so far.
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On Wed, Mar 21, 2012 at 16:48, Jesse Barnes wrote:
> It's only used by the main read/write functions, so we can keep it with
> them.
>
> Signed-off-by: Jesse Barnes
>
Reviewed-by: Eugeni Dodonov
(One patch less from my own series to send).
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<ht
w that we failed as
well?
> return ret;
>
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at those patches and point me at
things I've been doing wrong :).
Cheers,
Eugeni
Eugeni Dodonov (37):
drm/i915: add Haswell devices and their PCI IDs
drm/i915: add support for LynxPoint PCH
drm/i915: add HAS_PLL_SPLIT macro
drm/i915: add haswell into the PCH SPLIT company
drm
This adds product definitions for desktop, mobile and server boards.
Signed-off-by: Eugeni Dodonov
---
drivers/char/agp/intel-agp.c|4
drivers/char/agp/intel-agp.h| 11 +++
drivers/char/agp/intel-gtt.c| 14 ++
drivers/gpu/drm/i915/i915_drv.c | 23
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_drv.c |4
drivers/gpu/drm/i915/i915_drv.h |2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d4f542b..5fe9d62 100644
--- a/drivers/gpu/drm/i915
Ivy Bridge is the only GPU which has split 3-display support over 2 PLLs.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_drv.h |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 49488e1..fb50c42 100644
Haswell is similar to Ivy Bridge in this sense.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_drv.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fb50c42..51e04ec 100644
--- a/drivers
This defines the registers used by different power wells.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 52a06be..ddc9c87 100644
--- a
There is one set of such registers for each pipe (A/B/C/EDP).
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ddc9c87
This is one set of those registers for each pipe.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 09b2267..7a9232e 100644
--- a
There is one set of those registers for each port.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h |8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7a9232e..3831fe7 100644
--- a/drivers/gpu
There is one instance of those registers for each DDI port.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3831fe7..2927460
code paths.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 59 +++---
1 file changed, 47 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index a37e0b7..10b92e8 10
the last item. Those are ignored in such modes, so there is
no harm in having them set.
Initially, we use DDI E for FDI connectivity. This is the suggested
configuration, and this seems to be what should work the best with FDI.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915
This should be already configured when FDI auto-negotiation is done.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index
This PLL control can drive DDI ports at desired frequencies for
DisplayPort and FDI connections.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h |8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
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