sometimes get into RC6 even if we pass the
i915_enable_rc6=0 parameter). I don't know if it is Bios playing some
tricks with us or something changed in the mailbox communication, but no
harm came from this so far. I'll see what is going on there.
But for the patch itself
for
> those patches I'll just mark like this:
>
> * indentation
> Reviewed-by: Rodrigo Vivi
>
The identation is different between registers themselves (e.g.,
0xSOMETHING) and the bits we use in those registers (e.g., (1<<31)). So
this is on purpose.
On Mon, Mar 26, 2012 at 14:35, Rodrigo Vivi wrote:
> *indentation
> and it is missing
> #define PIPE_DDI_MODE_SELECT_DP_MST (3<<24)
>
> Otherwise:
> Reviewed-by: Rodrigo Vivi
>
We are not using this bit, this is why I am not exposing it...
--
Eugeni Dodonov
On Mon, Mar 26, 2012 at 19:34, Ben Widawsky wrote:
> I'd like to resubmit this patch with either %u or %x instead of the %d.
> Can I still keep your r-b?
>
I'd vote for %u - it makes more sense as we are counting real time here.
But sure, you can keep my R-b for this.
--
Eu
On Wed, Mar 28, 2012 at 16:32, Jesse Barnes wrote:
> On Thu, 22 Mar 2012 11:05:22 +
> Chris Wilson wrote:
>
> > On Wed, 21 Mar 2012 22:10:06 -0300, Eugeni Dodonov <
> eugeni.dodo...@intel.com> wrote:
> > > The modesetting sequence for PCH-related connections
fic chip features or names.
So if we drop the IS_GEN macros, and just use the specific feature or GPU
name checks instead we should improve both the readability and decrease the
code complexity I think.
--
Eugeni Dodonov
<http://eugeni.dodonov.net/>
_
eplace them, but I don't think it would be worth the
effort just to replace all the Gen checks with a different switch just for
the sake of doing it.
--
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<http://eugeni.dodonov.net/>
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could you check which of those patches could be
early picked into your tree? This would reduce future patchbombs from my side -
I'd expect to have at least a half-dozen new patches until we'll have working
digital outputs in place..
Eugeni Dodonov (41):
drm/i915: transform HAS_PCH_SPLIT
The macro is becoming too complex and with VLV upon us it can lead to
confusion. So transforming this into a feature check instead.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_drv.c |6 ++
drivers/gpu/drm/i915/i915_drv.h |3 ++-
2 files changed, 8 insertions(+), 1
This adds product definitions for desktop, mobile and server boards.
v2: split into a separate patch, add .has_pch_split feature.
Signed-off-by: Eugeni Dodonov
---
drivers/char/agp/intel-agp.h| 11 +++
drivers/char/agp/intel-gtt.c| 14 ++
drivers/gpu/drm/i915
This patch enabled i915 driver to handle Haswell devices. It should go in
last, when things are working stable enough.
Signed-off-by: Eugeni Dodonov
---
drivers/char/agp/intel-agp.c|4
drivers/gpu/drm/i915/i915_drv.c |7 +++
2 files changed, 11 insertions(+)
diff --git a
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_drv.c |4
drivers/gpu/drm/i915/i915_drv.h |2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 8995165..e4b5571 100644
This defines the registers used by different power wells.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index
There are 5 DDI ports on Haswell. Port A is always enabled, and is the one
connected to eDP, and Port E is the one that can be connected to the PCH
using FDI protocol. Ports B, C, D and E can be used for digital outputs.
Signed-off-by: Daniel Vetter
Signed-off-by: Eugeni Dodonov
---
drivers
There is one set of such registers for each pipe (A/B/C/EDP).
v2: update to use DDI PORTS enum
v1 Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915
This is one set of those registers for each pipe.
v2: use port enum to access individual registers
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915
There is one set of those registers for each port.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h |8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 627e52d..666e319 100644
--- a/drivers/gpu
v2: prevent possible conflicts with VLV.
v1 Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_irq.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 998116e
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5e226ad..1484195 100644
--- a/drivers/gpu
With Lynx Point, we need to use SBI to communicate with the display clock
control. This commit adds helper functions to access the registers via
SBI.
v2: de-inline the function and address changes in bits names
v1 Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_hdmi.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index cae3e5f..de54c01 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915
afterwards to get a working modesetting.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_hdmi.c | 63 -
1 file changed, 62 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 09c18f8..0324250 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b
Those are driven by DDIs on Haswell architecture, so we need to keep track
of which DDI is being used on each output.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_hdmi.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
DDIA is detected via the DDI_BUF_CTL registers bit 0, but for DDIB, DDIC
and DDID we need to consult SFUSE_STRAP values.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h |7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8e5f5be..5e226ad 100644
--- a/drivers/gpu/drm/i915/intel_display.c
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index ea103ca..7daad41 100644
--- a/drivers/gpu
This needs proper enablement to avoid machine hangs, so let's just avoid
it for now.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c |4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/driver
This should be already configured when FDI auto-negotiation is done.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm
considerable rework of our display handling, so we just leave them all
enabled when the driver is loaded for now.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915
Multiple clocks can drive different outputs.
v2: use the port enums to access individual ports
v1 Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h |3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 880c4f7..58fcfae 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b
The line time can be programmed according to the number of horizontal
pixels vs effective pixel rate ratio.
v2: improve comment as per Chris Wilson suggestion
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 13 +
1 file changed, 13 insertions(+)
diff
the output is DP or HDMI.
However, the DDI buffers can be programmed in a way that is shared between
DP/HDMI and FDI/HDMI except for PORT E.
So for now, we detect those digital outputs as being HDMI, but proper DP
support is still pending.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915
Those registers are used to train DDI buffer translations for each link
type.
v2: access each port registers through the DDI_BUF_TRANS macro
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h |7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915
They work differently, but the count is the same.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_dma.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index fdff009
Watermark line time registers for display low power watermark.
v2: improve bit names as suggested by Chris Wilson
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu
The WR PLL can drive the DDI ports at fixed frequencies for HDMI, DVI, DP
and FDI.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h |8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fc24229
-- THIS PATCH IS NOT INTENDED FOR MERGING. IT IS MERELY HERE TO SIMPLIFY
THE DEBUGGING --
This patch is here for make debugging and log tracing easier, it should
go away in the future, when we'll stop hitting those code paths.
v2: cope with changes in bit names
Signed-off-by: Eugeni Do
There is one instance of those registers for each DDI port.
v2: access registers via the DDI_BUF_CTL() macro
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu
This PLL control can drive DDI ports at desired frequencies for
DisplayPort and FDI connections.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h |8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers
calculate those values manually in case no match is found. But I don't
think we'll encounter a mode not covered by those table, and VGA is pretty
much going away in the future anyway.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 309 +++
Pixel clock gating control for Lynx point.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h |6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d6c0e36..48346ad 100644
Different registers are identified by their target id and offset. To
simplify their programming, they are called as .
For example, SSCCTL register accessed through SBI at target id 6 and
offset 0c is called SBI_SSCCTL6.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 1484195..ea103ca 100644
--- a/drivers/gpu
Those are used to control the display core clock.
v2: change the enable bit setting, spotted by Rodrigo Vivi.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h |7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915
both FDI and DP-friendly buffers.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 84 +-
drivers/gpu/drm/i915/intel_drv.h |1 +
2 files changed, 84 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b
separately, for clearer distinction of what happens when.
v2: improve comments a bit, use PORT enums instead of hardcoded PORT_E
registers, split DDI buffers programming into a separate patch.
v1 Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c
Those are responsible for the Sideband Interface programming.
v2: rename SBI bits to better reflect their meaning
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm
This adds PCI ID for IVB GT2 server variant which we were missing.
Signed-off-by: Eugeni Dodonov
---
drivers/char/agp/intel-agp.h|1 +
drivers/char/agp/intel-gtt.c|2 ++
drivers/gpu/drm/i915/i915_drv.c |1 +
3 files changed, 4 insertions(+)
diff --git a/drivers/char/agp
From: Eugeni Dodonov
We were missing this one and it is being used by Bromolow.
Signed-off-by: Eugeni Dodonov
---
intel/intel_chipset.h |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 435d01a..9c1abc8 100644
--- a
This is the GT2 variant of Ivy Bridge server chip.
Signed-off-by: Eugeni Dodonov
---
src/intel_driver.h |1 +
src/intel_module.c |2 ++
2 files changed, 3 insertions(+)
diff --git a/src/intel_driver.h b/src/intel_driver.h
index e9d6d9e..98973e5 100644
--- a/src/intel_driver.h
+++ b/src
;[Intel-gfx] Scanline wait hack for IVB' patch, so hope is not lost yet.
There is a huge thread about this on the
https://bugs.freedesktop.org/show_bug.cgi?id=37686 bug as well.
--
Eugeni Dodonov
<http://eugeni.dodonov.net/>
___
Intel-gfx
", plane A pending flip wait": "",
> + data & (1<<1)? ", plane A scan linscan line":
> "");
>
Shouldn't it be "plane A scan line wait"?
> + } else {
> + instr_out(ctx, 0,
> "MI_WAIT_FOR_EVENT%s%s%s%s%s%s%s%s%s%s%s%s\n",
> + data & (1<<20)? ", prite C pending flip wait":
> "", /* ivb */
>
s/prite/sprite/.
The only major question I have about this is if we should add the other
IVB-specific fields as well, besides the (1<<20) one.
Other than that,
Reviewed-by: Eugeni Dodonov
--
Eugeni Dodonov
<http://eugeni.dodonov.net/>
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* operations. It does not look trivial nor desirable to move
> +* that lokcing higher. So instead we leave a window for the
>
*locking
Reviewed-by: Eugeni Dodonov
--
Eugeni Dodonov
<http://eugeni.dodonov.net/>
___
Intel-gf
4?
I think we don't need to write the entire pre-defined message here, only
those 2 bits seem to matter in this case..
--
Eugeni Dodonov
<http://eugeni.dodonov.net/>
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valid
adapter as it was looking too error-prone otherwise. Perhaps we could add a
WARN into them as well.
Eugeni Dodonov (29):
drm/i915: add definition of LPT FDI port width registers
drm/i915: add WRPLL divider programming bits
drm/i915: add Haswell DIP controls registers
drm/i915: s
v2: change bits names to align better with other bits style
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h |3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 972321f
Those are used to program the WRPLL dividers correctly for each gives
frequency.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h |4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 98579f5..05d98f2
Haswell has different DIP control registers and offsets.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_reg.h | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 05d98f2..8cc53fb 100644
Haswell has different DIP registers which we need to use for infoframes,
so add proper infrastructure to address that.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_hdmi.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/drivers/gpu/drm
Prevent a NULL pointer exception when we are trying to retrieve EDID data
from non-existent adapter.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_hdmi.c | 30 +++---
1 file changed, 19 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 63 ++
1 file changed, 63 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 33aaad3..36f6b8e 100644
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 36f6b8e..60b1540 100644
--- a/drivers/gpu/drm/i915/intel_display.c
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 60b1540..3d78686 100644
--- a/drivers/gpu
They work differently, but the count is the same.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_dma.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 333b746
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 0768f48..e4ebd39 100644
--- a/drivers/gpu/drm/i915/intel_display.c
considerable rework of our display handling, so we just leave them all
enabled when the driver is loaded for now.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915
On Haswell, the only PCH-connected output is the one driven by DDI E in
FDI mode, used for VGA connection. All the others are handled by the CPU.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c |7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm
Haswell has a different way of accessing pipes and PCH-specific registers,
so avoid using legacy registers on it.
This patch will probably be reworked into a series of smaller patches once
the required plumbing lands and we won't hit those assertions anymore.
Signed-off-by: Eugeni Do
calculate those values manually in case no match is found. But I don't
think we'll encounter a mode not covered by those table, and VGA is pretty
much going away in the future anyway.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 309 +++
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index dcfe143..ac34457 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b
This should be already configured when FDI auto-negotiation is done.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 3d78686..5ee652d 100644
--- a/drivers/gpu
programming instead of HDMI-specific registers.
This commit take advantage of the WR PLL clock table which is in a
separate (previous) commit to select the right divisors for each mode.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_hdmi.c | 129
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 5ee652d..33ff60e 100644
--- a/drivers/gpu
both FDI and DP-friendly buffers.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 84 +-
drivers/gpu/drm/i915/intel_drv.h |1 +
2 files changed, 84 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b
Those are driven by DDIs on Haswell architecture, so we need to keep track
of which DDI is being used on each output.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_hdmi.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
This table is used for programming WR PLL clocks, used by HDMI and DVI outputs.
I split it into a separate patch to simplify the HDMI enabling patch which was
getting huge.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_hdmi.c | 388 +
1 file
The line time can be programmed according to the number of horizontal
pixels vs effective pixel rate ratio.
v2: improve comment as per Chris Wilson suggestion
v3: incorporate latest changes in specs.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 13
separately, for clearer distinction of what happens when.
v2: improve comments a bit, use PORT enums instead of hardcoded PORT_E
registers, split DDI buffers programming into a separate patch.
v1 Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c
This patch enables i915 driver to handle Haswell devices. It should go in
last, when things are working stable enough.
Signed-off-by: Eugeni Dodonov
---
drivers/char/agp/intel-agp.c|4
drivers/gpu/drm/i915/i915_drv.c |7 +++
2 files changed, 11 insertions(+)
diff --git a
v2: prevent possible conflicts with VLV.
v1 Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/i915_irq.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index febddc2
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_hdmi.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 700bd0b..0978fb7 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915
This needs proper enablement to avoid machine hangs, so let's just avoid
it for now.
Reviewed-by: Rodrigo Vivi
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c |4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/driver
here for hdmi
initialization.
Signed-off-by: Eugeni Dodonov
---
drivers/gpu/drm/i915/intel_display.c | 51 +++---
1 file changed, 35 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index
On Fri, Apr 13, 2012 at 17:18, Chris Wilson wrote:
> On Fri, 13 Apr 2012 17:08:41 -0300, Eugeni Dodonov <
> eugeni.dodo...@intel.com> wrote:
> > Prevent a NULL pointer exception when we are trying to retrieve EDID data
> > from non-existent adapter.
>
> This just me
On Fri, Apr 13, 2012 at 17:26, Chris Wilson wrote:
> On Fri, 13 Apr 2012 17:08:42 -0300, Eugeni Dodonov <
> eugeni.dodo...@intel.com> wrote:
> > With Lynx Point, we need to use SBI to communicate with the display clock
> > control. This commit adds helper functions to
wait for the PLL patches to land and will refactor this
accordingly. I just didn't wanted to have it blocking my entire series here.
With HSW, on PCH, we only have 1 PLL (iCLKIP), the other ones are on the
CPU.
--
Eugeni Dodonov
<http://eugeni.dodonov.net/>
__
ur dinq maintainership point of
view - refactor those bits here and in other big patches of this series
(fdi and hdmi ones) and then resend all the patches; or have them as is and
do the big refactoring for everything after that?
--
Eugeni Dodonov
<
On Fri, Apr 13, 2012 at 18:03, Chris Wilson wrote:
> On Fri, 13 Apr 2012 17:08:53 -0300, Eugeni Dodonov <
> eugeni.dodo...@intel.com> wrote:
> > void intel_modeset_init(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_privat
On Fri, Apr 13, 2012 at 18:11, Chris Wilson wrote:
> On Fri, 13 Apr 2012 17:08:57 -0300, Eugeni Dodonov <
> eugeni.dodo...@intel.com> wrote:
> > - if (IS_HASWELL(dev))
> > + if (IS_HASWELL(dev)) {
> >
or this patch, I have just one comment/suggestion below, but other
than that:
Reviewed-by: Eugeni Dodonov
+static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
> *dev_priv)
>
Perhaps this functions should be named ivybridge_setup_fixed_func_scheduler
instead?
Even
On Sat, Apr 14, 2012 at 14:05, Chris Wilson wrote:
> And most of that concern is due to the fact that the modesetting code
> seems to have evolved ad-hoc with very few sanity checks and no
> overarching design.
>
Yep, I have to agree on that :(.
--
Eugeni Dodonov
<http://eug
mode->private_flags if the crtc
> timings have been adjusted.
>
> Reported-and-Tested-by: Hans de Bruin
> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43071
> Signed-Off-by: Daniel Vetter
>
As for the patch itself, as far as I can tell, it does what it meant to, so
means that we are sending TV data that it does not
understands, but there are many possible cases why it could happen..
Intel_reg_dumper should give us a summary of what bits and registers could
be wrong.
--
Eugeni Dodonov
<http://eugeni.dodonov.net/>
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new and previously
unthinkable mode pops up :).
--
Eugeni Dodonov
<http://eugeni.dodonov.net/>
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, and so far it seems
to improve the display detection timing by 30%-3000% (depending on hardware
of course and number of outputs and such).
--
Eugeni Dodonov
<http://eugeni.dodonov.net/>
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On Mon, Apr 16, 2012 at 20:23, Chris Wilson wrote:
> On Mon, 16 Apr 2012 20:06:01 -0300, Eugeni Dodonov <
> eugeni.dodo...@intel.com> wrote:
> > As previously discussed on irc with Daniel, Ben and Jesse, This patch
> > moves the power-related functionality into in
intel_display.c module by around 2800 lines
while also simplifying future power-related developments.
Eugeni Dodonov (5):
drm/i915: move fbc-related functionality into intel_pm module
drm/i915: move watermarks settings into intel_pm module
drm/i915: move drps, rps and rc6-related functions
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