On 08/06/15 18:03, Tomas Elf wrote:
> In preparation for per-engine reset add way for setting context reset stats.
>
> OPEN QUESTIONS:
> 1. How do we deal with get_reset_stats and the GL robustness interface when
> introducing per-engine resets?
>
> a. Do we set context that cause per-engin
On 08/06/15 18:45, Chris Wilson wrote:
> On Mon, Jun 08, 2015 at 06:03:28PM +0100, Tomas Elf wrote:
>> 1. The i915_wedged_set function allows us to schedule three forms of hang
>> recovery:
>>
>> a) Legacy hang recovery: By passing e.g. -1 we trigger the legacy full
>> GPU reset recovery
On 12/06/15 12:58, Siluvery, Arun wrote:
> On 09/06/2015 19:43, Dave Gordon wrote:
>> On 05/06/15 14:57, Arun Siluvery wrote:
>>> In Per context w/a batch buffer,
>>> WaRsRestoreWithPerCtxtBb
>>>
>>> v2: This patches modifies definitions of MI_LOAD_R
Updates and supersedes the referenced patch,
"Reinstate order of operations in {intel,logical}_ring_begin()"
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
l ring submission mechanism
So now we have to fix it in both paths ...
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/intel_lrc.c| 64 +++
drivers/gpu/drm/i915/intel_ringbuffer.c | 63 +++---
2 files changed, 64 insertions(+), 63
When calculating the available space in a ringbuffer, we should
use the effective_size rather than the true size of the ring.
v2: rebase to latest drm-intel-nightly
v3: rebase to latest drm-intel-nightly
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/intel_lrc.c|5
On 12/06/15 19:05, Chris Wilson wrote:
> On Fri, Jun 12, 2015 at 06:09:08PM +0100, Dave Gordon wrote:
>> The original idea of preallocating the OLR was implemented in
>>
>>> 9d773091 drm/i915: Preallocate next seqno before touching the ring
>>
>> and the sequen
On 12/06/15 19:12, Chris Wilson wrote:
> On Fri, Jun 12, 2015 at 06:09:07PM +0100, Dave Gordon wrote:
>> When calculating the available space in a ringbuffer, we should
>> use the effective_size rather than the true size of the ring.
>>
>> v2: rebase to latest drm-int
iding
both the problems described in the two commits mentioned above. So this
commit moves the calls to i915_gem_request_alloc() into the middle of
{__intel,logical}_ring_prepare() rather than either before or after them.
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/intel_lrc.c
end of the ringbuffer), and
then again to get enough space for the new data that the caller
wants to add.
Now we just precalculate the total amount of space we'll need
*including* any for padding at the end of the ringbuffer and wait
for that much in one go.
Signed-off-by: Dave Gordon
---
Updated version split into two. The first tidies up the _ring_prepare()
functions and removes the corner case where we might have had to wait
twice; the second is a temporary workaround to solve a kernel OOPS that
can occur if logical_ring_begin is called while the ringbuffer is not
mapped because
On 12/06/15 22:30, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> We tried to fix this in the following commit:
>
> commit fdc454c1484a20e1345cf4e4d7a9feaee814147f
> Author: Michel Thierry
> Date: Tue Mar 24 15:46:19 2015 +
> drm/i915: Prevent out of range pt in gen6_for_each_pde
>
> b
On 13/06/15 09:28, Chris Wilson wrote:
> On Fri, Jun 12, 2015 at 06:30:56PM -0300, Paulo Zanoni wrote:
>> From: Paulo Zanoni
>>
>> We tried to fix this in the following commit:
>>
>> commit fdc454c1484a20e1345cf4e4d7a9feaee814147f
>> Author: Michel Thierry
>> Date: Tue Mar 24 15:46:19 2015 +000
On 15/06/15 15:10, Siluvery, Arun wrote:
> On 12/06/2015 18:03, Dave Gordon wrote:
>> On 12/06/15 12:58, Siluvery, Arun wrote:
>>> On 09/06/2015 19:43, Dave Gordon wrote:
>>>> On 05/06/15 14:57, Arun Siluvery wrote:
>>>>> In Per context w/a
On 15/06/15 10:15, Chris Wilson wrote:
> On Mon, Jun 08, 2015 at 07:51:36PM +0100, Dave Gordon wrote:
>> The original idea of preallocating the OLR was implemented in
>>
>>> 9d773091 drm/i915: Preallocate next seqno before touching the ring
>>
>> and the sequen
On 15/06/15 13:34, Daniel Vetter wrote:
> On Fri, Jun 05, 2015 at 12:27:21PM +0300, Ville Syrjälä wrote:
>> On Fri, Jun 05, 2015 at 12:24:45PM +0300, Jani Nikula wrote:
>>> On Thu, 04 Jun 2015, Ville Syrjälä wrote:
On Thu, Jun 04, 2015 at 04:56:18PM +0100, Damien Lespiau wrote:
> I notice
log
drm/i915: Implementation of GuC client
drm/i915: Integrate GuC-based command submission
Documentation/drm: kerneldoc for GuC
Dave Gordon (5):
drm/i915: Embedded microcontroller (uC) firmware loading support
drm/i915: Defer default hardware context initialisation until first
drm/i915: Interru
From: Alex Dai
i915_gem_object_write() is a generic function to copy data from a plain
linear buffer to a paged gem object.
We will need this for the microcontroller firmware loading support code.
Issue: VIZ-4884
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915
From: Alex Dai
Two new module parameters: "enable_guc_submission" which will turn
on submission of batchbuffers via the GuC (when implemented), and
"guc_log_level" which controls the level of debugging logged by the
GuC and captured by the host.
Signed-off-by: Alex Dai
used by each uC-specific loader, thus reducing code duplication
and testing effort.
Signed-off-by: Dave Gordon
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/Makefile |3 +
drivers/gpu/drm/i915/intel_uc_loader.c | 312
drivers/gpu/drm/i915/intel_uc_
setting it running. Some of these also need
to be kept in sync with the firmware.
Issue: VIZ-4884
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_reg.h |4 +-
drivers/gpu/drm/i915/intel_guc.h | 169 +
drivers/gpu/drm/i915
erefore be in non-GuC mode, and will be
allowed to complete even if the GuC cannot be loaded or used.
Issue: VIZ-4884
Signed-off-by: Dave Gordon
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_drv.h |2 ++
drivers/gpu/drm/i915/i915_gem.c |9 +-
drivers/gp
ified firmware loading mechanism by Dave Gordon as well
as new firmware layout etc.
Issue: VIZ-4884
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/Makefile |3 +
drivers/gpu/drm/i915/i915_dma.c |4 +
drivers/gpu/drm/i915/i915_drv.h |
and the GuC's debug log.
Issue: VIZ-4884
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/Makefile |3 +-
drivers/gpu/drm/i915/i915_guc_submission.c | 122
drivers/gpu/drm/i915/intel_guc.h |4 +
d
From: Alex Dai
Allocate a GEM object to hold GuC log data. A debugfs interface
(i915_guc_log_dump) is provided to print out the log content.
Issue: VIZ-4884
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_debugfs.c| 29 +++
drivers
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_guc_submission.c | 668
drivers/gpu/drm/i915/intel_guc.h |5 +
drivers/gpu/drm/i915/intel_guc_loader.c| 10 +
3 files changed, 683 insertions(+)
diff --git a/drivers/gpu/drm/i915
Turn on interrupt steering to route necessary interrupts to GuC.
Issue: VIZ-4884
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_reg.h | 11 +--
drivers/gpu/drm/i915/intel_guc_loader.c | 51 +++
2 files changed, 60
From: "Michael H. Nguyen"
Move defines from intel_lrc.c to i915_reg.h so they are accessible
to the GuC submission code; and expose a previously static function
in the execlist code which will also be required for GuC submission.
Issue: VIZ-4884
Signed-off-by: Michael H. Nguyen
Signed-off-by: A
From: Alex Dai
The new node provides access to the status of the common uC loader
code and the GuC-specific loader; also the scratch registers used
for communicatio between the i915 driver and the GuC firmware.
Issue: VIZ-4884
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
drivers
This provides a means of reading status and counts relating
to GuC actions and submissions.
Signed-off-by: Dave Gordon
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_debugfs.c | 41 +++
1 file changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/i915
e GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
Issue: VIZ-4884
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
drivers/gpu/drm
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_params.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 5134095..926a6df 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b
From: Alex Dai
Add overview design of GuC, plus some key points related to
the implementation.
Signed-off-by: Alex Dai
---
Documentation/DocBook/drm.tmpl | 19 +++
1 file changed, 19 insertions(+)
diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
i
On 15/06/15 11:07, Daniel Vetter wrote:
> On Thu, Jun 04, 2015 at 03:36:32PM +0100, Dave Gordon wrote:
>> On 04/06/15 06:59, Sagar Arun Kamble wrote:
>>>
>>> Hi Daniel,
>>>
>>> We already are grabbing RPM reference before start of DMC FW load and
>&g
On 15/06/15 21:41, Chris Wilson wrote:
> On Mon, Jun 15, 2015 at 07:11:37PM +0100, Dave Gordon wrote:
>>> It still applies. If you submit say 1024 interrupted execbuffers they
>>
>> What is an interrupted execbuffer? AFAICT we hold the struct_mutex while
>> stuffing
On 15/06/15 11:53, Chris Wilson wrote:
> On Mon, Jun 15, 2015 at 11:33:37AM +0100, Dave Gordon wrote:
>> On 13/06/15 09:28, Chris Wilson wrote:
>>> On Fri, Jun 12, 2015 at 06:30:56PM -0300, Paulo Zanoni wrote:
>>>> From: Paulo Zanoni
>>>>
>>
On 15/06/15 21:09, Chris Wilson wrote:
> On Mon, Jun 15, 2015 at 07:36:19PM +0100, Dave Gordon wrote:
>> From: Alex Dai
>>
>> i915_gem_object_write() is a generic function to copy data from a plain
>> linear buffer to a paged gem object.
>>
>> We will nee
On 16/06/15 10:37, Chris Wilson wrote:
> On Mon, Jun 15, 2015 at 07:36:26PM +0100, Dave Gordon wrote:
>> From: "Michael H. Nguyen"
>>
>> Move defines from intel_lrc.c to i915_reg.h so they are accessible
>> to the GuC submission code; and expose a previous
On 16/06/15 10:24, Chris Wilson wrote:
> On Mon, Jun 15, 2015 at 07:36:30PM +0100, Dave Gordon wrote:
>> +static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
>> +{
>> +struct intel_engine_cs *ring;
>> +int i, irqs;
>> +
>> +/
On 15/06/15 21:20, Chris Wilson wrote:
> On Mon, Jun 15, 2015 at 07:36:22PM +0100, Dave Gordon wrote:
>> From: Alex Dai
>>
>> intel_guc_api.h contains the subset of the GuC interface that we
>> will need for submission of commands through the GuC. These MUST
On 17/06/15 12:04, Daniel Vetter wrote:
> On Fri, Jun 12, 2015 at 09:25:36PM +0100, Dave Gordon wrote:
>> Updated version split into two. The first tidies up the _ring_prepare()
>> functions and removes the corner case where we might have had to wait
>> twice; the second is a
On 16/06/15 14:54, Chris Wilson wrote:
> On Tue, Jun 16, 2015 at 03:48:09PM +0200, Daniel Vetter wrote:
>> On Mon, Jun 08, 2015 at 06:33:59PM +0100, Chris Wilson wrote:
>>> On Mon, Jun 08, 2015 at 06:03:21PM +0100, Tomas Elf wrote:
In preparation for per-engine reset add way for setting contex
On 17/06/15 13:02, Daniel Vetter wrote:
> On Wed, Jun 17, 2015 at 08:23:40AM +0100, Dave Gordon wrote:
>> On 15/06/15 21:09, Chris Wilson wrote:
>>> On Mon, Jun 15, 2015 at 07:36:19PM +0100, Dave Gordon wrote:
>>>> From: Alex Dai
>>>>
>>>>
On 17/06/15 13:05, Daniel Vetter wrote:
> On Mon, Jun 15, 2015 at 07:36:20PM +0100, Dave Gordon wrote:
>> Current devices may contain one or more programmable microcontrollers
>> that need to have a firmware image (aka "binary blob") loaded from an
>> externa
On 18/06/15 13:10, Chris Wilson wrote:
> On Thu, Jun 18, 2015 at 12:49:55PM +0100, Dave Gordon wrote:
>> On 17/06/15 13:02, Daniel Vetter wrote:
>>> Domain handling is required for all gem objects, and the resulting bugs if
>>> you don't for one-off objects are
On 18/06/15 15:31, Daniel Vetter wrote:
> On Thu, Jun 18, 2015 at 12:49:55PM +0100, Dave Gordon wrote:
>> On 17/06/15 13:02, Daniel Vetter wrote:
>>> On Wed, Jun 17, 2015 at 08:23:40AM +0100, Dave Gordon wrote:
>>>> On 15/06/15 21:09, Chris Wilson wrote:
>>&g
On 15/06/15 21:30, Chris Wilson wrote:
> On Mon, Jun 15, 2015 at 07:36:23PM +0100, Dave Gordon wrote:
>> +/* We can't enable contexts until all firmware is loaded */
>> +ret = intel_guc_ucode_load(dev, false);
>
> Pardon. I know context initialisation is
On 16/06/15 10:40, Chris Wilson wrote:
> On Mon, Jun 15, 2015 at 07:36:24PM +0100, Dave Gordon wrote:
>> From: Alex Dai
>>
>> The new node provides access to the status of the common uC loader
>> code and the GuC-specific loader; also the scratch registers used
>
On 18/06/15 15:49, Daniel Vetter wrote:
> On Thu, Jun 18, 2015 at 01:11:34PM +0100, Dave Gordon wrote:
>> On 17/06/15 13:05, Daniel Vetter wrote:
>>> On Mon, Jun 15, 2015 at 07:36:20PM +0100, Dave Gordon wrote:
>>>> Current devices may contain one or more programma
On 17/06/15 13:18, Daniel Vetter wrote:
> On Mon, Jun 15, 2015 at 07:36:25PM +0100, Dave Gordon wrote:
>> In order to fully initialise the default contexts, we have to execute
>> batchbuffer commands on the GPU engines. But in the case of GuC-based
>> batch submission, we ca
On 16/06/15 10:35, Chris Wilson wrote:
> On Mon, Jun 15, 2015 at 07:36:25PM +0100, Dave Gordon wrote:
>> +static int i915_gem_context_first_open(struct drm_device *dev)
>> +{
>> +struct drm_i915_private *dev_priv = dev->dev_private;
>> +int ret;
>> +
&
On 18/06/15 21:12, Chris Wilson wrote:
> On Thu, Jun 18, 2015 at 10:53:10AM -0700, Yu Dai wrote:
>>
>>
>> On 06/15/2015 01:30 PM, Chris Wilson wrote:
>>> On Mon, Jun 15, 2015 at 07:36:23PM +0100, Dave Gordon wrote:
>>>> + /* Set the source
On 15/06/15 22:32, Chris Wilson wrote:
> On Mon, Jun 15, 2015 at 07:36:27PM +0100, Dave Gordon wrote:
>> +static struct drm_i915_gem_object *gem_allocate_guc_obj(struct drm_device
>> *dev,
>> +u32 size)
>> +{
>>
On 19/06/15 18:02, Dave Gordon wrote:
> On 15/06/15 22:32, Chris Wilson wrote:
[snip]
>> Try to keep comments to explain why rather than what. Most of the
>> comments here fall into the "i++; // postincrement i" category.
>> -Chris
>
> Most of the "
On 15/06/15 22:55, Chris Wilson wrote:
> On Mon, Jun 15, 2015 at 07:36:29PM +0100, Dave Gordon wrote:
>> +/* Get valid workqueue item and return it back to offset */
>> +static int guc_get_workqueue_space(struct i915_guc_client *gc, u32 *offset)
>> +{
>> +st
On 16/06/15 10:22, Chris Wilson wrote:
> On Mon, Jun 15, 2015 at 07:36:31PM +0100, Dave Gordon wrote:
>> From: Alex Dai
>>
>> GuC-based submission is mostly the same as execlist mode, up to
>> intel_logical_ring_advance_and_submit(), where the context being
>>
On 19/06/15 09:44, Chris Wilson wrote:
> On Thu, Jun 18, 2015 at 07:07:46PM +0100, Dave Gordon wrote:
>> On 18/06/15 13:10, Chris Wilson wrote:
>>> On Thu, Jun 18, 2015 at 12:49:55PM +0100, Dave Gordon wrote:
>>>> On 17/06/15 13:02, Daniel Vetter wrote:
>>>
On 17/06/15 08:59, Chris Wilson wrote:
> On Wed, Jun 17, 2015 at 08:31:59AM +0100, Dave Gordon wrote:
>> On 16/06/15 10:37, Chris Wilson wrote:
>>> On Mon, Jun 15, 2015 at 07:36:26PM +0100, Dave Gordon wrote:
>>>> From: "Michael H. Nguyen"
>>>>
On 22/06/15 16:35, Daniel Vetter wrote:
> On Mon, Jun 22, 2015 at 03:18:12PM +0100, Chris Wilson wrote:
>> On Mon, Jun 22, 2015 at 04:11:01PM +0200, Daniel Vetter wrote:
>>> On Fri, Jun 19, 2015 at 02:04:16PM +0100, Chris Wilson wrote:
Exclude active GPU pages from the purview of the backgroun
On 17/06/15 13:41, Daniel Vetter wrote:
> On Wed, Jun 17, 2015 at 02:22:19PM +0200, Daniel Vetter wrote:
>> On Wed, Jun 17, 2015 at 09:20:44AM +0100, Dave Gordon wrote:
>>> On 16/06/15 10:24, Chris Wilson wrote:
>>>> On Mon, Jun 15, 2015 at 07:36:30PM +0100, Dave Go
On 22/06/15 13:37, Chris Wilson wrote:
> On Mon, Jun 22, 2015 at 12:59:00PM +0100, Dave Gordon wrote:
>> On 19/06/15 09:44, Chris Wilson wrote:
>>> On Thu, Jun 18, 2015 at 07:07:46PM +0100, Dave Gordon wrote:
>>>> On 18/06/15 13:10, Chris Wilson wrote:
>>&g
On 17/06/15 16:01, Dave Gordon wrote:
> On 15/06/15 21:20, Chris Wilson wrote:
>> On Mon, Jun 15, 2015 at 07:36:22PM +0100, Dave Gordon wrote:
>>> From: Alex Dai
>>>
>>> intel_guc_api.h contains the subset of the GuC interface that we
>>> will ne
On 15/06/15 21:20, Chris Wilson wrote:
> On Mon, Jun 15, 2015 at 07:36:22PM +0100, Dave Gordon wrote:
>> From: Alex Dai
>>
>> intel_guc_api.h contains the subset of the GuC interface that we
>> will need for submission of commands through the GuC. These MUST
On 16/06/15 10:28, Chris Wilson wrote:
> On Mon, Jun 15, 2015 at 07:36:32PM +0100, Dave Gordon wrote:
>> This provides a means of reading status and counts relating
>> to GuC actions and submissions.
>
> Anything that ends to ease debugging also tends to ease
> postmort
On 17/06/15 13:43, Daniel Vetter wrote:
> On Mon, Jun 15, 2015 at 07:36:18PM +0100, Dave Gordon wrote:
>> This patch series enables command submission via the GuC. In this mode,
>> instead of the host CPU driving the execlist port directly, it hands
>> over work items to the
On 24/06/15 10:32, Daniel Vetter wrote:
> On Thu, Jun 18, 2015 at 07:28:26PM +0100, Dave Gordon wrote:
>> On 18/06/15 15:31, Daniel Vetter wrote:
>>> On Thu, Jun 18, 2015 at 12:49:55PM +0100, Dave Gordon wrote:
>>>> On 17/06/15 13:02, Daniel Vetter wrote:
>>&g
mware log
drm/i915: Integrate GuC-based command submission
Documentation/drm: kerneldoc for GuC
Dave Gordon (10):
drm/i915: Add i915_gem_object_create_from_data()
drm/i915: Embedded microcontroller (uC) firmware loading support
drm/i915: Add GuC-related header files
drm/i915: Split lat
, changing their names to
better describe what they do (they're related to logical ring
contexts rather than to execlists per se).
v2:
Replaces previous "drm/i915: Move execlists defines from .c to .h"
Issue: VIZ-4884
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/int
f-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_guc_reg.h | 102 ++
drivers/gpu/drm/i915/intel_guc_fwif.h | 236 +
2 files changed, 338 insertions(+)
create mode 100644 drivers/gpu/drm/i915/i915_guc_reg.h
create mode 100644 drivers/gpu/drm/
used by each uC-specific loader, thus reducing code duplication
and testing effort.
v2:
Local functions should pass dev_priv rather than dev [Chris Wilson]
Various other improvements per Chris Wilson's review comments
Signed-off-by: Dave Gordon
Signed-off-by: Alex Dai
---
drivers/g
-4884
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_debugfs.c | 45 +++
1 file changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index f3b8062..8f53f69 100644
ified firmware loading mechanism by Dave Gordon as well
as new firmware layout etc.
v2:
Various improvements per review comments by Chris Wilson
Issue: VIZ-4884
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/Makefile |3 +
drivers/gpu/drm/i915/i915_
erefore be in non-GuC mode, and will be
allowed to complete even if the GuC cannot be loaded or used.
Issue: VIZ-4884
Signed-off-by: Dave Gordon
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_drv.h |2 ++
drivers/gpu/drm/i915/i915_gem.c |8 -
drivers/gp
ris Wilson]
Rationalise type declarations [Chris Wilson]
Issue: VIZ-4884
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_guc_submission.c | 661
drivers/gpu/drm/i915/intel_guc.h | 43 ++
drivers/gpu/drm/i915/intel_guc_loader.c
tions [Chris Wilson]
Issue: VIZ-4884
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_debugfs.c|2 +-
drivers/gpu/drm/i915/i915_guc_submission.c | 48 +---
drivers/gpu/drm/i915/intel_guc.h |1 +
drivers/gpu/drm
VIZ-4884
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_drv.h |2 ++
drivers/gpu/drm/i915/i915_gem.c | 39 +++
2 files changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv
the inline loop with a call.
This will allow a future patch to add a call from another
locations (for now, there are no other calls).
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/i915_gem.c | 85 ++-
2 files
and the GuC's debug log.
v2:
Remove redundant initialisation [Chris Wilson]
Defer adding struct members until needed [Chris Wilson]
Local functions should pass dev_priv rather than dev [Chris Wilson]
Issue: VIZ-4884
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
drivers/gp
From: Alex Dai
Two new module parameters: "enable_guc_submission" which will turn
on submission of batchbuffers via the GuC (when implemented), and
"guc_log_level" which controls the level of debugging logged by the
GuC and captured by the host.
Signed-off-by: Alex Dai
From: Alex Dai
Allocate a GEM object to hold GuC log data. A debugfs interface
(i915_guc_log_dump) is provided to print out the log content.
v2:
Add struct members at point of use [Chris Wilson]
Issue: VIZ-4884
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915
From: Alex Dai
Add overview design of GuC, plus some key points related to
the implementation.
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
Documentation/DocBook/drm.tmpl | 19 +++
1 file changed, 19 insertions(+)
diff --git a/Documentation/DocBook/drm.tmpl b
This provides a means of reading status and counts relating
to GuC actions and submissions.
v2:
Remove surplus blank line in output [Chris Wilson]
Signed-off-by: Dave Gordon
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_debugfs.c | 40 +++
1 file
Turn on interrupt steering to route necessary interrupts to GuC.
Issue: VIZ-4884
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_reg.h | 11 +--
drivers/gpu/drm/i915/intel_guc_loader.c | 51 +++
2 files changed, 60
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_params.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index a8f48dd..479c97b 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b
On 26/06/15 08:31, Chris Wilson wrote:
> On Thu, Jun 25, 2015 at 01:57:16PM -0700, Yu Dai wrote:
>>
>> On 06/25/2015 07:40 AM, Dave Gordon wrote:
>>> GuC submission is basically execlist submission, but with the GuC
>>> handling the actual writes to the ELSP and
On 24/06/15 11:04, Chris Wilson wrote:
> On Tue, Jun 23, 2015 at 07:45:42AM +0200, Sedat Dilek wrote:
>> I have seen this typo once and added an entry to codespell's dictionary.txt
>> file.
>>
>> $ diff -uprN /usr/share/codespell/dictionary.txt.orig
>> /usr/share/codespell/dictionary.txt
>> --- /
On 23/06/15 13:21, Michel Thierry wrote:
> Gen8+ supports 48-bit virtual addresses, but some objects must always be
> allocated inside the 32-bit address range.
>
> In specific, any resource used with flat/heapless (0x-0xf000)
> General State Heap (GSH) or Intruction State Heap (ISH) m
On 16/06/15 21:38, Chris Wilson wrote:
> On Tue, Jun 16, 2015 at 08:25:23PM +0100, Arun Siluvery wrote:
>> +/* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
>> +if (IS_BROADWELL(ring->dev)) {
>> +struct drm_i915_private *dev_priv = ring->dev->dev_private;
>
> dev_priv = to_
On 25/06/15 18:51, Chris Wilson wrote:
> On Thu, Jun 25, 2015 at 06:35:14PM +0300, Mika Kuoppala wrote:
>> During review of dynamic page tables series, I was able
>> to hit a lite restore bug with execlists. I assume that
>> due to incorrect pd, the batch run out of legit address space
>> and into
On 25/06/15 19:38, Tomas Elf wrote:
> On 24/06/2015 18:03, john.c.harri...@intel.com wrote:
>> From: John Harrison
>>
>> An earlier patch was added to reserve space in the ring buffer for the
>> commands issued during 'add_request()'. The initial version was
>> pessimistic in the way it handled bu
On 29/06/15 12:39, Jani Nikula wrote:
> On Wed, 06 May 2015, Daniel Vetter wrote:
>> On Thu, Apr 30, 2015 at 01:54:41PM +0100, Dave Gordon wrote:
>>> On 29/04/15 17:10, yu@intel.com wrote:
>>>> From: Alex Dai
>>>>
>>>> This is to
containing LRI instructions to
set up context-specific registers.
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/i915_gem.c | 15 ++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu
more complete environment
than the driver_load stage presents. This can be important for
embedded programmable devices that need firmware loaded from a file
before they can be used.
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/i915_
On 01/07/15 14:02, Daniel Vetter wrote:
On Tue, Jun 30, 2015 at 11:14:54AM -0300, Paulo Zanoni wrote:
2015-06-30 10:54 GMT-03:00 Chris Wilson :
On Tue, Jun 30, 2015 at 02:41:09PM +0100, Michel Thierry wrote:
@@ -1109,7 +1109,7 @@ static void setup_sink_crc(void)
set_mode_for_params(&pri
previously part of an internal patch, but which was omitted from
the version recently committed to drm-intel-nightly:
7a01a0a drm/i915/lrc: Update PDPx registers with lri commands
So we reinstate this change here.
Issue: VIZ-4884
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i
-4884
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_debugfs.c | 45 +
1 file changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 71ba519..65d40f1 100644
VIZ-4884
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_gem.c | 40
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index
ach uC-specific loader, thus reducing code duplication
and testing effort.
v2:
Local functions should pass dev_priv rather than dev [Chris Wilson]
Various other improvements per Chris Wilson's review comments
v3:
Defeatured version without async prefetch [Daniel Vetter]
Signed
ommon firmware loading mechanism by Dave Gordon as well
as new firmware layout etc.
v2:
Various improvements per review comments by Chris Wilson
v3:
Removed 'wait' parameter to intel_guc_ucode_load() as prefetch
is no longer supported in the common firmware loader, per
From: Alex Dai
Allocate a GEM object to hold GuC log data. A debugfs interface
(i915_guc_log_dump) is provided to print out the log content.
v2:
Add struct members at point of use [Chris Wilson]
Issue: VIZ-4884
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915
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