On 22/01/16 14:48, Ville Syrjälä wrote:
On Fri, Jan 22, 2016 at 12:51:23PM +, Damien Lespiau wrote:
We are reading at most sizeof(data) bytes, but then data may not contain
a terminating '\0', at least in theory, so strstr() may overflow the
stack allocated array.
Make sure that data always
On 22/01/16 13:34, Chris Wilson wrote:
On Fri, Jan 22, 2016 at 01:17:44PM +, Tvrtko Ursulin wrote:
On 22/01/16 13:01, Chris Wilson wrote:
On Fri, Jan 22, 2016 at 12:19:32PM +, Dave Gordon wrote:
In the error-handling paths of i915_gem_do_execbuffer() and
intel_crtc_page_flip(), the
tests need to be
updated to accommodate this case.
v2: Added testcase (Chris Wilson)
Testcase: igt/gem_close_race
Signed-off-by: Dave Gordon
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 2 +-
2 files changed, 2
On 23/01/16 17:54, Chris Wilson wrote:
intel_rcs_ctx_init() can be interrupted by a signal (if it has to wait
upon a full ring to advance). Don't emit an error for this.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++--
1 file changed, 2 insertions(+), 2 delet
On 25/01/16 18:17, Daniel Vetter wrote:
On Fri, Jan 22, 2016 at 05:54:15PM +0530, akash.g...@intel.com wrote:
From: Akash Goel
Added a new macro i915_dbg, which is a wrapper over dev_dbg macro.
dev_dbg allows use of dynamic debug framework, so offers a number
of advantages over DRM_DEBUG to de
On 26/01/16 14:42, Joe Perches wrote:
On Tue, 2016-01-26 at 11:10 +0200, Jani Nikula wrote:
Different subsystems and drivers have different preferred ways of
receiving bug reports; mailing list or bugzillas at various
locations. Add "B:" entry for specifying the preference to guide bug
reporters
On 26/01/16 14:06, Chris Wilson wrote:
On Tue, Jan 26, 2016 at 01:51:19PM +, Rodrigo Vivi wrote:
On Tue, Jan 26, 2016 at 12:30 AM Chris Wilson
<[1]ch...@chris-wilson.co.uk> wrote:
On Mon, Jan 25, 2016 at 09:17:15PM +, Chris Wilson wrote:
> On Mon, Jan 25, 2016 at 11:
On 26/01/16 09:44, Joonas Lahtinen wrote:
On ma, 2016-01-25 at 18:57 +, Dave Gordon wrote:
On 25/01/16 18:17, Daniel Vetter wrote:
On Fri, Jan 22, 2016 at 05:54:15PM +0530, akash.g...@intel.com
wrote:
From: Akash Goel
Added a new macro i915_dbg, which is a wrapper over dev_dbg
macro
On 27/01/16 15:36, Ville Syrjälä wrote:
On Wed, Jan 27, 2016 at 03:02:15PM +, Morton, Derek J wrote:
-Original Message-
From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
Sent: Wednesday, January 27, 2016 2:31 PM
To: Morton, Derek J
Cc: intel-gfx@lists.freedesktop.org
Subje
On 27/01/16 13:50, Chris Wilson wrote:
On Wed, Jan 27, 2016 at 01:13:54PM +, Daniele Ceraolo Spurio wrote:
On 27/01/16 09:38, Chris Wilson wrote:
On Wed, Jan 27, 2016 at 08:55:40AM +, daniele.ceraolospu...@intel.com wrote:
From: Daniele Ceraolo Spurio
While running some tests on th
wildcard expression is
insufficient.
v2: Use comma as list separator (Ville Syrjala)
support both ^ and ! as not operators (Dave Gordon)
Signed-off-by: Derek Morton
---
lib/igt_core.c | 48 ++--
1 file changed, 46 insertions(+), 2 deletions(-)
diff --git
nature of lrc_setup_hardware_status_page()
to match
so that all knowledge of this special arrangement is local to these
two functions.
It will also help with efforts in progress to eliminate special
handling of the default (kernel) context elsewhere in LRC code :)
v3: Rebased
Signed-off-by: Dave Gordon
---
dr
ation.
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_gem.c | 5 -
drivers/gpu/drm/i915/intel_lrc.c | 10 ++
2 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 371bbb2..12f7e3e 100644
--- a/dr
as first implemented.
v3:
Rebased.
Signed-off-by: Dave Gordon
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index b0e4605.
() rather than repeat the mapping calculation.
[Chris Wilson]
Signed-off-by: Dave Gordon
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index d6e2e8f.
at it actually does
(cleanup engines, not a ringbuffer), and fix an annoying whitespace
issue.
v2: Also make the fix in i915_load_modeset_init, not just in
i915_driver_unload (Chris Wilson)
v3: Had extra stuff in it.
v4: Reverted extra stuff (so we're back to v2).
Rebased and updated comme
tches 3 and 5.
The former could stand alone; the latter depends on patch 4 and is
a prerequisite for Nick's patch [6/6] to function.
Dave Gordon (5):
drm/i915: tidy up initialisation failure paths (legacy)
drm/i915: tidy up initialisation failure paths (GEM & LRC)
;.
v3:
Make intel_unpin_ringbuffer_obj() return early if ringbuffer is
not mapped, simplifying matters for the caller. [Chris Wilson,
Daniel Vetter]
Don't bother to clear a pointer in an object about to be freed.
[Chris Wilson]
Signed-off-by: Dave Gordon
Cc: Chris Wilson
---
drivers/gpu/drm/i91
On 28/01/16 12:57, Dave Gordon wrote:
On 28/01/16 11:05, Derek Morton wrote:
Added support for specifying arbitary lists of subtests to run, or
to exclude from being run if prefixed by ^ or !.
subtest1,subtest2 Will run subtest1 and subtest2
^subtest1,subtest2 or !subtest1,subtest2 will run
at it actually does
(cleanup engines, not a ringbuffer), and fix an annoying whitespace
issue.
v2: Also make the fix in i915_load_modeset_init, not just in
i915_driver_unload (Chris Wilson)
v3: Had extra stuff in it.
v4: Reverted extra stuff (so we're back to v2).
Rebased and updated comme
ation.
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_gem.c | 5 -
drivers/gpu/drm/i915/intel_lrc.c | 10 ++
2 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a928823..5a4d468 100644
--- a/dr
;.
v3:
Make intel_unpin_ringbuffer_obj() return early if ringbuffer is
not mapped, simplifying matters for the caller. [Chris Wilson,
Daniel Vetter]
Don't bother to clear a pointer in an object about to be freed.
[Chris Wilson]
Signed-off-by: Dave Gordon
Cc: Chris Wilson
---
drivers/gpu/drm/i91
() rather than repeat the mapping calculation.
[Chris Wilson]
Signed-off-by: Dave Gordon
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 60d7cdd.
tches 3 and 5.
The former could stand alone; the latter depends on patch 4 and is
a prerequisite for Nick's patch [6/6] to function.
v4:
Rebased
Dave Gordon (5):
drm/i915: tidy up initialisation failure paths (legacy)
drm/i915: tidy up initialisation failure paths (GEM & LRC)
nature of lrc_setup_hardware_status_page()
to match
so that all knowledge of this special arrangement is local to these
two functions.
It will also help with efforts in progress to eliminate special
handling of the default (kernel) context elsewhere in LRC code :)
v3: Rebased
Signed-off-by: Dave Gordon
---
dr
as first implemented.
v3:
Rebased.
Signed-off-by: Dave Gordon
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index ff38e57.
On 30/01/16 10:50, Chris Wilson wrote:
On Fri, Jan 29, 2016 at 07:19:26PM +, Dave Gordon wrote:
1. Fix intel_cleanup_ring_buffer() to handle the error cleanup
case where the ringbuffer has been allocated but map-and-pin
failed. Unpin it iff it's previously been mapped-and-pinne
On 30/01/16 11:28, Chris Wilson wrote:
On Sat, Jan 30, 2016 at 10:56:27AM +, Chris Wilson wrote:
On Fri, Jan 29, 2016 at 07:19:27PM +, Dave Gordon wrote:
1. add call to i915_gem_context_fini() to deallocate the default
context(s) if the call to init_rings() fails, so that we don&#
Wilson
Cc: Dave Gordon
Cc: Rodrigo Vivi
---
Generally, yes, but ...
drivers/gpu/drm/i915/intel_lrc.c | 41
1 file changed, 21 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index
On 02/02/16 11:06, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
This is for callers who want micro-second precision but are not
waiting from the atomic context.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_dp.c | 3 +--
drivers/gpu/drm/i915/intel_drv.h | 9 +
driver
On 02/02/16 12:00, Chris Wilson wrote:
On Tue, Feb 02, 2016 at 11:06:20AM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Looks like this code does not need to wait atomically since it
otherwise takes the mutex.
Signed-off-by: Tvrtko Ursulin
Cc: Ville Syrjälä
Reviewed-by: Ville Syrjälä
-
ode_response(dev_priv, &status), 100);
DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
I915_READ(DMA_CTRL), status);
LGTM.
Reviewed-by: Dave Gordon
___
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allows for either type of
interrupt, while still detecting and complaining about misuse of the
page flip code if it is ever called from non-interrupt context.
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/d
On 06/03/15 15:57, Daniel Vetter wrote:
> On Fri, Mar 06, 2015 at 11:38:44AM +, John Harrison wrote:
>> On 05/03/2015 16:14, Daniel Vetter wrote:
>>> On Thu, Mar 05, 2015 at 03:06:42PM +, John Harrison wrote:
On 05/03/2015 14:44, Daniel Vetter wrote:
> Imo reserving a bit of ring s
ntel_bo *bo)
> * not guarantee that the buffer is re-issued via another thread, or an
> flinked
> * handle. Userspace must make sure this race does not occur if such
> precision
> * is important.
> + *
> + * Note that some kernels have broken the inifite wait for negative values
From: John Harrison
Check whether each engine exists before trying to clean up the
corresponding logical ring.
Change-Id: I31b1ed941824db2d6bd7233360dbce05671979a8
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/intel_lrc.c | 12
1 file changed, 8 insertions(+), 4 deletions
ned-off-by: Dave Gordon
---
drivers/gpu/drm/i915/intel_lrc.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index cd74e5c..3c727d9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gp
ust
one place, ensuring that this confusion does not arise.
Change-Id: Id7ce9096ed100a2882c68a54206f30b6c87e92fa
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_dma.c |5 ++-
drivers/gpu/drm/i915/intel_lrc.c| 36 ++---
drivers/gpu/drm/i915/intel_ringbuffer.c | 53
On 30/10/14 19:26, Ville Syrjälä wrote:
> On Thu, Oct 30, 2014 at 10:32:38AM -0700, Kenneth Graunke wrote:
>> On Thursday, October 30, 2014 01:01:30 PM Ville Syrjälä wrote:
>>> On Thu, Oct 30, 2014 at 02:32:40AM -0700, Kenneth Graunke wrote:
On Thursday, October 30, 2014 11:00:51 AM Ville Syrj
On 31/10/14 14:52, Damien Lespiau wrote:
> On Fri, Oct 31, 2014 at 12:00:26PM +, john.c.harri...@intel.com wrote:
>> From: John Harrison
>>
>> If a ring failed to initialise for any reason then the error path would try
>> to
>> clean up all rings including those that had not yet been allocate
On 03/11/14 20:59, Chris Wilson wrote:
> On Mon, Nov 03, 2014 at 01:29:04PM +0000, Dave Gordon wrote:
>> Fixes to both the LRC and the legacy ringbuffer code to correctly
>> calculate and update the available space in a ring.
>>
>> The logical ring code was updating the
On 06/11/14 14:09, Daniel Vetter wrote:
> On Wed, Nov 05, 2014 at 05:30:52PM +0200, Mika Kuoppala wrote:
>> This reverts commit 5cb13c07dae73380d8b3ddc792740487b8742938.
>>
>> While the relevance for WaRsDontPollForAckOnClearingFWBits is under
>> investigation, revert this as regression.
>>
>> Bugz
f the existing interfaces will see no change from this, but
it will enable TDR to safely access the registers it needs to sample.
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/intel_uncore.c | 61 ---
1 file changed, 49 insertions(+), 12 deletions(-)
diff --
On 07/11/14 15:46, Ville Syrjälä wrote:
> On Wed, Sep 10, 2014 at 07:34:54PM +0100, Chris Wilson wrote:
>> Introduce a structure to track the individual forcewake domains and use
>> that to eliminated duplicate logic.
>> ---
>> drivers/gpu/drm/i915/i915_debugfs.c | 41 +++---
>> drivers/gpu/drm/i
On 18/11/14 15:00, Deepak S wrote:
>
> On Monday 03 November 2014 06:59 PM, Dave Gordon wrote:
>> Fixes to both the LRC and the legacy ringbuffer code to correctly
>> calculate and update the available space in a ring.
>>
>> The logical ring code was updating the so
Fixes to both the LRC and the legacy ringbuffer code to correctly
calculate and update the available space in a ring.
The logical ring code was updating the software ring 'head' value
by reading the hardware 'HEAD' register. In LRC mode, this is not
valid as the hardware is not necessarily executi
other contexts.
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/intel_lrc.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 2a1a719..1003b3a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/driver
there is only one place where the ring space
is updated, and it ALWAYS uses (and consumes) 'last_retired_head' if
(and ONLY if) it has been updated since the last call.
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_dma.c |5 ++-
drivers/gpu/drm/i915
uld put an unrelated (undefined, effectively random) value into
the s/w 'head' -- A Bad Thing for the free space calculations.
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/intel_lrc.c |1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/
On 19/11/14 17:05, John Harrison wrote:
> On 19/11/2014 13:28, Daniel, Thomas wrote:
>>> -Original Message-
>>> From: Harrison, John C
>>> Sent: Wednesday, November 19, 2014 12:26 PM
>>> To: Daniel, Thomas; Intel-GFX@Lists.FreeDesktop.Org
>>> Subject: Re: [Intel-gfx] [PATCH v2 11/28] drm/i9
On 20/11/14 19:13, Chris Wilson wrote:
> For example,
>
> /sys/kernel/debug/dri/0/i915_hangcheck_info:
>
> Hangcheck active, fires in 15887800ms
> render ring:
> seqno = -4059 [current -583]
> action = 2
> score = 0
> ACTHD = 1ee8 [current 21f980]
> max ACT
On 20/11/14 08:45, Daniel Vetter wrote:
> We need to do that every time we resume the rings, not just at load.
> I've overlooked this in my untangling of the ring init code.
Hi Daniel,
another thing that needs untangling in the general maze of init code is
the initialisation of the active and req
On 24/11/14 10:04, Daniel Vetter wrote:
> On Tue, Nov 18, 2014 at 08:07:22PM +0000, Dave Gordon wrote:
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index ae09258..a08ae65 100644
>> --- a/drivers/gpu/drm/i915/
Essentially the same as patch 3/3 from v2 of this set, but split
into two patches; one to improve the robustness of the freespace
calculation, and then one to update all the various places that
calculate free space to call the new improved code. See individual
commit messages for more detail.
there is only one place where the ring space
is updated, and it ALWAYS uses (and consumes) 'last_retired_head' if
(and ONLY if) it has been updated since the last call.
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/intel_lrc.c| 25 ++
drivers/gp
rong.
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/intel_ringbuffer.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 1d01b51..a5cfaae 100644
--- a/drivers
On 26/11/14 18:10, Daniel Vetter wrote:
> On Wed, Nov 26, 2014 at 05:07:29PM +0200, ville.syrj...@linux.intel.com wrote:
>> From: Ville Syrjälä
>>
>> Clear the video overlay state on GPU reset. Any pending overlay request
>> in the ring has been nuked, and the display itself gets reset. So we
>> p
Vetter
Reviewed-by: Dave Gordon
> ---
> drivers/gpu/drm/i915/intel_lrc.c| 14 +++---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 12 ++--
> drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
> 3 files changed, 14 insertions(+), 14 deletions(-)
>
> dif
be "s/init_workarounds_ring/init_render_workarounds/",
with no mention of "intel_" !
Once that's corrected, then
Reviewed-by: Dave Gordon
.Dave.
> drivers/gpu/drm/i915/intel_lrc.c| 2 +-
> drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++--
> drivers/g
it would be nice to move the init_hw() out of
intel_init_ring_buffer() and logical_ring_init() so that they actually
do what their names say, but I see that's forthcoming, so
Reviewed-by: Dave Gordon
.Dave.
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tter
> ---
> drivers/gpu/drm/i915/i915_gem.c | 13 ++---
> drivers/gpu/drm/i915/intel_lrc.c| 6 --
> drivers/gpu/drm/i915/intel_ringbuffer.c | 4
> 3 files changed, 10 insertions(+), 13 deletions(-)
Yep, that's what I was hoping for :)
Review
On 28/11/14 09:29, Daniel Vetter wrote:
> We've lost the +1 required for correct timeouts in
>
> commit 5ed0bdf21a85d78e04f89f15ccf227562177cbd9
> Author: Thomas Gleixner
> Date: Wed Jul 16 21:05:06 2014 +
>
> drm: i915: Use nsec based interfaces
>
> Use ktime_get_raw_ns() and get
should developers try to
submit corresponding changes to both paths together (e.g. in the same
patchset). Or is it OK to submit improvements only to one of the two
paths, causing them to diverge and hence possibly making deduplication
more difficult?
Anyway, this change looks OK in
On 21/11/14 20:27, Daniel Vetter wrote:
> On Fri, Nov 21, 2014 at 07:01:54PM +0000, Dave Gordon wrote:
>> On 20/11/14 08:45, Daniel Vetter wrote:
>>> We need to do that every time we resume the rings, not just at load.
>>> I've overlooked this in my untangling
On 02/12/14 15:19, Daniel Vetter wrote:
> Similar to a patch from Thomas Daniel for lrc contexts. This keeps
> both sides somewhat in sync and should make Dave Gordon happy.
>
> Note that both the wa and the golden context init code suffer a bit
> from an inssuficient split into
On 08/12/14 13:59, Damien Lespiau wrote:
> On Mon, Dec 08, 2014 at 02:33:57PM +0200, Jani Nikula wrote:
>>> #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
>>> #define _MASKED_BIT_DISABLE(a) ((a) << 16)
>>> +#define _MASKED_FIELD(value, mask) (((mask) << 16) | (value))
>>
>> Obligatory bikeshed
rently more
generic definition is actually a pre-GEN4 legacy from the days when the
instruction had only 3 words? Perhaps a comment here from somebody who
knows -- or even something like
#define MI_STORE_DWORD_IMM_LEGACY MI_INSTR(0x20, 1) /* pre-GEN4 */
#define MI_STO
On 08/12/14 16:27, Daniel Vetter wrote:
> On Mon, Dec 08, 2014 at 04:22:27PM +, Damien Lespiau wrote:
>> I was playing with clang and oh surprise! a warning trigerred by
>> -Wshift-overflow (gcc doesn't have this one):
[snip]
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> b/drive
around list in ring initialization
>
> v2: Invert the order of the mask and value arguments (Daniel Vetter)
> Rewrite _MASKED_BIT_ENABLE() and _MASKED_BIT_DISABLE() with
> _MASKED_FIELD() (Jani Nikula)
> Make sure we only evaluate 'a' once in _MASKED_BIT_ENABLE
n the
mean time, the traditional single-level begin/advance mechanism remains
fully supported.
This commit changes only the begin/advance checking code, to permit (but
not require) nested begin/advance pairs.
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/intel_ringbuffer.h |
When adding instructions to a legacy or LRC ringbuffer, the sequence of
emit() calls must be preceded by a call to intel(_logical)_ring_begin()
to reserve the required amount of space, and followed by a matching call
to intel(_logical)_ring_advance(). Historically some (display) code
didn't use be
ut an advance between
* exceeding the space reserved by begin
* leaving the ring misaligned
* ring buffer overrun (negative freespace)
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/intel_lrc.c|4 ++-
drivers/gpu/drm/i915/intel_lrc.h| 11 ++-
drivers/gpu/drm
On 10/12/14 09:11, Daniel Vetter wrote:
> On Wed, Dec 10, 2014 at 02:18:15AM +, Gong, Zhipeng wrote:
>> On Tue, 2014-12-09 at 10:46 +0100, Daniel Vetter wrote:
>>> On Mon, Dec 08, 2014 at 01:55:56PM -0800, Rodrigo Vivi wrote:
[snip]
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
ut an advance between
* exceeding the space reserved by begin
* leaving the ring misaligned
* ring buffer overrun (negative freespace)
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/intel_lrc.c|4 ++-
drivers/gpu/drm/i915/intel_lrc.h| 11 ++-
drivers/gpu/drm
n the
mean time, the traditional single-level begin/advance mechanism remains
fully supported.
This commit changes only the begin/advance checking code, to permit (but
not require) nested begin/advance pairs.
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/intel_ringbuffer.h |
When adding instructions to a legacy or LRC ringbuffer, the sequence of
emit() calls must be preceded by a call to intel(_logical)_ring_begin()
to reserve the required amount of space, and followed by a matching call
to intel(_logical)_ring_advance(). Historically some (display) code
didn't use be
On 10/12/14 10:58, Daniel Vetter wrote:
> On Tue, Dec 09, 2014 at 12:59:11PM +, john.c.harri...@intel.com wrote:
>> From: John Harrison
>>
>> The scheduler decouples the submission of batch buffers to the driver with
>> their
>> submission to the hardware. This basically means splitting the e
On 10/12/14 10:40, Daniel Vetter wrote:
> On Tue, Dec 09, 2014 at 12:59:06PM +, john.c.harri...@intel.com wrote:
>> From: Dave Gordon
>>
>> Added various definitions that will be useful for the scheduler in general
>> and
>> pre-emptive context switchi
On 10/12/14 10:42, Daniel Vetter wrote:
> On Tue, Dec 09, 2014 at 12:59:08PM +, john.c.harri...@intel.com wrote:
>> From: Dave Gordon
>>
>> There is a workaround for a hardware bug when reading the seqno from the
>> status
>> page. The bug does not exist o
TCH 8/8] drm/i915: Enum forcewake domains and domain identifiers
Change-Id: Id1a9f3785cb20b82d4caa330c37b31e4e384a3ef
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/intel_uncore.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm
[PATCH 1/3] drm/i915: use effective_size for ringbuffer calculations
When calculating the available space in a ringbuffer, we should
use the effective_size rather than the true size of the ring.
[PATCH 2/3] drm/i915: recheck ringspace after wait+retire
When a ringbuffer is nearly ful
same check
in the legacy ringbuffer mode too.
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/intel_lrc.c|9 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 12 +++-
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/driver
When calculating the available space in a ringbuffer, we should
use the effective_size rather than the true size of the ring.
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/intel_lrc.c|2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c |5 +++--
2 files changed, 4 insertions
ut an advance between
* exceeding the space reserved by begin
* leaving the ring misaligned
* ring buffer overrun (negative freespace)
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/intel_lrc.c|4 ++-
drivers/gpu/drm/i915/intel_lrc.h| 11 ++-
drivers/gpu/drm
On 12/12/14 17:12, Chris Wilson wrote:
> On Fri, Dec 12, 2014 at 04:13:03PM +0000, Dave Gordon wrote:
>> static inline void intel_ring_advance(struct intel_engine_cs *ring)
>> {
>> struct intel_ringbuffer *ringbuf = ring->buffer;
>> -ring
ut an advance between
* exceeding the space reserved by begin
* leaving the ring misaligned
* ring buffer overrun (negative freespace)
v2: more deduplication (Chris)
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/intel_lrc.c|3 +-
drivers/gpu/drm/i915/intel_lrc.h|
On 05/06/15 11:04, Damien Lespiau wrote:
> On Fri, Jun 05, 2015 at 12:27:21PM +0300, Ville Syrjälä wrote:
>> On Fri, Jun 05, 2015 at 12:24:45PM +0300, Jani Nikula wrote:
>>> On Thu, 04 Jun 2015, Ville Syrjälä wrote:
On Thu, Jun 04, 2015 at 04:56:18PM +0100, Damien Lespiau wrote:
> I notic
On 27/05/15 10:17, David Weinehall wrote:
> On Thu, May 21, 2015 at 10:50:37AM +0100, Chris Wilson wrote:
>> It also have just as much risk as reporting EBUSY due to the CL client
>> trying to use a pinned buffer.
>>
>> However, it is a security hole because the same process can arrange to
>> have
On 08/06/15 17:28, Imre Deak wrote:
> By running igt/store_dword_loop_render on BXT we can hit a coherency
> problem where the seqno written at GPU command completion time is not
> seen by the CPU. This results in __i915_wait_request seeing the stale
> seqno and not completing the request (not cons
to become the execbuffer code, in
> 82e104c drm/i915/bdw: New logical ring submission mechanism
So now we have to fix it in both paths ...
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/intel_lrc.c|6 +++---
drivers/gpu/drm/i915/intel_ringbuffer.c |
On 08/06/15 19:40, Ville Syrjälä wrote:
> On Mon, Jun 08, 2015 at 07:00:49PM +0100, Chris Wilson wrote:
>> On Mon, Jun 08, 2015 at 08:34:51PM +0300, Ville Syrjälä wrote:
>>> On Mon, Jun 08, 2015 at 06:12:47PM +0100, Chris Wilson wrote:
>>>> On Mon, Jun 08, 2015 at
On 08/06/15 18:42, Abdiel Janulgue wrote:
>
> On 06/08/2015 07:10 PM, Ville Syrjälä wrote:
>> On Mon, Jun 08, 2015 at 01:04:07PM +0300, Abdiel Janulgue wrote:
>>> Adds support for executing the resource streamer on BDW and HSW
>>>
>>> v2: Add support for Execlists (Minu Mathai )
>>>
>>> Reviewed-b
On 05/06/15 14:08, Ville Syrjälä wrote:
> On Fri, Jun 05, 2015 at 02:00:24PM +0100, Minu Mathai wrote:
>> From: Minu
>>
>> Display CRCs were not readable because the register defintions
>> for PORT_DFT_I9XX and PORT_DFT2_G4X were wrong.
>> MMIO offset needs to be added to these register offsets to
On 05/06/15 11:34, Arun Siluvery wrote:
> Some of the WA applied using WA batch buffers perform writes to scratch page.
> In the current flow WA are initialized before scratch obj is allocated.
> This patch reorders intel_init_pipe_control() to have a valid scratch obj
> before we initialize WA.
>
On 05/06/15 11:34, Arun Siluvery wrote:
> In Indirect context w/a batch buffer,
> +WaFlushCoherentL3CacheLinesAtContextSwitch
>
> Signed-off-by: Rafael Barbalho
> Signed-off-by: Arun Siluvery
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_lrc.c | 8
> 2 fi
On 05/06/15 14:57, Arun Siluvery wrote:
> In Per context w/a batch buffer,
> WaRsRestoreWithPerCtxtBb
>
> v2: This patches modifies definitions of MI_LOAD_REGISTER_MEM and
> MI_LOAD_REGISTER_REG; Add GEN8 specific defines for these instructions
> so as to not break any future users of existing def
On 10/06/15 09:09, Jani Nikula wrote:
> On Tue, 09 Jun 2015, Dave Gordon wrote:
>> Regardless of whether it's used, we have an inconsistency between the
>> definitions of PORT_DFT_I9XX and PORT_DFT2_G4X -- one includes the
>> mmio_offset and the other doesn't.
&
On 10/06/15 12:42, Michel Thierry wrote:
> On 5/29/2015 1:53 PM, Michel Thierry wrote:
>> On 5/29/2015 12:05 PM, Michel Thierry wrote:
>>> On 5/22/2015 6:04 PM, Mika Kuoppala wrote:
With BDW/SKL and 32bit addressing mode only, the hardware preloads
pdps. However the TLB invalidation only
On 10/06/15 16:52, Chris Wilson wrote:
> On Wed, Jun 10, 2015 at 06:26:58PM +0300, Imre Deak wrote:
>> On ke, 2015-06-10 at 08:10 -0700, Jesse Barnes wrote:
>>> On 06/10/2015 03:59 AM, Imre Deak wrote:
I think the discussion here is about two separate things:
1. Possible ordering issue be
On 10/06/15 15:58, Chris Wilson wrote:
> As the clflush operates on cache lines, and we can flush any byte
> address, in order to flush all bytes given in the range we issue an
> extra clflush on the last byte to ensure the last cacheline is flushed.
> We can can the iteration to be over the actual
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