[PATCH v5 07/11] drm/i915/xe3lpd: Move async flip bit to PLANE_SURF register

From: Dnyaneshwar Bhadane The async flip moved from PLANE_CTL to PLANE_SURF for Xe3_LPD. Bspec: 69853,69878 Signed-off-by: Dnyaneshwar Bhadane Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor Reviewed-by: Shekhar Chauhan --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 13

[PATCH v4 06/11] drm/i915/cx0: Remove bus reset after every c10 transaction

C10 phy timeouts occur on xe3lpd if the c10 bus is reset every transaction. Starting with xe3lpd this is bus reset not necessary Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm

[PATCH v4 09/11] drm/i915/display/xe3: disable x-tiled framebuffers

From: "Heikkila, Juha-pekka" Xe3 has no more support for x-tile on display. v2: Include up to display 29 for X-tiled support. (Gustavo) Signed-off-by: Heikkila, Juha-pekka Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor Reviewed-by: Gustavo Sousa --- drivers/gpu/drm/i9

[PATCH v3 05/11] drm/i915/cx0: Extend C10 check to PTL

From: Dnyaneshwar Bhadane When deciding the type of the phy, add PTL support to make sure the correct path is taken for selection of C10 PHY. Only port A is connected C10 PHY for Pantherlake. Bspec: 72571 Signed-off-by: Dnyaneshwar Bhadane Signed-off-by: Matt Atwood Signed-off-by: Clint

[PATCH v3 01/11] drm/i915/xe3lpd: Update pmdemand programming

splay_ver check, use INTEL_NUM_PIPES v4: add a conditional for number of pipes macro vs using 3. v5: reverse conditional order of v4. v6: undo v5 and fix num_pipes assignment Bspec: 68883, 69125 Signed-off-by: Matt Roper Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor --- drivers/

[PATCH v3 08/11] drm/i915/xe3: Underrun recovery does not exist post Xe2

From: Ravi Kumar Vodapalli >From platforms xe3 Underrun recovery does not exist v2: improve DISPLAY_VER checking BSpec: 68849 Signed-off-by: Ravi Kumar Vodapalli Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor Reviewed-by: Sai Teja Pottumuttu --- drivers/gpu/drm/i915/disp

[PATCH v3 02/11] drm/i915/xe3lpd: Disable HDCP Line Rekeying for Xe3

From: Suraj Kandpal We need to disable HDCP Line Rekeying for Xe3 when we are using an HDMI encoder. v2: add additional definition instead of function, commit message typo fix and update. v3: restore lost conditional from v2. v4: subject line and subject message updated, fix the if ladder order,

[PATCH v3 03/11] drm/i915/xe3lpd: Add check to see if edp over type c is allowed

display version check [Jani] -change the warn on condition [Jani] -no need for a different function for edp type c check [Jani] -dont add register in i915_reg [Jani] Bspec: 68846 Signed-off-by: Suraj Kandpal Signed-off-by: Matt Atwood Reviewed-by: Mika Kahola Signed-off-by: Clint Taylor

[PATCH v3 07/11] drm/i915/xe3lpd: Move async flip bit to PLANE_SURF register

From: Dnyaneshwar Bhadane The async flip moved from PLANE_CTL to PLANE_SURF for Xe3_LPD. Bspec: 69853,69878 Signed-off-by: Dnyaneshwar Bhadane Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor Reviewed-by: Shekhar Chauhan --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 13

[PATCH v3 09/11] drm/i915/display/xe3: disable x-tiled framebuffers

From: "Heikkila, Juha-pekka" Xe3 has no more support for x-tile on display. v2: Include up to display 29 for X-tiled support. (Gustavo) Signed-off-by: Heikkila, Juha-pekka Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor Reviewed-by: Gustavo Sousa --- drivers/gpu/drm/i9

[PATCH v4 02/11] drm/i915/xe3lpd: Disable HDCP Line Rekeying for Xe3

, fix the bit definition order. Signed-off-by: Suraj Kandpal Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/display/intel_hdcp.c | 10 +++--- drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a

[PATCH v4 03/11] drm/i915/xe3lpd: Add check to see if edp over type c is allowed

display version check [Jani] -change the warn on condition [Jani] -no need for a different function for edp type c check [Jani] -dont add register in i915_reg [Jani] Bspec: 68846 Signed-off-by: Suraj Kandpal Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/display

[PATCH v4 10/11] drm/i915/xe3lpd: Skip disabling VRR during modeset disable

From: Ravi Kumar Vodapalli Spec does not request to disable VRR in the modeset disabling sequence for DP and HDMI for xe3_lpd. Bspec: 68848 Signed-off-by: Ravi Kumar Vodapalli Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/display/intel_display.c | 8

[PATCH v4 08/11] drm/i915/xe3: Underrun recovery does not exist post Xe2

From: Ravi Kumar Vodapalli >From platforms xe3 Underrun recovery does not exist v2: improve DISPLAY_VER checking BSpec: 68849 Signed-off-by: Ravi Kumar Vodapalli Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor Reviewed-by: Sai Teja Pottumuttu --- drivers/gpu/drm/i915/disp

[PATCH v4 01/11] drm/i915/xe3lpd: Update pmdemand programming

splay_ver check, use INTEL_NUM_PIPES v4: add a conditional for number of pipes macro vs using 3. v5: reverse conditional order of v4. v6: undo v5 and fix num_pipes assignment Bspec: 68883, 69125 Signed-off-by: Matt Roper Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor --- drivers/

[PATCH v3 10/11] drm/i915/xe3lpd: Skip disabling VRR during modeset disable

From: Ravi Kumar Vodapalli Spec does not request to disable VRR in the modeset disabling sequence for DP and HDMI for xe3_lpd. Bspec: 68848 Signed-off-by: Ravi Kumar Vodapalli Signed-off-by: Matt Atwood --- drivers/gpu/drm/i915/display/intel_display.c | 8 +--- 1 file changed, 5 insertion

[PATCH v4 07/11] drm/i915/xe3lpd: Move async flip bit to PLANE_SURF register

From: Dnyaneshwar Bhadane The async flip moved from PLANE_CTL to PLANE_SURF for Xe3_LPD. Bspec: 69853,69878 Signed-off-by: Dnyaneshwar Bhadane Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor Reviewed-by: Shekhar Chauhan --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 13

[PATCH v4 04/11] drm/i915/ptl: Define IS_PANTHERLAKE macro

From: Dnyaneshwar Bhadane Common display code requires IS_PANTHERLAKE macro. Define the macro and set 0 as PTL is no longer support for i915. Signed-off-by: Dnyaneshwar Bhadane Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor Reviewed-by: Matt Roper --- drivers/gpu/drm/i915

[PATCH v3 04/11] drm/i915/ptl: Define IS_PANTHERLAKE macro

From: Dnyaneshwar Bhadane Common display code requires IS_PANTHERLAKE macro. Define the macro and set 0 as PTL is no longer support for i915. Signed-off-by: Dnyaneshwar Bhadane Signed-off-by: Matt Atwood Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/i915_drv.h | 1 + 1 file changed, 1 ins

[PATCH v5 11/11] drm/xe/ptl: Enable PTL display

From: Haridhar Kalvala Signed-off-by: Haridhar Kalvala Signed-off-by: Clint Taylor --- drivers/gpu/drm/xe/xe_pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index 4085bb3b6550..6f73a243c24c 100644 --- a

[PATCH v5 10/11] drm/i915/xe3lpd: Power request asserting/deasserting

busy bit and command value with 0x1 4. Read mailbox command and wait until run/busy bit is clear before continuing power request. Signed-off-by: Mika Kahola Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/display/intel_tc.c | 40 +

[PATCH v5 00/11] drm/i915/xe3lpd: ptl display patches

This series builds on the previous v4, Review Comments have addressed for the first 2 patches in a series. 1 more VRR related patch dropped. PTL display enabling patch added. Clint Taylor (1): drm/i915/cx0: Remove bus reset after every c10 transaction Dnyaneshwar Bhadane (3): drm/i915/ptl

[PATCH v5 08/11] drm/i915/xe3: Underrun recovery does not exist post Xe2

From: Ravi Kumar Vodapalli >From platforms xe3 Underrun recovery does not exist v2: improve DISPLAY_VER checking BSpec: 68849 Signed-off-by: Ravi Kumar Vodapalli Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor Reviewed-by: Sai Teja Pottumuttu --- drivers/gpu/drm/i915/disp

[PATCH v5 06/11] drm/i915/cx0: Remove bus reset after every c10 transaction

C10 phy timeouts occur on xe3lpd if the c10 bus is reset every transaction. Starting with xe3lpd this is bus reset not necessary Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm

[PATCH v5 01/11] drm/i915/xe3lpd: Update pmdemand programming

splay_ver check, use INTEL_NUM_PIPES v4: add a conditional for number of pipes macro vs using 3. v5: reverse conditional order of v4. v6: undo v5 and fix num_pipes assignment v7: pass display struct instead of i915, checkpatch fix Bspec: 68883, 69125 Signed-off-by: Matt Roper Signed-off-by: Matt Atwood

[PATCH v5 02/11] drm/i915/xe3lpd: Disable HDCP Line Rekeying for Xe3

conditional from v2. v4: subject line and subject message updated, fix the if ladder order, fix the bit definition order. v5: Add the bspec link and remove the Wa comment tag Bspec: 68933 Signed-off-by: Suraj Kandpal Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor Signed-off-by: Clint

[PATCH v2 10/12] drm/i915/display/xe3: disable x-tiled framebuffers

From: "Heikkila, Juha-pekka" Xe3 has no more support for x-tile on display. v2: Include up to display 29 for X-tiled support. (Gustavo) Signed-off-by: Heikkila, Juha-pekka Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/display/intel_fb.c | 2

[PATCH v5 03/11] drm/i915/xe3lpd: Add check to see if edp over type c is allowed

display version check [Jani] -change the warn on condition [Jani] -no need for a different function for edp type c check [Jani] -dont add register in i915_reg [Jani] Bspec: 68846 Signed-off-by: Suraj Kandpal Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/display

[PATCH v5 05/11] drm/i915/cx0: Extend C10 check to PTL

From: Dnyaneshwar Bhadane When deciding the type of the phy, add PTL support to make sure the correct path is taken for selection of C10 PHY. Only port A is connected C10 PHY for Pantherlake. Bspec: 72571 Signed-off-by: Dnyaneshwar Bhadane Signed-off-by: Matt Atwood Signed-off-by: Clint

[PATCH v5 09/11] drm/i915/display/xe3: disable x-tiled framebuffers

From: "Heikkila, Juha-pekka" Xe3 has no more support for x-tile on display. v2: Include up to display 29 for X-tiled support. (Gustavo) Signed-off-by: Heikkila, Juha-pekka Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor Reviewed-by: Gustavo Sousa --- drivers/gpu/drm/i9

[PATCH v5 04/11] drm/i915/ptl: Define IS_PANTHERLAKE macro

From: Dnyaneshwar Bhadane Common display code requires IS_PANTHERLAKE macro. Define the macro and set 0 as PTL is no longer support for i915. Signed-off-by: Dnyaneshwar Bhadane Signed-off-by: Matt Atwood Signed-off-by: Clint Taylor Reviewed-by: Matt Roper --- drivers/gpu/drm/i915

[PATCH] drm/i915/display: HDMI C10 PLL entry for 265250 MHz

Add PLL values for 265.250MHz pixel clock to support recent 3440x1440 monitors. Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915

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