but it would be consistent.
Feel free to change the name or leave it. The code appears to match the
current BSPEC table.
Reviewed-by: Clint Taylor
-Clint
+ /* NT mV Trans mV db*/
+ { 0xA, 0x32, 0x3F, 0x00, 0x00 },/* 350
Appears to match latest BSPEC
Reviewed-by: Clint Taylor
-Clint
On 9/3/21 5:35 PM, Matt Roper wrote:
From: Lucas De Marchi
Like DG1, XeHP SDV doesn't have LLC/eDRAM control values due to being a
dgfx card. XeHP SDV adds 2 more bits: L3_GLBGO to "push the Go point to
memory for L
drm_dbg_kms(&dev_priv->drm,
+ "plane %d pitch (%d) must be power of two for
tiled buffers\n",
+ i, mode_cmd->pitches[i]);
+ goto err;
+ }
+
Reviewed-by: Clint T
Reviewed-by: Clint Taylor
-Clint
On 5/14/21 8:10 PM, Matt Roper wrote:
From: Anusha Srivatsa
When scalers are enabled, we need to program underrun
bubble counter to 0x50 to avoid Soft Pipe A underruns.
Make sure other bits dont get overwritten.
Cc: Matt Roper
Cc: Clint Taylor
Cc: José
Reviewed-by: Clint Taylor
-Clint
On 5/14/21 8:10 PM, Matt Roper wrote:
From: Anusha Srivatsa
The clocks in ALD_P is similar to that of TGL.
The combo PLLs use the same DPLL0, DPLL1 and TBT_PLL.
This patch adds the helper function intel_mg_pll_enable_reg()
which is similar to
Values match current BSPEC.
Reviewed-by: Clint Taylor
-Clint
On 5/14/21 8:10 PM, Matt Roper wrote:
From: Mika Kahola
Define and use DP voltage swing and pre-emphasis translation tables
for ADL-P.
v2:
- Update according to recent bspec updates; there are now separate
tables for RBR
_unblock(dig_port, wakeref);
+ mutex_unlock(&dig_port->tc_lock);
drm_WARN_ON(&i915->drm, val == 0xffff);
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ld(struct intel_digital_port
*dig_port);
void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy);
+bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port);
+
#endif /* __INTEL_TC_H__ */
Reviewed-by: Clint Taylor
-Clint
_
ls = max_t(u8, 1, dev_priv->dram_info.num_channels);
int deinterleave;
int ipqdepth, ipqdepthpch;
int dclk_max;
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dig_port->base.port != PORT_A)
+ if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
return;
/*
Reviewed-by: Clint Taylor
-Clint
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anscoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) {
drm_dbg_kms(&dev_priv->drm,
"PSR2 not supported in transcoder %s\n",
Reviewed-by: Clint Taylor
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Reviewed-by: Clint Taylor
-Clint
On 2/8/19 12:05, Ville Syrjala wrote:
From: Ville Syrjälä
Currently we're only dumping out the ddb allocation changes, let's do
the same for the watermarks. This should help with debugging underruns
and whatnot.
First I tried one line per pl
On 11/30/2018 03:15 PM, Imre Deak wrote:
On Fri, Nov 30, 2018 at 02:58:01PM -0800, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence.
BSpec: 21257
Cc: Ville Syrjälä
On 12/03/2018 04:19 AM, Ville Syrjälä wrote:
On Fri, Nov 30, 2018 at 02:58:01PM -0800, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
In August 2018 the BSPEC changed the ICL port programming sequence to
closely resemble earlier gen programming sequence.
BSpec: 21257
Cc: Ville
Oops, failure caused by ICL_PORT_TX_DW7 not being defined yet. Still
waiting on r-b for a patch that includes the DW7 definition.
-Clint
On 12/14/18 10:15, Patchwork wrote:
== Series Details ==
Series: drm/i915/dsi: Add PORT_TX_DW7 programming to DSI vswing sequence
URL : https://patchwor
matches BSPEC.
Reviewed-by: Clint Taylor
-Clint
On 1/13/22 8:04 AM, José Roberto de Souza wrote:
EHL table was recently updated with some minor fixes.
BSpec: 21257
Cc: Clint Taylor
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 10
Matches BSPEC for DKL Phy.
Reviewed-by: Clint Taylor
-Clint
On 1/13/22 9:48 AM, José Roberto de Souza wrote:
TC voltage swing programming sequence was updated with a new step.
BSpec: 54956
Cc: sta...@vger.kernel.org
Cc: Jani Nikula
Cc: Clint Taylor
Cc: Imre Deak
Signed-off-by: José
Reviewed-by: Clint Taylor
-Clint
On 11/2/21 3:25 PM, Matt Roper wrote:
The bspec's performance guide suggests programming specific values into
a few registers for optimal performance. Although these aren't
workarounds, it's easiest to handle them inside the GT workaround
f
Reviewed-by: Clint Taylor
-Clint
On 11/2/21 3:25 PM, Matt Roper wrote:
From: Stuart Summers
Add the initial set of workarounds for Xe_HP SDV.
There are some additional workarounds specific to the compute engines
that we're holding back for now. Those will be added later, after
ge
Looks correct.
Reviewed-by: Clint Taylor
-Clint
On 11/16/21 9:48 AM, Matt Roper wrote:
This workaround is documented a bit strangely in the bspec; it's listed
as an A0 workaround, but the description clarifies that the workaround
is implicitly handled by the hardware and what the d
Correct,
Reviewed-by: Clint Taylor
-Clint
On 11/16/21 9:48 AM, Matt Roper wrote:
Coarse power gating for render should not be enabled on some DG2
steppings.
Bspec: 52698
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_rc6.c | 15 +++
1 file changed, 11
Reviewed-by: Clint Taylor
-Clint
On 11/16/21 9:48 AM, Matt Roper wrote:
From: Ramalingam C
Invalidate IC cache through pipe control command as part of the ctx
restore flow through indirect ctx pointer.
v2:
- Move pipe control from xcs indirect context to the rcs indirect
context
Reviewed-by: Clint Taylor
-Clint
On 11/16/21 9:48 AM, Matt Roper wrote:
From: Matt Atwood
Extend existing workaround 1409120013 to DG2.
Cc: José Roberto de Souza
Signed-off-by: Matt Atwood
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
1 file changed, 2
image quality */
wa_masked_en(wal,
Reviewed-by: Clint Taylor
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On 04/11/2018 04:11 PM, Chris Wilson wrote:
Quoting clinton.a.tay...@intel.com (2018-04-12 00:13:26)
From: Clint Taylor
In commit dc911f5bd8aa ("drm/i915/edp: Allow alternate fixed mode for eDP
if available."), the patch was always selecting the alternate refresh rate
even though
On 03/13/2018 06:11 AM, Ville Syrjälä wrote:
On Tue, Mar 13, 2018 at 10:28:55AM +0100, Maarten Lankhorst wrote:
On fi-cnl-y3 we have 2 modes that differ only by crtc_clock. This means
that if we request the normal mode, we automatically get the downclocked
mode.
This can be seen during boot:
put buffer %s\n",
+ enable ? "enabling" : "disabling");
+
+ return -EIO;
}
EXPORT_SYMBOL(drm_dp_dual_mode_set_tmds_output);
Appears to fix the issue seen on GLK with LSPCON and DMC firmware
loaded. Customer was concerned about the fix being in D
(0x591C, info), /* Mobile GT2 */ \
KBL-R Y 2+2 should actually be labeled as ULX GT2 instead of Mobile GT2.
Of course this information is conveniently missing from the spec.
With that change:
Reviewed-by: Clint Taylor
-Clint
INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F
On 04/30/2018 12:49 AM, Jani Nikula wrote:
On Sat, 14 Apr 2018, "Vivi, Rodrigo" wrote:
On Apr 12, 2018, at 2:21 PM, Taylor, Clinton A
wrote:
On 04/11/2018 04:11 PM, Chris Wilson wrote:
Quoting clinton.a.tay...@intel.com (2018-04-12 00:13:26)
From: Clint Taylor
In commit dc
panel, the T12 panel timeout requirement is
being meet at >500ms during reboot and suspend/resume.
Cc: Clint Taylor
Cc: Paulo Zanoni
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_display.c
On 10/15/2018 04:31 AM, Jani Nikula wrote:
On Mon, 15 Oct 2018, Jani Nikula wrote:
On Fri, 05 Oct 2018, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
HDMI 2.0 594Mhz modes were incorrectly selecting 25.200Mhz Automatic N
value mode instead of HDMI specification values.
Signed-off
827: Gen9:all */
+ if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv))
return true;
return false;
Looks good.
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* warn since our MST HW readout is incomplete.
+*/
+ if (WARN_ON(is_mst))
+ return;
+ }
if (clk_enabled == !!encoder->base.crtc)
return;
Fixes the mDP lock up iss
attributes properly. Naturally, the workaround of reducing
main link attributes for all devices ended up in regressions for other
devices. So here we are.
Cc: Ville Syrjälä
Cc: Dhinakaran Pandiyan
Cc: Clint Taylor
Cc: Adam Jackson
Cc: Harry Wentland
Tested-by: Clinton Taylor
Signed-off-by: J
On 05/11/2017 02:57 AM, Jani Nikula wrote:
From: Clint Taylor
The Analogix 7737 DP to HDMI converter requires reduced M and N values
when to operate correctly at HBR2. Detect this IC by its OUI value of
0x0022B9 via the DPCD quirk list.
v2 by Jani: Rebased on the DP quirk database
Fixes
On 05/11/2017 03:03 AM, Jani Nikula wrote:
On Wed, 10 May 2017, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
The Analogix 7737 DP to HDMI converter requires reduced N and M values when
to operate correctly at HBR2. Detect this IC by its OUI value of 0x0022B9.
I'm not happy,
On 10/08/2018 03:33 AM, Ville Syrjälä wrote:
On Fri, Oct 05, 2018 at 03:18:44PM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Setting the SCDC scrambling CTS mode causes HDMI Link Layer protocol tests
HF1-12 and HF1-13 to fail. Added "Source Shall" entries from SC
On 10/15/2018 06:41 AM, Ville Syrjälä wrote:
On Fri, Oct 12, 2018 at 01:14:45PM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Initialize SCDC Source Version and TDMS_Config_0 registers to nominal
values during intel_hdmi_detect(). The i915 driver currently doesn't
impl
On 06/25/2018 03:33 AM, Imre Deak wrote:
On Wed, Jun 13, 2018 at 02:48:49PM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
On GLK NUC platforms the HDMI retiming buffer needs additional disabled
time to correctly sync to a faster incoming signal.
When measured on a scope the
On 06/29/2018 02:09 AM, Imre Deak wrote:
On Thu, Jun 28, 2018 at 11:14:30AM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
On GLK NUC platforms the HDMI retiming buffer needs additional disabled
time to correctly sync to a faster incoming signal.
When measured on a scope the
On 06/08/2018 06:31 AM, Imre Deak wrote:
Hi Clint,
nice debugging!
On Thu, Jun 07, 2018 at 04:12:39PM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
On GLK NUC platforms the HDMI retiming buffer needs additional disabled
time to correctly sync to a faster incoming signal
On 11/20/2015 05:55 AM, Ville Syrjälä wrote:
On Thu, Nov 19, 2015 at 09:20:16AM -0800, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Add SKL and KBL cdclk changes during modeset. Taking into account new
linkrates available using 8640 VCO.
Signed-off-by: Clint Taylor
---
drivers/gpu
> still trying to understand the flow but is "ctrl1"/"VCO" in this patch
written to DPLL_CTRL1 before we change the CD Clock ? if not then
it might be a bug and must be fixed as part of changes
here.
regards,
Sivakumar
On 2/10/2016 5:58 AM, clinton.a.t
On 02/12/2016 03:18 AM, Ville Syrjälä wrote:
On Thu, Feb 11, 2016 at 03:22:08PM -0800, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Track VCO frequency of SKL instead of the boot CDCLK and allow modeset
to set cdclk based on the max required pixel clock based on VCO
selected.
The vco
On 02/25/2016 05:49 AM, Ville Syrjälä wrote:
On Tue, Feb 16, 2016 at 09:44:55AM -0800, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Set cdclk based on the max required pixel clock based on VCO
selected. Track boot vco instead of boot cdclk.
The vco is now tracked at the atomic level
matches the kernels entries. Thanks.
Reviewed-by: Clint Taylor
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On 03/10/2016 12:08 AM, Maarten Lankhorst wrote:
Op 09-03-16 om 22:58 schreef clinton.a.tay...@intel.com:
From: Clint Taylor
WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected
to DDI1 the system will hard hang during a cold boot. Occurs when DDI1
is enabled when the
On 03/16/2016 12:27 AM, Daniel Vetter wrote:
On Tue, Mar 15, 2016 at 02:34:05PM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
WARNING: Using ChromeOS with an eDP panel and a 4K@60 DP monitor connected
to DDI1 the system will hard hang during a cold boot. Occurs when DDI1
is
On 03/17/2016 02:18 PM, Rodrigo Vivi wrote:
On Wed, Mar 16, 2016 at 4:33 PM Clint Taylor mailto:clinton.a.tay...@intel.com>> wrote:
On 03/16/2016 12:27 AM, Daniel Vetter wrote:
> On Tue, Mar 15, 2016 at 02:34:05PM -0700,
clinton.a.tay...@intel.com <mailto:c
On 10/08/2015 05:44 AM, Ville Syrjälä wrote:
On Thu, Oct 08, 2015 at 03:39:26PM +0300, Jani Nikula wrote:
On Thu, 08 Oct 2015, Ville Syrjälä wrote:
On Wed, Oct 07, 2015 at 02:38:29PM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
The TMDS_296M define was computing as 296704
*/
{ 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
+
+ /* Dell Chromebook 11 (2015 version) */
+ { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
};
static void intel_init_quirks(struct drm_device *dev)
Reviewed-by: Clint Taylor
On 01/12/2016 05:21 AM, Ville Syrjälä wrote:
On Mon, Jan 11, 2016 at 01:52:17PM -0800, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Add reboot notifier for all platforms. This guarantees T12 delay
compliance during reboot cycles when pre-os enables the panel within
500ms.
Signed-off
es for all devices ended up in regressions for other
devices. So here we are.
v2: Rebase on DRM DP desc read helpers
Cc: Ville Syrjälä
Cc: Dhinakaran Pandiyan
Cc: Clint Taylor
Cc: Adam Jackson
Cc: Harry Wentland
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_dp_hel
main link attributes for all devices ended up in
regressions for other devices. So here we are.
v2: Rebase on DRM DP desc read helpers
v3: Fix the OUI memcmp blunder (Clint)
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Cc: Ville Syrjälä
Cc: Dhinakaran Pandiyan
Cc: Clint Taylor
On 05/30/2017 12:11 AM, Jani Nikula wrote:
On Tue, 30 May 2017, Hans Verkuil wrote:
On 05/29/2017 09:00 PM, Daniel Vetter wrote:
On Fri, May 26, 2017 at 12:20:48PM +0200, Hans Verkuil wrote:
On 05/26/2017 09:15 AM, Daniel Vetter wrote:
Did you look into also wiring this up for dp mst chain
On 05/29/2017 04:06 AM, Jani Nikula wrote:
On Thu, 18 May 2017, Clint Taylor wrote:
On 05/18/2017 04:10 AM, Jani Nikula wrote:
Face the fact, there are Display Port sink and branch devices out there
in the wild that don't follow the Display Port specifications, or they
have bugs, or
On 05/30/2017 09:49 AM, Hans Verkuil wrote:
On 05/30/2017 04:19 PM, Clint Taylor wrote:
On 05/30/2017 12:11 AM, Jani Nikula wrote:
On Tue, 30 May 2017, Hans Verkuil wrote:
On 05/29/2017 09:00 PM, Daniel Vetter wrote:
On Fri, May 26, 2017 at 12:20:48PM +0200, Hans Verkuil wrote:
On 05
On 05/30/2017 09:54 AM, Hans Verkuil wrote:
On 05/30/2017 06:49 PM, Hans Verkuil wrote:
On 05/30/2017 04:19 PM, Clint Taylor wrote:
On 05/30/2017 12:11 AM, Jani Nikula wrote:
On Tue, 30 May 2017, Hans Verkuil wrote:
On 05/29/2017 09:00 PM, Daniel Vetter wrote:
On Fri, May 26, 2017 at
On 05/30/2017 02:29 PM, Hans Verkuil wrote:
On 05/30/2017 10:32 PM, Clint Taylor wrote:
On 05/30/2017 09:54 AM, Hans Verkuil wrote:
On 05/30/2017 06:49 PM, Hans Verkuil wrote:
On 05/30/2017 04:19 PM, Clint Taylor wrote:
On 05/30/2017 12:11 AM, Jani Nikula wrote:
On Tue, 30 May 2017
On 05/26/2017 12:18 AM, Daniel Vetter wrote:
On Thu, May 25, 2017 at 05:06:25PM +0200, Hans Verkuil wrote:
From: Hans Verkuil
This adds support for the DisplayPort CEC-Tunneling-over-AUX
feature that is part of the DisplayPort 1.3 standard.
Unfortunately, not all DisplayPort/USB-C to HDMI a
Reviewed-by: Clinton Taylor
-Clint
On 05/30/2017 03:42 PM, Rodrigo Vivi wrote:
As for BXT, PP_DIVISOR was removed from CNP PCH and power
cycle delay has been moved to PP_CONTROL.
Cc: Jani Nikula
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_dp.c | 10 +-
1 file chang
On 05/31/2017 03:16 AM, Jani Nikula wrote:
Print DID not VID on the DID error path. Looks like a copy-paste error
from the VID error path. Clarify and clean up error logging, making them
distinguishable from each other, while at it.
Reviewed-by: Clinton Taylor
-Clint
Reported-by: Petru M
On 04/06/2017 12:15 PM, Rodrigo Vivi wrote:
Platform enabling and its power-on are organized in different
skus (U x Y x S x H, etc). So instead of organizing it in
GT1 x GT2 x GT3 let's also use the platform sku.
This is also the new Spec style what makes the review much
more easy and straight
On 06/07/2017 10:55 AM, Ville Syrjälä wrote:
On Wed, Jun 07, 2017 at 10:45:25AM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
RGB565 Pixel format planes can now be rotated at 90 and 270 degrees
"now" == since when?
GLK, I will update the commit message to be mor
On 06/08/2017 04:45 AM, Szwichtenberg, Radoslaw wrote:
On Wed, 2017-06-07 at 10:45 -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
RGB565 Pixel format planes can now be rotated at 90 and 270 degrees
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915/intel_atomic_plane.c
Matches pseudo code in BSpec.
Reviewed-by: Clint Taylor
On 06/08/2017 04:03 PM, Rodrigo Vivi wrote:
From: "Kahola, Mika"
Enable wrpll computation for Cannonlake platform to support
pll's required for HDMI output. The patch contains the following features
- compute Cannon
(0x3E9B, info), /* Halo GT2 */ \
+ INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */
+
Device ID's Matches current documentation
Reviewed-by: Clint Taylor
#define INTEL_CFL_IDS(info) \
- INTEL_CFL_S_IDS(info)
+ INTEL_CFL_S_IDS(info), \
+ INTEL_CFL_H_IDS(info)
#
), /* SRV GT1 */ \
+ INTEL_VGA_DEVICE(0x3E93, info), /* SRV GT1 */ \
+ INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \
+ INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \
+ INTEL_VGA_DEVICE(0x3E96, info) /* SRV GT2 */
+
Matches current documentation
Reviewed-by: Clint Taylor
On 06/21/2017 09:34 AM, Anusha Srivatsa wrote:
From: anushasr
Follow the spec and add ID for U SKU
v2: Update IDs.
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
lib/i915_pciids.h | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/lib/i915_pciids.h b/lib/i
On 06/21/2017 09:39 AM, Anusha Srivatsa wrote:
Add the PCI IDs for U SKU IN CFL by following the spec.
v2: Update IDs
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
intel/intel_chipset.h | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/intel/intel_chi
On 06/22/2017 09:28 AM, Anusha Srivatsa wrote:
From: anushasr
Follow the spec and add ID for U SKU
v2: Update IDs in accordance to the kernel commit:
d29fe702c9cb682df99146d24d06e5455f043101 (Chris)
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
lib/i915_pciids.h | 9 -
1
On 06/21/2017 09:39 AM, Anusha Srivatsa wrote:
Add the PCI IDs for S SKU IN CFL by following the spec.
v2: Update IDs.
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
intel/intel_chipset.h | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/intel/int
On 06/21/2017 09:39 AM, Anusha Srivatsa wrote:
Add the PCI IDs for H SKU IN CFL by following the spec.
v2: Update IDs
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
intel/intel_chipset.h | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/intel/intel_chipset.h
On 06/21/2017 09:39 AM, Anusha Srivatsa wrote:
Add the PCI IDs for U SKU IN CFL by following the spec.
v2: Update IDs
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
intel/intel_chipset.h | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/intel/intel_chi
Looks Good.
Reviewed-by: Clinton Taylor
-Clint
On 06/28/2017 05:14 PM, Manasi Navare wrote:
This patch fixes the DP AUX CH timeouts observed during CI IGT
tests thus fixing the CI failures. This is done by adding a
quirk for a particular PCI device that requires the panel power
cycle delay (
Identical to other platforms.
Reviewed-by: Clinton Taylor
On 06/29/2017 10:18 AM, Rodrigo Vivi wrote:
Coffeelake is a Intel® Processor containing Intel® HD Graphics
following Kabylake.
It is Gen9 graphics based platform on top of CNP PCH.
On following patches we will start adding PCI IDs and
Reviewed-by: Clinton Taylor
-Clint
On 06/29/2017 02:18 PM, Rodrigo Vivi wrote:
Platform enabling and its power-on are organized in different
skus (U x Y x S x H, etc). So instead of organizing it in
GT1 x GT2 x GT3 let's also use the platform sku.
This is also the new Spec style what makes t
Matches i915 support PCI device IDs
Reviewed-by: Clinton Taylor
-Clint
On 06/29/2017 02:18 PM, Rodrigo Vivi wrote:
By the Spec all CNL Y skus are 2+2, i.e. GT2.
This is a copy of merged i915's
commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.")
v2: Based on Anusha's ke
Reviewed-by: Clinton Taylor
-Clint
On 06/29/2017 02:34 PM, Rodrigo Vivi wrote:
Platform enabling and its power-on are organized in different
skus (U x Y x S x H, etc). So instead of organizing it in
GT1 x GT2 x GT3 let's also use the platform sku.
This is a copy of merged i915's
commit e918
Reviewed-by: Clinton Taylor
-Clint
On 06/29/2017 02:34 PM, Rodrigo Vivi wrote:
By the Spec all CNL Y skus are 2+2, i.e. GT2.
This is a copy of merged i915's
commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.")
v2: Add kernel commit id for reference.
Cc: Anusha Srivatsa
Reviewed-by: Clinton Taylor
-Clint
On 07/06/2017 02:01 PM, Rodrigo Vivi wrote:
Cannonlake has same color setup as Geminilake.
Legacy color load luts doesn't work anymore on Cannonlake+.
Cc: Clint Taylor
Cc: Ander Conselvan de Oliveira
Signed-off-by: Rodrigo Vivi
---
drivers/gp
on VBT for
this information.
Cc: Clint Taylor
Signed-off-by: Rodrigo Vivi
---
drivers/gpu/drm/i915/intel_bios.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 639d45c..82b144c 100644
--- a/drivers/gp
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
-Clint
On 06/19/2017 11:10 PM, Vidya Srinivas wrote:
From: Chandra Konduru
This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling
On 06/19/2017 11:10 PM, Vidya Srinivas wrote:
From: Chandra Konduru
This patch adds NV12 to format_is_yuv() function and
made it available for both primary and sprite planes
small nit on the commit message:
static function in intel_sprite.c is not available to the primary
plane functio
On 06/19/2017 11:10 PM, Vidya Srinivas wrote:
From: Chandra Konduru
This patch updates scaler max limit support for NV12
v2: Rebased (me)
Needs rebase again.
Tested-by: Clinton Taylor
Reviewed-by: Clinton Taylor
Signed-off-by: Chandra Konduru
Signed-off-by: Nabendu Maiti
Signed-off-
On 06/19/2017 11:10 PM, Vidya Srinivas wrote:
From: Chandra Konduru
This patch adds NV12 to list of supported formats for
primary plane
v2: Rebased (Chandra Konduru)
v3: Rebased (me)
v4: Review comments by Ville addressed
Removed the skl_primary_formats_with_nv12 and
added
On 06/19/2017 11:10 PM, Vidya Srinivas wrote:
From: Chandra Konduru
This patch adds NV12 to list of supported formats for sprite plane.
v2: Rebased (me)
v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12 case in existing skl_plane_for
On 06/19/2017 11:10 PM, Vidya Srinivas wrote:
From: Chandra Konduru
This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.
v2:
-Fix an issue in checks added (Chandra Konduru)
v3: rebased (me)
v4: Review comments by Ville addressed
Added plat
On 07/09/2017 11:53 PM, Vidya Srinivas wrote:
From: Chandra Konduru
This patch adds NV12 to list of supported formats for sprite plane.
v2: Rebased (me)
v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12 case in existing skl_plane_for
On 07/11/2017 07:10 AM, Vidya Srinivas wrote:
From: Chandra Konduru
This patch adds NV12 to list of supported formats for sprite plane.
v2: Rebased (me)
v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12 case in existing skl_plane_for
On 07/12/2017 04:47 PM, Rodrigo Vivi wrote:
Version 1.05 is now available for CNL.
According to its release notes the only difference is:
- Change from aux A pwrreq always turn on during restore,
to saving and restoring aux A pwrreq.
Reviewed-by: Clinton Taylor
-Clint
Anusha Sriv
On 03/02/2018 10:10 AM, Rodrigo Vivi wrote:
On Thu, Mar 01, 2018 at 11:36:12AM -0800, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
DisplayPort Phy compliance test patterns register definitions.
Hi Clint,
what's the current plan to add the actual use of these registers and
lf
Of clinton.a.tay...@intel.com
Sent: Friday, August 4, 2017 9:23 PM
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH i-g-t] tests/kms: increase max threshold time for
edid read
From: Clint Taylor
Current 50ms max threshold timing for an EDID read is very close to the
actual time fo
ls.
/Marta
-Original Message-
From: Taylor, Clinton A
Sent: Thursday, August 10, 2017 1:52 AM
To: intel-gfx@lists.freedesktop.org
Cc: Taylor, Clinton A ; Vetter, Daniel
; Lofstedt, Marta
Subject: [PATCH v3 i-g-t] tests/kms: increase max threshold time for
edid read
From: Clint Taylor
Curre
time for edid
read
From: Clint Taylor
Current 50ms max threshold timing for an EDID read is very close to the
actual time for a 2 block HDMI EDID read. Adjust the timings base on
connector type as DP reads are at 1 MBit and HDMI at 100K bit. If an LSPcon is
connected to device under test the -l
On 08/14/2017 07:40 AM, Daniel Vetter wrote:
On Thu, Aug 10, 2017 at 10:50:19AM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Current 50ms max threshold timing for an EDID read is very close to the
actual time for a 2 block HDMI EDID read. Adjust the timings base on
connector
On 08/15/2017 12:58 AM, Daniel Vetter wrote:
On Mon, Aug 14, 2017 at 10:21:51AM -0700, Clint Taylor wrote:
On 08/14/2017 07:40 AM, Daniel Vetter wrote:
On Thu, Aug 10, 2017 at 10:50:19AM -0700, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Current 50ms max threshold timing for an
This patch fixes the alignment. I spotted another issue with teh
structure and will fix it once this one is merged.
Reviewed-by: Clint Taylor
Tested-by: Clint Taylor
On 08/16/2017 07:20 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
Fix decoding of the start of the child
On 08/16/2017 02:19 PM, Rodrigo Vivi wrote:
It seems this quirk is randomly masking the real issue.
It could be masking the real issue. The most likely cause of this issue
is a slow power fall off to the panel when the PPS requests power-off.
We would need physical access to the platform itse
On 03/23/2017 05:30 AM, Jani Nikula wrote:
On Thu, 23 Mar 2017, clinton.a.tay...@intel.com wrote:
From: Clint Taylor
Several major vendor USB-C->HDMI converters fail to recover a 5.4 GHz 1 lane
signal if the Data Link N is greater than 0x8.
Patch detects when 1 lane 5.4 GHz signal
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