DPIO name still using old name. Change it according to the driver name.
Signed-off-by: Chon Ming Lee
---
tools/quick_dump/vlv_dpio.txt | 104 +-
1 file changed, 51 insertions(+), 53 deletions(-)
diff --git a/tools/quick_dump/vlv_dpio.txt b/tools
The extra parameter is for future platform.
Signed-off-by: Chon Ming Lee
---
lib/intel_dpio.c | 19 +++
lib/intel_gpu_tools.h | 4 ++--
tools/intel_dpio_read.c| 2 +-
tools/intel_dpio_write.c | 2 +-
tools/quick_dump/chipset.i | 4
Future platform require the phy input to determine which PHY to target for.
Signed-off-by: Chon Ming Lee
---
lib/intel_iosf.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/lib/intel_iosf.c b/lib/intel_iosf.c
index f57212f..0c9f4d8 100644
--- a/lib
eDP 1.4 supports 4-5 extra link rates in additional to current 2 link
rate. Create a structure to store the DPLL divisor data to improve
readability.
Signed-off-by: Chon Ming Lee
---
drivers/gpu/drm/i915/intel_dp.c | 48 +++---
1 files changed, 24 insertions
For DP pll settings, there is only two golden configs. Instead of running
through the algorithm to determine it, hardcode the value and get it
determine in intel_dp_set_clock.
Signed-off-by: Chon Ming Lee
---
drivers/gpu/drm/i915/intel_display.c | 22 --
drivers/gpu/drm
-off-by: Chon Ming Lee
---
drivers/gpu/drm/i915/intel_dp.c | 65 ++-
1 files changed, 37 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2151d13..fd09058 100644
--- a/drivers/gpu/drm/i915
For DP pll settings, there is only two golden configs. Instead of
running through the algorithm to determine it, hardcode the value and get it
determine in intel_dp_set_clock.
v2: Rework on the intel_limit compiler warning. (Jani)
Signed-off-by: Chon Ming Lee
---
drivers/gpu/drm/i915
The additional pipe parameter will use to select which phy to target
for.
Signed-off-by: Chon Ming Lee
---
drivers/gpu/drm/i915/i915_debugfs.c | 18 ++--
drivers/gpu/drm/i915/i915_drv.h |4 +-
drivers/gpu/drm/i915/intel_display.c | 51
The patch doesn't contain functional change, but is to prepare for
future platform which has different DPIO phy. The additional pipe
parameter will use to select which phy to target for.
Signed-off-by: Chon Ming Lee
v2: Update the commit message and add static for the new function.
(Jani/
fails to work. The patch add some
missing init code, such as doing a DPIO CMNRESET and program the GMBUS
frequency.
Signed-off-by: Chon Ming Lee
---
drivers/gpu/drm/i915/i915_reg.h |8 +
drivers/gpu/drm/i915/intel_display.c | 51 ++
2 files change
i915 fails to work. The patch add some
missing init code, such as doing a DPIO CMNRESET and program the GMBUS
frequency.
Chon Ming Lee (2):
drm/i915: Send a DPIO cmnreset during driver load or system resume.
drm/i915: Program GMBUS Frequency based on the CDCLK
drivers/gpu/drm/i915/i915_
Without the DPIO cmnreset, the PLL fail to lock. This should have
done by BIOS.
v2: Move this to intel_uncore_sanitize to allow it to get call during
resume path. (Daniel)
Signed-off-by: Chon Ming Lee
---
drivers/gpu/drm/i915/intel_uncore.c | 15 +++
1 files changed, 15
CDCLK is used to generate the gmbus clock. This is normally done by
BIOS. This is only for valleyview platform.
v2: Move this to intel_i2c_reset to allow reprogram the gmbus frequency
during resume. (Daniel)
Signed-off-by: Chon Ming Lee
---
drivers/gpu/drm/i915/i915_reg.h |8
/media well may still power gated.
Turn it off.
Signed-off-by: Chon Ming Lee
---
drivers/gpu/drm/i915/i915_reg.h |9 +
drivers/gpu/drm/i915/intel_uncore.c | 23 +++
2 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
uency. (Ville)
Add get_disp_clk_div, which can use to get cdclk/czclk divide.
Signed-off-by: Chon Ming Lee
---
drivers/gpu/drm/i915/i915_reg.h |8 +
drivers/gpu/drm/i915/intel_i2c.c | 60 ++
2 files changed, 68 insertions(+), 0 deletions(-)
/media well may still power gated.
Turn it off.
Signed-off-by: Chon Ming Lee
---
drivers/gpu/drm/i915/i915_reg.h |9 +
drivers/gpu/drm/i915/intel_uncore.c | 23 +++
2 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h
uency. (Ville)
Add get_disp_clk_div, which can use to get cdclk/czclk divide.
Signed-off-by: Chon Ming Lee
---
drivers/gpu/drm/i915/i915_reg.h |8 +
drivers/gpu/drm/i915/intel_i2c.c | 60 ++
2 files changed, 68 insertions(+), 0 deletions(-)
Fix the typo in previous commit for DP 1.62 divisor.
drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2
Reported-by: Jesse Barnes
Signed-off-by: Chon Ming Lee
---
drivers/gpu/drm/i915/intel_dp.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a
Fix the typo in previous commit for DP 1.62 divisor.
drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2
v2: sigh, the m1 div is 3.
Reported-by: Jesse Barnes
Signed-off-by: Chon Ming Lee
---
drivers/gpu/drm/i915/intel_dp.c |2 +-
1 files changed, 1 insertions(+), 1
igned-off-by: Chon Ming Lee
---
drivers/gpu/drm/i915/i915_reg.h |8 +
drivers/gpu/drm/i915/intel_i2c.c | 57 ++
2 files changed, 65 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a0
has been selected. Jesse DPIO reset patch
which toggle the cmnreset in intel_modeset_init_hw() should handle it.
(Ville)
Signed-off-by: Chon Ming Lee
---
drivers/gpu/drm/i915/i915_reg.h |9 +
drivers/gpu/drm/i915/intel_uncore.c | 16
2 files changed, 25
There is no functional change on this patch. Only rename several
hdmi encoder function name which suppose to use only by valleyview from
intel_hdmi_pre_pll_enable to vlv_hdmi_pre_pll_enable, and etc.
Signed-off-by: Chon Ming Lee
---
drivers/gpu/drm/i915/intel_hdmi.c | 12 ++--
1
vlv_dpio_read/write should be describe more in PHY centric instead of
display controller centric.
Create a enum dpio_channel for channel index and enum dpio_phy for PHY
index. This should better to gather for upcoming platform.
Suggested-by: Ville Syrjälä
Signed-off-by: Chon Ming Lee
Incorrect definition DPIO_TX3_SWING_CTL4.
Signed-off-by: Chon Ming Lee
---
drivers/gpu/drm/i915/i915_reg.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6799d53..f7ecad2 100644
--- a/drivers/gpu
Group access to TX lane 0 to 3 for TX DWORD 0
VLV_TX0_DW0 - Refer to TX Lane 0 access only for TX DWORD 0.
There is no functional change on this patch.
Suggested-by: Ville Syrjälä
Signed-off-by: Chon Ming Lee
---
drivers/gpu/drm/i915/i915_debugfs.c | 40
drivers/gpu/drm/i915/i915_
register define.
Suggested-by: Ville Syrjälä
Signed-off-by: Chon Ming Lee
---
drivers/gpu/drm/i915/i915_drv.h | 13 +
drivers/gpu/drm/i915/i915_reg.h |2 ++
drivers/gpu/drm/i915/intel_display.c | 16
drivers/gpu/drm/i915/intel_dp.c |9
register define.
v3: Rename vlv_phy to dpio_phy_iosf_port and define additional macro
DPIO_PHY, and remove unrelated change. (Ville)
Suggested-by: Ville Syrjälä
Signed-off-by: Chon Ming Lee
---
drivers/gpu/drm/i915/i915_drv.h | 13 +
drivers/gpu/drm/i915/i915_reg.h |3
Group access to TX lane 0 to 3 for TX DWORD 0
VLV_TX0_DW0 - Refer to TX Lane 0 access only for TX DWORD 0.
There is no functional change on this patch.
v2: Rebase based on previous patch change.
Suggested-by: Ville Syrjälä
Signed-off-by: Chon Ming Lee
---
drivers/gpu/drm/i915/i915_debugfs.c |
arify. Fix up some mismatch start DW
for second PLL block. (Ville)
Suggested-by: Ville Syrjälä
Signed-off-by: Chon Ming Lee
---
drivers/gpu/drm/i915/i915_debugfs.c | 40
drivers/gpu/drm/i915/i915_reg.h | 191 --
drivers/gpu/drm/i915/intel_disp
The max frequency reporting is not correct. But there is already an existing
valleyview_rps_max_freq and valleyview_rps_min_freq to get the
frequency. Use that for i915_cur_delayinfo.
Signed-off-by: Chon Ming Lee
---
drivers/gpu/drm/i915/i915_debugfs.c |4 ++--
1 files changed, 2
Ming Lee
---
drivers/gpu/drm/i915/intel_pm.c |7 +--
1 files changed, 1 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a5778e5..13fb7f8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
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